Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3CFC4ABBB0; Thu, 17 Sep 2026 19:02:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789671746; cv=none; b=KIzdVyfzakpWpxwkAup346bjCtWLy8vvbBltH+txpXsndBz4YEX0KUej3eAYPykeOhl2CRURd6a1hWIm1GhoccicmWMNBwbipZ8wTFaRqGo/FZ2OSe7tJ5RLYXJJ4OEe603MBoRTFQXgjR4O+ypbz7JWcWooZzQT4tcx1h72GdE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789671746; c=relaxed/simple; bh=dQwLC9E3Sa2AB4CJVJnjso8SAoxUcIxoQNuPMe3QcCM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ebQGxK2Lvb03GpPrQJOpgL5DBmYieR7GM9xa1Ckk11mmRGtgPDsHiMK5JH43D2lujGWklfrtWmKgMhf92lV43WG2ECoBq4QUKuPHj5yQZicJ83f8eysrnttTI27H6y9z0g4gBH/d9aPRWMrnckSEIKlqOSrEajNpEiV1u3tzuck= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=O8EEr2fw; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="O8EEr2fw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D16761F00893; Thu, 17 Sep 2026 19:02:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1789671745; bh=1z6sT3XgjWcm9ODHKyksHwme1t733YJM4EFIkxZcJ+I=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=O8EEr2fwy5QhX2LerD/Yg8O21JEG58ryOgyzVl5kNUX5g3AV2yDcj9pGlvUREXRer FVHJ793mkwhiqBVV+gHQu9MzdgvNmyG1Q+UThv1rYZlykzyEKJ7j329kxmTMfdr4sk XcMR8RUuGgNUeSA35YatYQdmRNJXdUaxK6645Am4= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Terry Bowman , Jonathan Cameron , Dave Jiang , Richard Cheng , Alison Schofield , Sasha Levin Subject: [PATCH 6.12 1075/1102] cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register Date: Thu, 17 Sep 2026 16:16:58 +0100 Message-ID: <20260917151607.826064979@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260917151539.408551884@linuxfoundation.org> References: <20260917151539.408551884@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Terry Bowman [ Upstream commit 9d399526128bae184b153deab42b49f5f3eea2ed ] cxl_rch_get_aer_severity() classifies RCH Downstream Port uncorrectable errors as fatal or non-fatal by ANDing uncorrectable status with PCI_ERR_ROOT_FATAL_RCV. This is wrong because PCI_ERR_ROOT_FATAL_RCV is a Root Error Status register bit (bit 6), not a severity bit. ANDing it against uncorrectable status tests a reserved bit and produces incorrect severity classification. Fix by ANDing the unmasked uncor_status against uncor_severity. Per PCIe Base Spec r6.0 Section 7.8.4.4, each bit in the Uncorrectable Error Severity register indicates whether the corresponding error is fatal (1) or non-fatal (0). Fixes: 6ac07883dbb5 ("cxl/pci: Add RCH downstream port error logging") Cc: stable@vger.kernel.org Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Richard Cheng Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260803221810.3685703-3-terry.bowman@amd.com Signed-off-by: Dave Jiang Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/cxl/core/ras_rch.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -94,11 +94,11 @@ static bool cxl_rch_get_aer_info(void __ static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, int *severity) { - if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { - if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) - *severity = AER_FATAL; - else - *severity = AER_NONFATAL; + u32 uncor_status = aer_regs->uncor_status & ~aer_regs->uncor_mask; + + if (uncor_status) { + *severity = (uncor_status & aer_regs->uncor_severity) ? + AER_FATAL : AER_NONFATAL; return true; }