From: Andrew Gigena Date: Wed, 04 Nov 2026 18:38:13 +0000 Subject: [PATCH v2 2/2] arm64: dts: qcom: sm8150: Use standalone ICE node for UFS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261104-sm8150-ice-rfc-v2-2-d697bbce0278@andrewgigena.dev> References: <20261104-sm8150-ice-rfc-v2-0-d697bbce0278@andrewgigena.dev> In-Reply-To: <20261104-sm8150-ice-rfc-v2-0-d697bbce0278@andrewgigena.dev> To: Abel Vesa , Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Alim Akhtar , Bart Van Assche , Bean Huo , Stanley Jhu , Bjorn Andersson , Andy Gross , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Andrew Gigena X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793817503; l=2613; i=mail@andrewgigena.dev; s=20261104; h=from:subject:message-id; bh=WlKNWLgTKrbe/21NLFWi4EX5Ly7RQNJI7RvyIEWjaMI=; b=a1nAxirKiAJiQ/12HZ3XDuVxxAvfW9Z8hM8ms+EoxVWLhaCPZPHg43hXKoKNt4udsKIMN2QpI w8Km050FwcaBD9DXTuzim5qYMjdt9khW9TidgKjwro6cV5u9sGV+VTB X-Developer-Key: i=mail@andrewgigena.dev; a=ed25519; pk=OMhlYIBaOEC8g4mJ4JCKy7kbg+lrwRxuujieZF8Ne6U= X-Endpoint-Received: by B4 Relay for mail@andrewgigena.dev/20261104 with auth_id=1402 List-Id: B4 Relay Submissions Convert SM8150 UFS to use a standalone ICE node. Move the ICE register region and clock from the UFS controller node into a dedicated ICE node. Reference the new node from the UFS controller using the qcom,ice property. This brings the SM8150 device tree in line with the standalone ICE representation used on newer Qualcomm platforms. Signed-off-by: Andrew Gigena Tested-by: Andrew Gigena --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 293fcbacff34..b3d6f3d92395 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2071,9 +2071,7 @@ pcie1_phy: phy@1c0e000 { ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; + reg = <0 0x01d84000 0 0x2500>; interrupts = ; phys = <&ufs_mem_phy>; phy-names = "ufsphy"; @@ -2092,8 +2090,7 @@ ufs_mem_hc: ufshc@1d84000 { "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; + "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -2102,8 +2099,7 @@ ufs_mem_hc: ufshc@1d84000 { <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <37500000 300000000>, <0 0>, @@ -2112,8 +2108,8 @@ ufs_mem_hc: ufshc@1d84000 { <0 0>, <0 0>, <0 0>, - <0 0>, - <0 300000000>; + <0 0>; + qcom,ice = <&ice>; status = "disabled"; }; @@ -2139,6 +2135,17 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; }; + ice: crypto@1d90000 { + compatible = "qcom,sm8150-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>; -- 2.56.0