From: Alex Ousherovitch Date: Tue, 10 Nov 2026 08:52:27 -0800 Subject: [PATCH v8 1/5] dt-bindings: crypto: add Rambus CryptoManager Hub MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261110-cmh-b4-a-v8-v8-1-4cea8ebc1d40@rambus.com> References: <20261110-cmh-b4-a-v8-v8-0-4cea8ebc1d40@rambus.com> In-Reply-To: <20261110-cmh-b4-a-v8-v8-0-4cea8ebc1d40@rambus.com> To: Saravanakrishnan Krishnamoorthy , Joel Wittenauer , Thi Nguyen , Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Shuah Khan , Randy Dunlap Cc: linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Alex Ousherovitch X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794329557; l=7393; i=aousherovitch@rambus.com; s=20261026; h=from:subject:message-id; bh=GZqVAWebmgss8+gw8k3vCH3UdrGSwgvS1FtLn9Ky7Zw=; b=S6J25R7zxk+xl8R1ue6YSlJBzcC9fgv2M41Whi/3Q1w+II+2iN1eTkw1ggL6I4HdEoDNM9lSX dmmrVo7glXwAq6gXMflVIo2OGh910S+ZjD6yV1aOYmxNqrtOj8H61DH X-Developer-Key: i=aousherovitch@rambus.com; a=ed25519; pk=ECFtTdQUPAolK+qGZ6v7Xm3sRf7rnM7wxpTeFzbqpmA= X-Endpoint-Received: by B4 Relay for aousherovitch@rambus.com/20261026 with auth_id=1330 List-Id: B4 Relay Submissions Add device tree binding schema for the Rambus CryptoManager Hub (CMH) hardware crypto accelerator. The binding describes the parent SoC-level node with its SIC register region and one queue@N child node per mailbox the host owns, each carrying a reg (mailbox instance index), an optional interrupt, VCQ ring geometry (rambus,num-slots / rambus,slot-stride-bytes) and a rambus,cores affinity list. Which crypto cores are present is discovered from the SIC CORE_ENABLE register at probe, not described in the device tree. Register the 'rambus' vendor prefix for Rambus Inc. Co-developed-by: Saravanakrishnan Krishnamoorthy Signed-off-by: Saravanakrishnan Krishnamoorthy Signed-off-by: Alex Ousherovitch --- .../bindings/crypto/rambus,cmh-v1030.yaml | 145 +++++++++++++++++++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + 2 files changed, 147 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/rambus,cmh-v1030.yaml b/Documentation/devicetree/bindings/crypto/rambus,cmh-v1030.yaml new file mode 100644 index 000000000000..eef82c2d7179 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/rambus,cmh-v1030.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/rambus,cmh-v1030.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rambus CryptoManager Hub (CMH) Hardware Crypto Accelerator + +maintainers: + - Alex Ousherovitch + - Saravanakrishnan Krishnamoorthy + - Joel Wittenauer + +description: | + The Rambus CryptoManager Hub (CMH) is a hardware cryptographic accelerator + accessed via a mailbox-based VCQ (Virtual Command Queue) interface. The + host writes VCQ command sequences into per-mailbox DMA queue buffers and + rings a doorbell; the CMH eSW processes them and signals completion via + interrupt. + + The management host statically partitions the hardware mailboxes across + the SoC's host interfaces at integration time; the set of mailboxes a + given host owns is therefore fixed and not runtime-discoverable (a + mailbox locked to a host reads as unavailable in the SIC availability + register). Each owned mailbox is described by a child node. Which + crypto cores are present is a fixed silicon-build property indicated by + the SIC CORE_ENABLE register, so cores are not described in the device + tree. Clock and reset are owned by the management host; a node + describing a non-management host has no clock or reset provider of its + own, so clocks and reset-gpios are optional. + + CMH gates access to a locked mailbox by a hardware HOST ID presented on + the bus with every access, permitting only the owning host's ID. An + integration must present a single, stable HOST ID for all accesses to a + given mailbox, independent of the issuing CPU (relevant on SMP hosts + whose interconnect encodes the issuing CPU in the HOST ID). + +properties: + compatible: + items: + - not: {} + description: SoC-specific compatible, e.g. vendor,soc-cmh + - const: rambus,cmh-v1030 + + reg: + maxItems: 1 + description: + SIC (System Interface Controller) MMIO region. The registers of + mailbox instance N are at offset N * 0x1000 within this region. + + clocks: + minItems: 1 + maxItems: 3 + description: + The "core" functional clock, and optionally the half-rate "core-div2" + clock (present only on configurations with side-channel-protected + cores) and/or the "rt" real-time tick clock. See clock-names for the + valid combinations. + + clock-names: + minItems: 1 + items: + - const: core + - enum: [core-div2, rt] + - const: rt + + reset-gpios: + maxItems: 1 + description: + Host-controlled reset for the CryptoManager Hub. The hub has two + external, active-low reset inputs -- a power-on reset and a hard + reset; where a board routes one of them to a host GPIO, that line is + described here. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^queue@[0-9a-f]+$": + type: object + description: + One node per hardware mailbox (VCQ command queue) this host owns. + The set of owned mailboxes is fixed by the management host at + integration time and enumerated here. + properties: + reg: + items: + - maximum: 63 + description: + 0-based mailbox instance index (0..63). The instance's + registers are at reg * 0x1000 within the SIC region. + + interrupts: + maxItems: 1 + description: Completion/error interrupt for this mailbox. + + rambus,num-slots: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, + 16384, 32768] + default: 64 + description: + Number of VCQ ring slots for this mailbox's command queue in + host DMA memory. This is a per-board, per-mailbox host-memory + ring geometry -- boards built around the same SoC (hence the + same compatible) may use different ring sizes, so it is + described per mailbox rather than derived from the compatible. + + rambus,slot-stride-bytes: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [512, 1024] + default: 512 + description: + Stride in bytes between consecutive VCQ ring slots for this + mailbox's command queue. Like rambus,num-slots this is a + per-board host-memory ring geometry, not derived from the + compatible. A slot must hold a complete command sequence, + which needs at least 512 bytes. + + rambus,cores: + $ref: /schemas/types.yaml#/definitions/string-array + items: + enum: [hc, aes, sm4, sm3, hcq, qse, pke, ccp] + description: | + Core-affinity list: the crypto cores whose work is dispatched to + this mailbox. A core may appear on at most one mailbox. Work + for cores not listed on any mailbox may be dispatched through + any mailbox. Optional (default: none -- the mailbox only + serves unlisted cores). + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 5471a06f93f1..66537d8f52e6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1411,6 +1411,8 @@ patternProperties: description: RaidSonic Technology GmbH "^ralink,.*": description: Mediatek/Ralink Technology Corp. + "^rambus,.*": + description: Rambus Inc. "^ramtron,.*": description: Ramtron International "^raspberrypi,.*": -- 2.43.7