Message-ID: <475B078E.7060809@kama-aina.net>
Date: Sat, 08 Dec 2007 11:07:26 -1000
From: Armin <akuster@kama-aina.net>
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Subject: [Qemu-devel] [Patch][Pxa2xx] Mainstone mmc support
Reply-To: qemu-devel@nongnu.org
To: qemu-devel@nongnu.org

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Hello,

Please consider this patch for inclusion.

This adds MMC and the rest of the FPGA irq definitions for the Mainstone II

Kind regards,
Armin

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 name="mainstone_mmci.patch"
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 filename="mainstone_mmci.patch"

Index: qemu/hw/mainstone.c
===================================================================
--- qemu.orig/hw/mainstone.c
+++ qemu/hw/mainstone.c
@@ -76,6 +76,10 @@ static void mainstone_common_init(int ra
     }
 
     mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);
+
+    /* MMC/SD host */
+    pxa2xx_mmci_handlers(cpu->mmc, mst_irq[MMC_IRQ], mst_irq[MMC_IRQ]);
+
     smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);
 
     arm_load_kernel(cpu->env, mainstone_ram, kernel_filename, kernel_cmdline,
Index: qemu/hw/mainstone.h
===================================================================
--- qemu.orig/hw/mainstone.h
+++ qemu/hw/mainstone.h
@@ -17,7 +17,20 @@
 #define MST_FLASH_1		0x04000000
 
 /* IRQ definitions */
-#define ETHERNET_IRQ	3
+#define MMC_IRQ       0
+#define USIM_IRQ      1
+#define USBC_IRQ      2
+#define ETHERNET_IRQ  3
+#define AC97_IRQ      4
+#define PEN_IRQ       5
+#define MSINS_IRQ     6
+#define EXBRD_IRQ     7
+#define S0_CD_IRQ     9
+#define S0_STSCHG_IRQ 10
+#define S0_IRQ        11
+#define S1_CD_IRQ     13
+#define S1_STSCHG_IRQ 14
+#define S1_IRQ        15
 
 extern qemu_irq
 *mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq);

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