Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LF927-00037y-9t for qemu-devel@nongnu.org; Tue, 23 Dec 2008 10:18:55 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LF924-00036O-7e for qemu-devel@nongnu.org; Tue, 23 Dec 2008 10:18:54 -0500 Received: from [199.232.76.173] (port=37043 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LF924-00036J-0c for qemu-devel@nongnu.org; Tue, 23 Dec 2008 10:18:52 -0500 Received: from pop-savannah.atl.sa.earthlink.net ([207.69.195.69]:58089) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LF923-0006Jx-L3 for qemu-devel@nongnu.org; Tue, 23 Dec 2008 10:18:51 -0500 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=[192.168.0.90]) by pop-savannah.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1LF922-0003B5-00 for qemu-devel@nongnu.org; Tue, 23 Dec 2008 10:18:50 -0500 Message-ID: <49510158.2070901@earthlink.net> Date: Tue, 23 Dec 2008 10:18:48 -0500 From: Robert Reif MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------080704000703030102020404" Subject: [Qemu-devel] [PATCH] add SuperSPARC breakpoint registers Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------080704000703030102020404 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit --------------080704000703030102020404 Content-Type: text/plain; name="breakpoint.diff.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="breakpoint.diff.txt" Index: target-sparc/cpu.h =================================================================== --- target-sparc/cpu.h (revision 6121) +++ target-sparc/cpu.h (working copy) @@ -300,6 +301,7 @@ uint32_t mmuregs[32]; uint64_t mxccdata[4]; uint64_t mxccregs[8]; + uint64_t mmubpregs[4]; uint64_t prom_addr; #endif /* temporary float registers */ Index: target-sparc/op_helper.c =================================================================== --- target-sparc/op_helper.c (revision 6121) +++ target-sparc/op_helper.c (working copy) @@ -953,6 +953,28 @@ case 0x39: /* data cache diagnostic register */ ret = 0; break; + case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ + { + int reg = (addr >> 8) & 3; + + switch(reg) { + case 0: /* Breakpoint Value (Addr) */ + ret = env->mmubpregs[reg]; + break; + case 1: /* Breakpoint Mask */ + ret = env->mmubpregs[reg]; + break; + case 2: /* Breakpoint Control */ + ret = env->mmubpregs[reg]; + break; + case 3: /* Breakpoint Status */ + ret = env->mmubpregs[reg]; + env->mmubpregs[reg] = 0ULL; + break; + } + DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret); + } + break; case 8: /* User code access, XXX */ default: do_unassigned_access(addr, 0, 0, asi, size); @@ -1283,9 +1305,30 @@ // descriptor diagnostic case 0x36: /* I-cache flash clear */ case 0x37: /* D-cache flash clear */ - case 0x38: /* breakpoint diagnostics */ case 0x4c: /* breakpoint action */ break; + case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ + { + int reg = (addr >> 8) & 3; + + switch(reg) { + case 0: /* Breakpoint Value (Addr) */ + env->mmubpregs[reg] = (val & 0xfffffffffULL); + break; + case 1: /* Breakpoint Mask */ + env->mmubpregs[reg] = (val & 0xfffffffffULL); + break; + case 2: /* Breakpoint Control */ + env->mmubpregs[reg] = (val & 0x7fULL); + break; + case 3: /* Breakpoint Status */ + env->mmubpregs[reg] = (val & 0xfULL); + break; + } + DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg, + env->mmuregs[reg]); + } + break; case 8: /* User code access, XXX */ case 9: /* Supervisor code access, XXX */ default: --------------080704000703030102020404--