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Date:	Mon, 01 Jun 2009 11:13:29 -0700
From:	David Daney <ddaney@caviumnetworks.com>
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To:	Florian Fainelli <florian@openwrt.org>,
	Ralf Baechle <ralf@linux-mips.org>
CC:	linux-mips@linux-mips.org
Subject: Re: [PATCH 4/9] mips: deal with larger physical offsets
References: <200906011359.47216.florian@openwrt.org>
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Florian Fainelli wrote:
> TI AR7 has larger physical offsets than other MIPS-based
> systems. A long jump to the target is required instead of
> a short jump like on other systems.
> 
> Signed-off-by: Eugene Konev <ejka@imfi.kspu.ru>
> Signed-off-by: Florian Fainelli <florian@openwrt.org>
> ---
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index e83da17..44f7141 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -1256,9 +1256,22 @@ void *set_except_vector(int n, void *addr)
>  
>  	exception_handlers[n] = handler;
>  	if (n == 0 && cpu_has_divec) {
> -		*(u32 *)(ebase + 0x200) = 0x08000000 |
> -					  (0x03ffffff & (handler >> 2));
> -		local_flush_icache_range(ebase + 0x200, ebase + 0x204);
> +		if ((handler ^ (ebase + 4)) & 0xfc000000) {
> +			/* lui k0, 0x0000 */
> +			*(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
> +			/* ori k0, 0x0000 */
> +			*(u32 *)(ebase + 0x204) =
> +					0x375a0000 | (handler & 0xffff);
> +			/* jr k0 */
> +			*(u32 *)(ebase + 0x208) = 0x03400008;
> +			/* nop */
> +			*(u32 *)(ebase + 0x20C) = 0x00000000;
> +			local_flush_icache_range(ebase + 0x200, ebase + 0x210);
> +		} else {
> +			*(u32 *)(ebase + 0x200) =
> +				0x08000000 | (0x03ffffff & (handler >> 2));
> +			local_flush_icache_range(ebase + 0x200, ebase + 0x204);
> +		}
>  	}
>  	return (void *)old_handler;
>  }
> 

I had to do a similar change for my mapped kernel patch.  However in 
mine, I used uasm.  I wonder if the extra memory occupied by uasm is too 
steep a penalty to pay for the ability to use it outside of __init code. 
  If not, we should move uasm out of __init and use it instead of this 
manual assembly.

David Daney