From: Andrew.Jackson@arm.com (Andrew Jackson) Date: Mon, 15 Dec 2014 08:37:52 +0000 Subject: [PATCH v2 2/6] ASoC: dwc: Ensure FIFOs are flushed to prevent channel swap In-Reply-To: <548AB75E.9030302@metafoo.de> References: <548AB75E.9030302@metafoo.de> Message-ID: <548E9DE0.7050502@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 12/12/14 09:37, Lars-Peter Clausen wrote: > On 12/12/2014 10:25 AM, Andrew Jackson wrote: >> From: Andrew Jackson >> >> If the FIFOs aren't flushed, the left/right channels may be swapped: >> this may occur if the FIFOs are not empty when the streams start. >> >> Signed-off-by: Andrew Jackson >> --- >> sound/soc/dwc/designware_i2s.c | 2 ++ >> 1 files changed, 2 insertions(+), 0 deletions(-) >> >> diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c >> index ef771ea..b9d6a25 100644 >> --- a/sound/soc/dwc/designware_i2s.c >> +++ b/sound/soc/dwc/designware_i2s.c >> @@ -228,12 +228,14 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, >> i2s_disable_channels(dev, substream->stream); >> >> if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { >> + i2s_write_reg(dev->i2s_base, TXFFR, 1); >> i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution); >> i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); >> irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); >> i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); >> i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); >> } else { >> + i2s_write_reg(dev->i2s_base, RXFFR, 1); >> i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution); >> i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); >> irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); >> > > This should probably go into the prepare callback. prepare is for example > also called when recovering from a underrun/overrun. Whereas hwparams is > only called during initial setup of the stream. That's a good idea: thank you. I'll rework the patch with this in mind. Andrew