From: Thomas Chou <thomas@wytron.com.tw>
Date: Wed, 21 Oct 2015 21:09:27 +0800
Subject: [U-Boot] [PATCH] net: convert altera_tse to driver model and
	phylib
In-Reply-To: <201510191431.55460.marex@denx.de>
References: <1445222181-30241-1-git-send-email-thomas@wytron.com.tw>
 <201510191431.55460.marex@denx.de>
Message-ID: <56278E87.9000208@wytron.com.tw>
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To: u-boot@lists.denx.de

Hi Marek,

On 10/19/2015 08:31 PM, Marek Vasut wrote:
>> +	/* decode regs, assume address-cells and size-cells are both one */
>> +	list = fdt_getprop(blob, node, "reg-names", &len);
>> +	if (!list)
>> +		return -ENOENT;
>> +	end = list + len;
>> +	cell = fdt_getprop(blob, node, "reg", &len);
>> +	if (!cell)
>> +		return -ENOENT;
>> +	idx = 0;
>> +	while (list < end) {
>> +		addr = fdt_translate_address((void *)blob,
>> +					     node, cell + idx);
>> +		size = fdt_addr_to_cpu(cell[idx + 1]);
>> +		base = ioremap(addr, size);
>> +		len = strlen(list);
>> +		if (strcmp(list, "control_port") == 0)
>> +			priv->mac_dev = base;
>
> fdtdec_get_addr() won't do here?

There are multiple "reg" tuples, and need to match "reg-names". That's 
beyond fdtdec_get_addr().

	tse_mac: ethernet at 0x4000 {
		compatible = "altr,tse-1.0";
		reg = <0x00004000 0x00000400>,
			<0x00004400 0x00000040>,
			<0x00004800 0x00000040>,
			<0x00002000 0x00002000>;
		reg-names = "control_port", "rx_csr", "tx_csr", "s1";

Thanks a lot for your reviews.

Best regards,
Thomas