From: Keir Fraser <keir@xensource.com>
Subject: Re: [PATCH] [HVM][SVM] Handle threshold register for
	guests
Date: Thu, 24 May 2007 11:45:45 +0100
Message-ID: <C27B2B69.F6F6%keir@xensource.com>
References: <200705211924.55185.Christoph.Egger@amd.com>
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To: Christoph Egger <Christoph.Egger@amd.com>, xen-devel@lists.xensource.com

On 21/5/07 18:24, "Christoph Egger" <Christoph.Egger@amd.com> wrote:

> The threshold register has been introduced in AMD RevF CPUs along with SVM
> (Actually this MCA/MCE msr register existed before, but had no meaning).
> Therefore no need for additional cpuid checks.
> 
> On read access it reports the HVM guest the register has been locked by the
> BIOS. This means, it is not available for OS use. Thus, write accesses are
> simply ignored.
> This behaviour actually matches real HW, so guests can deal with this.
> 
> Further, this way no multiplexing for multiple guests is necessary.
> Please apply.

I can't find any information about the revised semantics of M4_MISC in the
latest revision (3.12) of Volume 2 of the AMD64 Architecture Programmer's
Manual. Am I looking in the wrong place?

Since we don't advertise SVM capability to guests, wouldn't they assume old
semantics for this register anyway?

 Thanks,
 Keir