From: Keir Fraser <keir.fraser@eu.citrix.com>
Subject: Re: [PATCH] A workaround for AMD erratum 411
Date: Fri, 4 Jun 2010 13:31:10 +0100
Message-ID: <C82EB09E.16AE6%keir.fraser@eu.citrix.com>
References: <201006041333.43265.wei.wang2@amd.com>
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To: Wei Wang2 <wei.wang2@amd.com>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>
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I don't think we are susceptible to this bug, but it's probably a nice thing
to do anyway. I will apply some variant of it to xen-unstable at least.

 -- Keir

On 04/06/2010 12:33, "Wei Wang2" <wei.wang2@amd.com> wrote:

> Hi,
> This patch is a workaround of AMD erratum 411 for family 10h CPUs. This does
> not cause functional issues but may reduce the power saving effectiveness of
> message-triggered C1e mode. This would normally occur only if OS which has
> used the local APIC timer masks the interrupt without clearing Timer Initial
> Count Register.
> 
> Thanks,
> Wei
> 
> Signed-off-by: Wei Wang <wei.wang2@amd.com>