Date: Thu, 4 Jan 2024 18:22:19 +0000
From: Oliver Upton <oliver.upton@linux.dev>
To: Will Deacon <will@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	maz@kernel.org, keirf@google.com,
	Quentin Perret <qperret@google.com>
Subject: Re: [PATCH] KVM: arm64: Add missing memory barriers when switching
 to pKVM's hyp pgd
Message-ID: <ZZb3W1N80q6pAib7@linux.dev>
References: <20240104164220.7968-1-will@kernel.org>
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In-Reply-To: <20240104164220.7968-1-will@kernel.org>

On Thu, Jan 04, 2024 at 04:42:20PM +0000, Will Deacon wrote:
> In commit f320bc742bc23 ("KVM: arm64: Prepare the creation of s1
> mappings at EL2"), pKVM switches from a temporary host-provided
> page-table to its own page-table at EL2. Since there is only a single
> TTBR for the nVHE hypervisor, this involves disabling and re-enabling
> the MMU in __pkvm_init_switch_pgd().
> 
> Unfortunately, the memory barriers here are not quite correct.
> Specifically:
> 
>   - A DSB is required to complete the TLB invalidation executed while
>     the MMU is disabled.
> 
>   - An ISB is required to make the new TTBR value visible to the
>     page-table walker before the MMU is enabled in the SCTLR.
> 
> An earlier version of the patch actually got this correct:
> 
>   https://lore.kernel.org/lkml/20210304184717.GB21795@willie-the-truck/
> 
> but thanks to some badly worded review comments from yours truly, these
> were dropped for the version that was eventually merged.
> 
> Bring back the barriers and fix the potential issue (but note that this
> was found by code inspection).
> 
> Cc: Quentin Perret <qperret@google.com>
> Fixes: f320bc742bc23 ("KVM: arm64: Prepare the creation of s1 mappings at EL2")
> Signed-off-by: Will Deacon <will@kernel.org>

+1 to Marc's suggestion about folding the appropriate barriers into the
macro, but fine with this as is:

Reviewed-by: Oliver Upton <oliver.upton@linux.dev>

-- 
Thanks,
Oliver