Message-ID: <sashiko-outbox-206648@kernel.org>
From: sashiko-bot@kernel.org
Subject: Re: [PATCH v6 5/9] phy: rockchip-samsung-dcphy: Move block-level
 setup to runtime resume
Reply-To: sashiko-reviews@lists.linux.dev
To: "Jason Yang" <jason98166@gmail.com>
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com
In-Reply-To: <20261110-dcphy-rx-v1-v6-5-d681ba20b36a@gmail.com>
References: <20261110-dcphy-rx-v1-v6-0-d681ba20b36a@gmail.com>
 <20261110-dcphy-rx-v1-v6-5-d681ba20b36a@gmail.com>
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Date: Tue, 10 Nov 2026 08:40:46 +0000
Precedence: list

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] phy: rockchip-samsung-dcphy: stale SSC state in
  samsung_mipi_dcphy_pll_configure()
--

commit fa85aa14323095163211849e2a7f194d32765398
Author: Jason Yang <jason98166@gmail.com>

phy: rockchip-samsung-dcphy: Move block-level setup to runtime resume

This commit moves the APB reset pulse and BIAS block initialization from
the PHY power-on path to the runtime resume callback so that a second PHY
consumer does not reset an already running block.

> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/=
phy/rockchip/phy-rockchip-samsung-dcphy.c
> index 7a009d87a6656..d6acc3e2d4486 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

[ ... ]

> @@ -1373,10 +1372,6 @@ static int samsung_mipi_dcphy_power_on(struct phy =
*phy)
>  {
>  	struct samsung_mipi_dcphy *samsung =3D phy_get_drvdata(phy);
> =20
> -	reset_control_assert(samsung->apb_rst);
> -	udelay(1);
> -	reset_control_deassert(samsung->apb_rst);

[Severity: Medium]
Does removing the samsung->apb_rst pulse from samsung_mipi_dcphy_power_on()
leave SSCG_EN enabled in PLL_CON4 when the transmitter is reconfigured from
a rate above 2.5 Gbps to 2.5 Gbps or below while the device stays
runtime-resumed?

Without the APB reset on each power_on, PLL_CON3 and PLL_CON4 keep their
previous values, and samsung_mipi_dcphy_pll_configure() only touches them
when samsung->pll.ssc_en is true:

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c:samsung_mipi_dcphy_pll_co=
nfigure() {
	...
	if (samsung->pll.ssc_en) {
		regmap_write(samsung->regmap, PLL_CON3,
			     MRR(samsung->pll.mrr) | MFR(samsung->pll.mfr));
		regmap_update_bits(samsung->regmap, PLL_CON4, SSCG_EN, SSCG_EN);
	}
	...
}

In addition, samsung_mipi_dcphy_pll_calc_rate() sets samsung->pll.ssc_en =3D
true when fout > 2500000000LL, but never resets it to false for lower
rates, so switching to a lower-rate mode keeps spread-spectrum clocking
enabled with stale modulation parameters.

--=20
Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261110-dcphy-rx-v=
1-v6-0-d681ba20b36a@gmail.com?part=3D5