Message-ID: <sashiko-outbox-208800@kernel.org>
From: sashiko-bot@kernel.org
Subject: Re: [PATCH 4/6] dt-bindings: memory: tegra: Add Tegra114 EMC
 channel registers
Reply-To: sashiko-reviews@lists.linux.dev
To: "Patrick Fischer" <admin@tsv-stahl-riesa.de>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
In-Reply-To: <20261111-upstream-emc-t114-v1-4-54d9e1bceb6a@tsv-stahl-riesa.de>
References: <20261111-upstream-emc-t114-v1-0-54d9e1bceb6a@tsv-stahl-riesa.de>
 <20261111-upstream-emc-t114-v1-4-54d9e1bceb6a@tsv-stahl-riesa.de>
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Date: Wed, 11 Nov 2026 10:24:51 +0000
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Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: memory: tegra: piling Tegra114 conditionals in
  tegra124-emc.yaml
--

commit d5391965f848eab5127dd4add5fff242e933a0a0
Author: Patrick Fischer <admin@tsv-stahl-riesa.de>

dt-bindings: memory: tegra: Add Tegra114 EMC channel registers

This commit updates the Tegra124 EMC binding schema to allow two optional
channel register blocks in the reg property for Tegra114 while restricting
Tegra124 to a single reg entry.

> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,=
tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nv=
idia,tegra124-emc.yaml
> index 8e0c67d671f91..c9335483ba850 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra12=
4-emc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra12=
4-emc.yaml
> @@ -25,7 +25,13 @@ properties:
>            - const: nvidia,tegra124-emc
> =20
>    reg:
> -    maxItems: 1
> +    oneOf:
> +      - items:
> +          - description: EMC registers, writes go to all channels
> +      - items:
> +          - description: EMC registers, writes go to all channels
> +          - description: EMC channel 0 registers
> +          - description: EMC channel 1 registers
> =20
>    clocks:
>      items:
> @@ -218,6 +224,9 @@ allOf:
>              enum:
>                - nvidia,tegra124-emc
>      then:
> +      properties:
> +        reg:
> +          maxItems: 1
>        patternProperties:
>          "^emc-timings-[0-9]+$":
>            patternProperties:

[Severity: Low]
This isn't a bug, but would it be cleaner to split nvidia,tegra114-emc into
its own schema file rather than adding more per-compatible conditionals to
nvidia,tegra124-emc.yaml?

nvidia,tegra124-emc.yaml already relaxes nvidia,emc-configuration to a 97 to
143 entry range and uses an if-then block under allOf to require
nvidia,emc-bgbias-ctl0 and nvidia,emc-cfg-2 only on Tegra124. Widening the
top-level reg property and constraining it back in the conditional further
diverges the two variants, whereas Tegra20, Tegra30, and Tegra210 each use a
separate EMC binding schema.

--=20
Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261111-upstream-e=
mc-t114-v1-0-54d9e1bceb6a@tsv-stahl-riesa.de?part=3D4