Add RISC-V TEE support

PATCH New liushiwei 1 participant 1 message Jan 16, 2023

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liushiwei

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2023-01-16 13:08 UTC #0 lore raw

PATCH 1/1 Add RISC-V TEE support

Hi?Conor.
I have replied to the question of a draft proposal in another email, and Anup suggested that I edit it in https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc. I tried to push a document edit commit [https://github.com/riscv-non-isa/riscv-sbi-doc/pull/106]. Please check. Am I doing what you expect me to do?

Thanks,
Liushiwei
-----????-----
???: Conor Dooley [mailto:conor at kernel.org]
????: 2023?1?13? 19:47
???: opensbi at lists.infradead.org; liushiwei <[email protected]>; 'Anup Patel' <[email protected]> ??: hchauhan at ventanamicro.com; chenchaokai at eswincomputing.com
??: Re: ??: [PATCH 1/1] Add RISC-V TEE support

Quoted 1 line · liushiwei

Hi, Anup

It'd be nice if you'd respond inline so that following the conversation was easier. And responding from a mobile device would be too!

arch/riscv/include/asm/sbi.h enum sbi_ext_id { · line 32

Quoted 12 lines

I've combed through the linux code. What do you think of the following
change?
(quoted diff) +0 -0
b/arch/riscv/include/asm/sbi.h index d1c37479d..9696c8c77 100644
arch/riscv/include/asm/sbi.h +1 -0
@@ -29,6 +29,7 @@ enum sbi_ext_id {
       SBI_EXT_RFENCE = 0x52464E43,
       SBI_EXT_HSM = 0x48534D,
       SBI_EXT_SRST = 0x53525354,
+       SBI_EXT_TEE = 0x544545,

This range is reserved for official extensions.
Can you please respond to Anup's request, preserved below, for a draft proposal?

Quoted 2 lines

arch/riscv/include/asm/sbi.h +0 -0

 	I find that these values are just transformations of these letters?So I just use the ext id, not the func id?
 	While the sbi_ecall_tee_handler function uses other registers, such as t0.

Quoted 2 lines · Anup

Quoted 2 lines
We can't blindly use SBI extension ID and function ID space for TEE. Please share a draft proposal of how OP-TEE calls will be implemented as SBI calls.

Thanks,
Conor.