KVM/ARM Implementation

From: Marc Zyngier <[email protected]>

The KVM hypervisor mmu code requires access to the mem_type prot_pte field when setting up page tables pointing to a device. Unfortunately, the mem_type structure is opaque.

Add an accessor (get_mem_type_prot_pte()) to retrieve the prot_pte value.

Signed-off-by Marc Zyngier <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

---
 arch/arm/include/asm/mach/map.h |    1 +
 arch/arm/mm/mmu.c               |    6 ++++++
 2 files changed, 7 insertions(+)

arch/arm/include/asm/mach/map.h +1 -0

index a6efcdd..3787c9f 100644
@@ -37,6 +37,7 @@ extern void iotable_init(struct map_desc *, int);
 
 struct mem_type;
 extern const struct mem_type *get_mem_type(unsigned int type);
+extern pteval_t get_mem_type_prot_pte(unsigned int type);
 /*
  * external interface to remap single page with appropriate type
  */

arch/arm/mm/mmu.c +0 -0

index 4c2d045..76bf4f5 100644

Quoted 36 lines · Christoffer Dall

From: Marc Zyngier <[email protected]>

The KVM hypervisor mmu code requires access to the mem_type prot_pte field when setting up page tables pointing to a device. Unfortunately, the mem_type structure is opaque.

Add an accessor (get_mem_type_prot_pte()) to retrieve the prot_pte value.

Signed-off-by Marc Zyngier <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

---
 arch/arm/include/asm/mach/map.h |    1 +
 arch/arm/mm/mmu.c               |    6 ++++++
 2 files changed, 7 insertions(+)

arch/arm/include/asm/mach/map.h +1 -0

index a6efcdd..3787c9f 100644
@@ -37,6 +37,7 @@ extern void iotable_init(struct map_desc *, int);
 
 struct mem_type;
 extern const struct mem_type *get_mem_type(unsigned int type);
+extern pteval_t get_mem_type_prot_pte(unsigned int type);
 /*
  * external interface to remap single page with appropriate type
  */

arch/arm/mm/mmu.c +0 -0

index 4c2d045..76bf4f5 100644
@@ -301,6 +301,12 @@ const struct mem_type *get_mem_type(unsigned int type)
 }
 EXPORT_SYMBOL(get_mem_type);
 

arch/arm/mm/mmu.c const struct mem_type *get_mem_type(unsigned int type) · line 309

Quoted 6 lines

arch/arm/mm/mmu.c +6 -0

+pteval_t get_mem_type_prot_pte(unsigned int type)
+{
+     return get_mem_type(type)->prot_pte;
+}
+EXPORT_SYMBOL(get_mem_type_prot_pte);
+

get_mem_type can return NULL, so you should probably pass the error through rather than dereferencing it.

From: Marc Zyngier <[email protected]>

The KVM hypervisor mmu code requires access to the mem_type prot_pte field when setting up page tables pointing to a device. Unfortunately, the mem_type structure is opaque.

Add an accessor (get_mem_type_prot_pte()) to retrieve the prot_pte value.

Signed-off-by Marc Zyngier <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

Quoted 11 lines · Christoffer Dall

From: Marc Zyngier <[email protected]>

The KVM hypervisor mmu code requires access to the mem_type prot_pte field when setting up page tables pointing to a device. Unfortunately, the mem_type structure is opaque.

Add an accessor (get_mem_type_prot_pte()) to retrieve the prot_pte value.

Signed-off-by Marc Zyngier <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

Is there a reason why we need this to be exposed, along with all the page table manipulation in patch 7?

Is there a reason why we can't have new MT_ types for PAGE_HYP and the HYP MT_DEVICE type (which is the same as MT_DEVICE but with PTE_USER set) and have the standard ARM/generic kernel code build those mappings?

That would (it seems) also avoid the need to export the pXd_clear_bad() acessors too...

Quoted 16 lines · Russell King - ARM Linux

Quoted 11 lines · Christoffer Dall

From: Marc Zyngier <[email protected]>

The KVM hypervisor mmu code requires access to the mem_type prot_pte field when setting up page tables pointing to a device. Unfortunately, the mem_type structure is opaque.

Add an accessor (get_mem_type_prot_pte()) to retrieve the prot_pte value.

Signed-off-by Marc Zyngier <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

Is there a reason why we need this to be exposed, along with all the page table manipulation in patch 7?

Quoted 4 lines

Is there a reason why we can't have new MT_ types for PAGE_HYP and the HYP MT_DEVICE type (which is the same as MT_DEVICE but with PTE_USER set) and have the standard ARM/generic kernel code build those mappings?

For hyp mode we can do this, but we cannot do this for the cpu interfaces that need to be mapped into each VM as they have each their own pgd.

Quoted 23 lines · Christoffer Dall

Quoted 20 lines · Russell King - ARM Linux

Quoted 11 lines · Christoffer Dall

From: Marc Zyngier <[email protected]>

The KVM hypervisor mmu code requires access to the mem_type prot_pte field when setting up page tables pointing to a device. Unfortunately, the mem_type structure is opaque.

Add an accessor (get_mem_type_prot_pte()) to retrieve the prot_pte value.

Signed-off-by Marc Zyngier <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

Is there a reason why we need this to be exposed, along with all the page table manipulation in patch 7?

Is there a reason why we can't have new MT_ types for PAGE_HYP and the HYP MT_DEVICE type (which is the same as MT_DEVICE but with PTE_USER set) and have the standard ARM/generic kernel code build those mappings?

Quoted 3 lines

For hyp mode we can do this, but we cannot do this for the cpu interfaces that need to be mapped into each VM as they have each their own pgd.

Isn't that the same problem? The HYP mode has its own pgd too. I think this is the main issue with the generic code. If we can come up with an interface that allows the generic code to work on alternative pgds, we could pretty much do what Russell suggests here.

KVM uses the stage-2 page tables and the Hyp page table format, so let's define the fields we need to access in KVM.

We use pgprot_guest to indicate stage-2 entries.

Christoffer Dall <[email protected]>

---
 arch/arm/include/asm/pgtable-3level.h |   13 +++++++++++++
 arch/arm/include/asm/pgtable.h        |    5 +++++
 arch/arm/mm/mmu.c                     |    3 +++
 3 files changed, 21 insertions(+)

arch/arm/include/asm/pgtable-3level.h +0 -0

index b249035..7351eee 100644

arch/arm/include/asm/pgtable-3level.h +4 -0

 #ifndef __ASSEMBLY__
 
 #define pud_none(pud)		(!pud_val(pud))
 #define pud_bad(pud)		(!(pud_val(pud) & 2))
 #define pud_present(pud)	(pud_val(pud))
+#define pmd_table(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
+						 PMD_TYPE_TABLE)
+#define pmd_sect(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
+						 PMD_TYPE_SECT)
 
 #define pud_clear(pudp)			\
 	do {				\

arch/arm/include/asm/pgtable.h +1 -0

index 41dc31f..c422f62 100644
@@ -70,6 +70,7 @@ extern void __pgd_error(const char *file, int line, pgd_t);
 
 extern pgprot_t		pgprot_user;
 extern pgprot_t		pgprot_kernel;
+extern pgprot_t		pgprot_guest;
 
 #define _MOD_PROT(p, b)	__pgprot(pgprot_val(p) | (b))
 

arch/arm/include/asm/pgtable-3level.h line 110

Quoted 3 lines · Christoffer Dall

arch/arm/include/asm/pgtable-3level.h +3 -0

+#define L_PTE2_SHARED                L_PTE_SHARED
+#define L_PTE2_READ          (_AT(pteval_t, 1) << 6) /* HAP[0] */
+#define L_PTE2_WRITE         (_AT(pteval_t, 1) << 7) /* HAP[1] */

This is actually HAP[2:1], not HAP[1:0]. Also, can you follow what we do for stage 1 translation and name these RDONLY and WRONLY (do you even use that?).

arch/arm/include/asm/pgtable-3level.h line 112

Quoted 2 lines

arch/arm/include/asm/pgtable-3level.h +2 -0

+#define L_PTE2_NORM_WB               (_AT(pteval_t, 3) << 4) /* MemAttr[3:2] */
+#define L_PTE2_INNER_WB              (_AT(pteval_t, 3) << 2) /* MemAttr[1:0] */

Another minor nit: PTE2 looks awful. Maybe L_PTE_HYP_* instead?

Quoted 8 lines · Will Deacon

arch/arm/include/asm/pgtable-3level.h line 110

Quoted 3 lines · Christoffer Dall

arch/arm/include/asm/pgtable-3level.h +3 -0

+#define L_PTE2_SHARED                L_PTE_SHARED
+#define L_PTE2_READ          (_AT(pteval_t, 1) << 6) /* HAP[0] */
+#define L_PTE2_WRITE         (_AT(pteval_t, 1) << 7) /* HAP[1] */

This is actually HAP[2:1], not HAP[1:0]. Also, can you follow what we do for stage 1 translation and name these RDONLY and WRONLY (do you even use that?).

We can't use RDONLY as this would have value 0 as the HAP attributes (stage 2 overriding stage 1 translation attributes). Unless you add 4 definitions like NOACCESS, RDONLY, WRONLY and RDWR to cover all the bit combinations.

Quoted 4 lines

arch/arm/include/asm/pgtable-3level.h line 112

Quoted 2 lines

arch/arm/include/asm/pgtable-3level.h +2 -0

+#define L_PTE2_NORM_WB               (_AT(pteval_t, 3) << 4) /* MemAttr[3:2] */
+#define L_PTE2_INNER_WB              (_AT(pteval_t, 3) << 2) /* MemAttr[1:0] */

Another minor nit: PTE2 looks awful. Maybe L_PTE_HYP_* instead?

L_PTE_HYP may be confused with the Stage 1 Hyp translation which is different from the guest Stage 2.

But I have another minor nit - just write them in the ascending bit order as other definitions in this file.

Quoted 20 lines · Catalin Marinas

Quoted 8 lines · Will Deacon

arch/arm/include/asm/pgtable-3level.h line 110

Quoted 3 lines · Christoffer Dall

arch/arm/include/asm/pgtable-3level.h +3 -0

+#define L_PTE2_SHARED                L_PTE_SHARED
+#define L_PTE2_READ          (_AT(pteval_t, 1) << 6) /* HAP[0] */
+#define L_PTE2_WRITE         (_AT(pteval_t, 1) << 7) /* HAP[1] */

This is actually HAP[2:1], not HAP[1:0]. Also, can you follow what we do for stage 1 translation and name these RDONLY and WRONLY (do you even use that?).

We can't use RDONLY as this would have value 0 as the HAP attributes (stage 2 overriding stage 1 translation attributes). Unless you add 4 definitions like NOACCESS, RDONLY, WRONLY and RDWR to cover all the bit combinations.

Quoted 4 lines

arch/arm/include/asm/pgtable-3level.h line 112

Quoted 2 lines

arch/arm/include/asm/pgtable-3level.h +2 -0

+#define L_PTE2_NORM_WB               (_AT(pteval_t, 3) << 4) /* MemAttr[3:2] */
+#define L_PTE2_INNER_WB              (_AT(pteval_t, 3) << 2) /* MemAttr[1:0] */

Another minor nit: PTE2 looks awful. Maybe L_PTE_HYP_* instead?

Quoted 2 lines

L_PTE_HYP may be confused with the Stage 1 Hyp translation which is different from the guest Stage 2.

exactly, it's misleading, how about L_PTE_STAGE2, a little verbose, but clear...?

Quoted 22 lines · Christoffer Dall

Quoted 20 lines · Catalin Marinas

Quoted 8 lines · Will Deacon

arch/arm/include/asm/pgtable-3level.h line 110

Quoted 3 lines · Christoffer Dall

arch/arm/include/asm/pgtable-3level.h +3 -0

+#define L_PTE2_SHARED                L_PTE_SHARED
+#define L_PTE2_READ          (_AT(pteval_t, 1) << 6) /* HAP[0] */
+#define L_PTE2_WRITE         (_AT(pteval_t, 1) << 7) /* HAP[1] */

This is actually HAP[2:1], not HAP[1:0]. Also, can you follow what we do for stage 1 translation and name these RDONLY and WRONLY (do you even use that?).

We can't use RDONLY as this would have value 0 as the HAP attributes (stage 2 overriding stage 1 translation attributes). Unless you add 4 definitions like NOACCESS, RDONLY, WRONLY and RDWR to cover all the bit combinations.

Quoted 4 lines

arch/arm/include/asm/pgtable-3level.h line 112

Quoted 2 lines

arch/arm/include/asm/pgtable-3level.h +2 -0

+#define L_PTE2_NORM_WB               (_AT(pteval_t, 3) << 4) /* MemAttr[3:2] */
+#define L_PTE2_INNER_WB              (_AT(pteval_t, 3) << 2) /* MemAttr[1:0] */

Another minor nit: PTE2 looks awful. Maybe L_PTE_HYP_* instead?

Quoted 5 lines

Quoted 2 lines

L_PTE_HYP may be confused with the Stage 1 Hyp translation which is different from the guest Stage 2.

exactly, it's misleading, how about L_PTE_STAGE2, a little verbose, but clear...?

I don't mind any (apart from L_PTE_HYP_ would be confusing) for stage 2. You could just use S2 to make it shorter.

Quoted 17 lines · Christoffer Dall

KVM uses the stage-2 page tables and the Hyp page table format, so let's define the fields we need to access in KVM.

We use pgprot_guest to indicate stage-2 entries.

Christoffer Dall <[email protected]>

---
 arch/arm/include/asm/pgtable-3level.h |   13 +++++++++++++
 arch/arm/include/asm/pgtable.h        |    5 +++++
 arch/arm/mm/mmu.c                     |    3 +++
 3 files changed, 21 insertions(+)

arch/arm/include/asm/pgtable-3level.h +0 -0

index b249035..7351eee 100644

arch/arm/include/asm/pgtable-3level.h line 107

Quoted 6 lines

arch/arm/include/asm/pgtable-3level.h +3 -0

@@ -102,11 +102,24 @@
  */
 #define L_PGD_SWAPPER                (_AT(pgdval_t, 1) << 55)        /* swapper_pg_dir entry */
 
+/*
+ * 2-nd stage PTE definitions for LPAE.
+ */

Minor nit: 2nd

arch/arm/include/asm/pgtable-3level.h line 110

Quoted 3 lines

arch/arm/include/asm/pgtable-3level.h +3 -0

+#define L_PTE2_SHARED                L_PTE_SHARED
+#define L_PTE2_READ          (_AT(pteval_t, 1) << 6) /* HAP[0] */
+#define L_PTE2_WRITE         (_AT(pteval_t, 1) << 7) /* HAP[1] */

This is actually HAP[2:1], not HAP[1:0]. Also, can you follow what we do for stage 1 translation and name these RDONLY and WRONLY (do you even use that?).

arch/arm/include/asm/pgtable-3level.h line 112

Quoted 2 lines

arch/arm/include/asm/pgtable-3level.h +2 -0

+#define L_PTE2_NORM_WB               (_AT(pteval_t, 3) << 4) /* MemAttr[3:2] */
+#define L_PTE2_INNER_WB              (_AT(pteval_t, 3) << 2) /* MemAttr[1:0] */

Another minor nit: PTE2 looks awful. Maybe L_PTE_HYP_* instead?

Quoted 25 lines

arch/arm/include/asm/pgtable-3level.h +4 -0

 #ifndef __ASSEMBLY__
 
 #define pud_none(pud)                (!pud_val(pud))
 #define pud_bad(pud)         (!(pud_val(pud) & 2))
 #define pud_present(pud)     (pud_val(pud))
+#define pmd_table(pmd)               ((pmd_val(pmd) & PMD_TYPE_MASK) == \
+                                              PMD_TYPE_TABLE)
+#define pmd_sect(pmd)                ((pmd_val(pmd) & PMD_TYPE_MASK) == \
+                                              PMD_TYPE_SECT)
 
 #define pud_clear(pudp)                      \
      do {                            \

arch/arm/include/asm/pgtable.h +1 -0

index 41dc31f..c422f62 100644
@@ -70,6 +70,7 @@ extern void __pgd_error(const char *file, int line, pgd_t);
 
 extern pgprot_t              pgprot_user;
 extern pgprot_t              pgprot_kernel;
+extern pgprot_t              pgprot_guest;
 
 #define _MOD_PROT(p, b)      __pgprot(pgprot_val(p) | (b))
 

arch/arm/include/asm/pgtable.h extern pgprot_t pgprot_kernel; · line 86

Quoted 4 lines

arch/arm/include/asm/pgtable.h +1 -0

@@ -82,6 +83,10 @@ extern pgprot_t            pgprot_kernel;
 #define PAGE_READONLY_EXEC   _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
 #define PAGE_KERNEL          _MOD_PROT(pgprot_kernel, L_PTE_XN)
 #define PAGE_KERNEL_EXEC     pgprot_kernel
+#define PAGE_HYP             _MOD_PROT(pgprot_kernel, L_PTE_USER)

Just define L_PTE_HYP to L_PTE_USER, otherwise that's confusing.

arch/arm/include/asm/pgtable.h extern pgprot_t pgprot_kernel; · line 89

Quoted 3 lines

arch/arm/include/asm/pgtable.h +3 -0

+#define PAGE_KVM_GUEST               _MOD_PROT(pgprot_guest, L_PTE2_READ | \
+                                       L_PTE2_NORM_WB | L_PTE2_INNER_WB | \
+                                       L_PTE2_SHARED)

It would be cleaner to separate the cacheability attributes out from here and into the cache_policies array. Then you just need L_PTE_HYP_RDONLY here.

Quoted 9 lines · Will Deacon

Review

Quoted 3 lines · Christoffer Dall

(quoted diff) +3 -0

+#define L_PTE2_SHARED                L_PTE_SHARED
+#define L_PTE2_READ          (_AT(pteval_t, 1) << 6) /* HAP[0] */
+#define L_PTE2_WRITE         (_AT(pteval_t, 1) << 7) /* HAP[1] */

This is actually HAP[2:1], not HAP[1:0]. Also, can you follow what we do for stage 1 translation and name these RDONLY and WRONLY (do you even use that?).

The ARM arm is actually ambiguous, B3-1335 defines it as HAP[2:1], but B3-1355 defines it as HAP[1:0] and I chose the latter as it is more clear to most people not knowing that for historical reasons {H}AP[0] is not defined. If there's a consensus for the other choice here, then I'm good with that.

Also, these bits have a different meaning for stage-2, HAP[2] (ok, in this case it's less misleading with bit index 2), HAP[2] actually means you can write this, two clear bits means access denied, not read/write, so it made more sense to me to do:

prot = READ | WRITE;

than

prt = RDONLY | WRONLY; // (not mutually exclusive). See my point?

Quoted 4 lines

It would be cleaner to separate the cacheability attributes out from here and into the cache_policies array. Then you just need L_PTE_HYP_RDONLY here.

ok, below is an attempt to rework all this, comments please:

arch/arm/include/asm/pgtable-3level.h +1 -2

index 7351eee..6df235c 100644
@@ -103,13 +103,19 @@
 #define L_PGD_SWAPPER		(_AT(pgdval_t, 1) << 55)	/* swapper_pg_dir entry */
 
 /*
- * 2-nd stage PTE definitions for LPAE.
+ * 2nd stage PTE definitions for LPAE.
  */
-#define L_PTE2_SHARED		L_PTE_SHARED

arch/arm/include/asm/pgtable-3level.h +4 -0

+/*
+ * Hyp-mode PL2 PTE definitions for LPAE.
+ */
+#define L_PTE_HYP		L_PTE_USER
 
 #ifndef __ASSEMBLY__
 

arch/arm/include/asm/pgtable.h +2 -4

index c422f62..6ab276b 100644
@@ -83,10 +83,8 @@ extern pgprot_t		pgprot_guest;
 #define PAGE_READONLY_EXEC	_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
 #define PAGE_KERNEL		_MOD_PROT(pgprot_kernel, L_PTE_XN)
 #define PAGE_KERNEL_EXEC	pgprot_kernel
-#define PAGE_HYP		_MOD_PROT(pgprot_kernel, L_PTE_USER)
-#define PAGE_KVM_GUEST		_MOD_PROT(pgprot_guest, L_PTE2_READ | \
-					  L_PTE2_NORM_WB | L_PTE2_INNER_WB | \
-					  L_PTE2_SHARED)
+#define PAGE_HYP		_MOD_PROT(pgprot_kernel, L_PTE_HYP)
+#define PAGE_KVM_GUEST		_MOD_PROT(pgprot_guest, L_PTE_S2_READ)
 
 #define __PAGE_NONE		__pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN)
 #define __PAGE_SHARED		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)

arch/arm/kvm/mmu.c +1 -1

index 82d0edf..3ff427b 100644
@@ -476,7 +476,7 @@ int kvm_phys_addr_ioremap(struct kvm *kvm,
 phys_addr_t guest_ipa,
 
 	end = (guest_ipa + size + PAGE_SIZE - 1) & PAGE_MASK;
 	prot = __pgprot(get_mem_type_prot_pte(MT_DEVICE) | L_PTE_USER |
-			L_PTE2_READ | L_PTE2_WRITE);
+			L_PTE_S2_READ | L_PTE_S2_WRITE);
 	pfn = __phys_to_pfn(pa);
 

arch/arm/kvm/mmu.c +1 -1

 	for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {

@@ -567,7 +567,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu,
 phys_addr_t fault_ipa,
 		goto out;
 	new_pte = pfn_pte(pfn, PAGE_KVM_GUEST);
 	if (writable)
-		pte_val(new_pte) |= L_PTE2_WRITE;
+		pte_val(new_pte) |= L_PTE_S2_WRITE;
 	coherent_icache_guest_page(vcpu->kvm, gfn);
 

arch/arm/kvm/mmu.c +0 -0

 	spin_lock(&vcpu->kvm->arch.pgd_lock);

arch/arm/mm/mmu.c +4 -0

index f2b6287..a06f3496 100644
@@ -67,6 +67,7 @@ struct cachepolicy {
 	unsigned int	cr_mask;
 	pmdval_t	pmd;
 	pteval_t	pte;
+	pteval_t	pte_s2;
 };
 
 static struct cachepolicy cache_policies[] __initdata = {

@@ -75,26 +76,31 @@ static struct cachepolicy cache_policies[] __initdata = {
 		.cr_mask	= CR_W|CR_C,
 		.pmd		= PMD_SECT_UNCACHED,
 		.pte		= L_PTE_MT_UNCACHED,
+		.pte_s2		= L_PTE_S2_MT_UNCACHED,
 	}, {
 		.policy		= "buffered",
 		.cr_mask	= CR_C,
 		.pmd		= PMD_SECT_BUFFERED,
 		.pte		= L_PTE_MT_BUFFERABLE,
+		.pte_s2		= L_PTE_S2_MT_UNCACHED,
 	}, {
 		.policy		= "writethrough",
 		.cr_mask	= 0,
 		.pmd		= PMD_SECT_WT,
 		.pte		= L_PTE_MT_WRITETHROUGH,
+		.pte_s2		= L_PTE_S2_MT_WRTHROUGH,
 	}, {
 		.policy		= "writeback",
 		.cr_mask	= 0,
 		.pmd		= PMD_SECT_WB,

arch/arm/mm/mmu.c +2 -1

@@ -318,7 +324,7 @@ static void __init build_mem_type_table(void)
 {
 	struct cachepolicy *cp;
 	unsigned int cr = get_cr();
-	pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
+	pteval_t user_pgprot, kern_pgprot, vecs_pgprot, guest_pgprot;
 	int cpu_arch = cpu_architecture();
 	int i;
 

@@ -430,6 +436,7 @@ static void __init build_mem_type_table(void)
 	 */
 	cp = &cache_policies[cachepolicy];
 	vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
+	guest_pgprot = cp->pte_s2;
 
 	/*
 	 * Enable CPU-specific coherency if supported.

Quoted 11 lines · Christoffer Dall

Quoted 9 lines · Will Deacon

Review

Quoted 3 lines · Christoffer Dall

(quoted diff) +3 -0

+#define L_PTE2_SHARED                L_PTE_SHARED
+#define L_PTE2_READ          (_AT(pteval_t, 1) << 6) /* HAP[0] */
+#define L_PTE2_WRITE         (_AT(pteval_t, 1) << 7) /* HAP[1] */

This is actually HAP[2:1], not HAP[1:0]. Also, can you follow what we do for stage 1 translation and name these RDONLY and WRONLY (do you even use that?).

Quoted 5 lines

The ARM arm is actually ambiguous, B3-1335 defines it as HAP[2:1], but B3-1355 defines it as HAP[1:0] and I chose the latter as it is more clear to most people not knowing that for historical reasons {H}AP[0] is not defined. If there's a consensus for the other choice here, then I'm good with that.

Just checked the latest ARM ARM (rev C) and "HAP[1:0]" doesn't appear anywhere in the document, so it looks like it's been fixed.

Quoted 10 lines

Also, these bits have a different meaning for stage-2, HAP[2] (ok, in this case it's less misleading with bit index 2), HAP[2] actually means you can write this, two clear bits means access denied, not read/write, so it made more sense to me to do:

prot = READ | WRITE;

than

prt = RDONLY | WRONLY; // (not mutually exclusive). See my point?

If you define the bits like:

L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6)
L_PTE_S2_WRONLY (_AT(pteval_t, 2) << 6)

then I think it's fairly clear and it also matches the ARM ARM descriptions for the HAP permissions. You could also add L_PTE_S2_RDWR if you don't like orring the things elsewhere.

Quoted 26 lines

Quoted 4 lines

It would be cleaner to separate the cacheability attributes out from here and into the cache_policies array. Then you just need L_PTE_HYP_RDONLY here.

ok, below is an attempt to rework all this, comments please:

arch/arm/include/asm/pgtable-3level.h +2 -6

index 7351eee..6df235c 100644
@@ -103,13 +103,19 @@
 #define L_PGD_SWAPPER                (_AT(pgdval_t, 1) << 55)        /* swapper_pg_dir entry */
 
 /*
- * 2-nd stage PTE definitions for LPAE.
+ * 2nd stage PTE definitions for LPAE.
  */
-#define L_PTE2_SHARED                L_PTE_SHARED
-#define L_PTE2_READ          (_AT(pteval_t, 1) << 6) /* HAP[0] */
-#define L_PTE2_WRITE         (_AT(pteval_t, 1) << 7) /* HAP[1] */
-#define L_PTE2_NORM_WB               (_AT(pteval_t, 3) << 4) /* MemAttr[3:2] */
-#define L_PTE2_INNER_WB              (_AT(pteval_t, 3) << 2) /* MemAttr[1:0] */
+#define L_PTE_S2_SHARED              L_PTE_SHARED

arch/arm/include/asm/pgtable-3level.h line 113

Quoted 5 lines

arch/arm/include/asm/pgtable-3level.h +5 -0

+#define L_PTE_S2_READ                (_AT(pteval_t, 1) << 6)   /* HAP[1] */
+#define L_PTE_S2_WRITE               (_AT(pteval_t, 1) << 7)   /* HAP[2] */
+#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_MT_WRTHROUGH        (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_MT_WRBACK   (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */

Again, just use the same names as we do for stage 1. It really makes the code easier to read (L_PTE_S2_MT_WRITETHROUGH etc.).

Quoted 88 lines

arch/arm/include/asm/pgtable-3level.h +4 -0

+/*
+ * Hyp-mode PL2 PTE definitions for LPAE.
+ */
+#define L_PTE_HYP            L_PTE_USER
 
 #ifndef __ASSEMBLY__
 

arch/arm/include/asm/pgtable.h +2 -4

index c422f62..6ab276b 100644
@@ -83,10 +83,8 @@ extern pgprot_t            pgprot_guest;
 #define PAGE_READONLY_EXEC   _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
 #define PAGE_KERNEL          _MOD_PROT(pgprot_kernel, L_PTE_XN)
 #define PAGE_KERNEL_EXEC     pgprot_kernel
-#define PAGE_HYP             _MOD_PROT(pgprot_kernel, L_PTE_USER)
-#define PAGE_KVM_GUEST               _MOD_PROT(pgprot_guest, L_PTE2_READ | \
-                                       L_PTE2_NORM_WB | L_PTE2_INNER_WB | \
-                                       L_PTE2_SHARED)
+#define PAGE_HYP             _MOD_PROT(pgprot_kernel, L_PTE_HYP)
+#define PAGE_KVM_GUEST               _MOD_PROT(pgprot_guest, L_PTE_S2_READ)
 
 #define __PAGE_NONE          __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN)
 #define __PAGE_SHARED                __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)

arch/arm/kvm/mmu.c +1 -1

index 82d0edf..3ff427b 100644
@@ -476,7 +476,7 @@ int kvm_phys_addr_ioremap(struct kvm *kvm,
 phys_addr_t guest_ipa,
 
      end = (guest_ipa + size + PAGE_SIZE - 1) & PAGE_MASK;
      prot = __pgprot(get_mem_type_prot_pte(MT_DEVICE) | L_PTE_USER |
-                     L_PTE2_READ | L_PTE2_WRITE);
+                     L_PTE_S2_READ | L_PTE_S2_WRITE);
      pfn = __phys_to_pfn(pa);
 

      for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {

arch/arm/kvm/mmu.c +1 -1

@@ -567,7 +567,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu,
 phys_addr_t fault_ipa,
              goto out;
      new_pte = pfn_pte(pfn, PAGE_KVM_GUEST);
      if (writable)
-             pte_val(new_pte) |= L_PTE2_WRITE;
+             pte_val(new_pte) |= L_PTE_S2_WRITE;
      coherent_icache_guest_page(vcpu->kvm, gfn);
 

      spin_lock(&vcpu->kvm->arch.pgd_lock);

arch/arm/mm/mmu.c +5 -0

index f2b6287..a06f3496 100644
@@ -67,6 +67,7 @@ struct cachepolicy {
      unsigned int    cr_mask;
      pmdval_t        pmd;
      pteval_t        pte;
+     pteval_t        pte_s2;
 };
 
 static struct cachepolicy cache_policies[] __initdata = {

@@ -75,26 +76,31 @@ static struct cachepolicy cache_policies[] __initdata = {
              .cr_mask        = CR_W|CR_C,
              .pmd            = PMD_SECT_UNCACHED,
              .pte            = L_PTE_MT_UNCACHED,
+             .pte_s2         = L_PTE_S2_MT_UNCACHED,
      }, {
              .policy         = "buffered",
              .cr_mask        = CR_C,
              .pmd            = PMD_SECT_BUFFERED,
              .pte            = L_PTE_MT_BUFFERABLE,
+             .pte_s2         = L_PTE_S2_MT_UNCACHED,
      }, {
              .policy         = "writethrough",
              .cr_mask        = 0,
              .pmd            = PMD_SECT_WT,
              .pte            = L_PTE_MT_WRITETHROUGH,
+             .pte_s2         = L_PTE_S2_MT_WRTHROUGH,
      }, {
              .policy         = "writeback",
              .cr_mask        = 0,
              .pmd            = PMD_SECT_WB,
              .pte            = L_PTE_MT_WRITEBACK,
+             .pte_s2         = L_PTE_S2_MT_WRBACK,
      }, {
              .policy         = "writealloc",
              .cr_mask        = 0,
              .pmd            = PMD_SECT_WBWA,
              .pte            = L_PTE_MT_WRITEALLOC,

arch/arm/mm/mmu.c static struct cachepolicy cache_policies[] __initdata = { · line 105

Quoted 3 lines

arch/arm/mm/mmu.c +1 -0

+             .pte_s2         = L_PTE_S2_MT_WRBACK,
      }
 };

Does this still compile for classic MMU? It might be nicer to use arrays for the pte types instead of the extra field too -- I assume you'll want something similar for the pmd if/when you map stage2 translations using sections?

Quoted 15 lines

arch/arm/mm/mmu.c +2 -1

@@ -318,7 +324,7 @@ static void __init build_mem_type_table(void)
 {
      struct cachepolicy *cp;
      unsigned int cr = get_cr();
-     pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
+     pteval_t user_pgprot, kern_pgprot, vecs_pgprot, guest_pgprot;
      int cpu_arch = cpu_architecture();
      int i;
 

@@ -430,6 +436,7 @@ static void __init build_mem_type_table(void)
       */
      cp = &cache_policies[cachepolicy];
      vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
+     guest_pgprot = cp->pte_s2;
 

arch/arm/mm/mmu.c static void __init build_mem_type_table(void) · line 474

Quoted 7 lines

arch/arm/mm/mmu.c +1 -0

      /*
       * Enable CPU-specific coherency if supported.

@@ -464,6 +471,7 @@ static void __init build_mem_type_table(void)
                      user_pgprot |= L_PTE_SHARED;
                      kern_pgprot |= L_PTE_SHARED;
                      vecs_pgprot |= L_PTE_SHARED;
+                     guest_pgprot |= L_PTE_SHARED;

If we're using L_PTE_SHARED directly, do we even need L_PTE_S2_SHARED to be defined?

arch/arm/mm/mmu.c static void __init build_mem_type_table(void) · line 529

Quoted 9 lines

arch/arm/mm/mmu.c +1 -1

                      mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
                      mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
                      mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;

@@ -518,7 +526,7 @@ static void __init build_mem_type_table(void)
      pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
      pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
                               L_PTE_DIRTY | kern_pgprot);
-     pgprot_guest  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG);
+     pgprot_guest  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | guest_pgprot);

We don't have L_PTE_S2_PRESENT, for example.

I'll try and get on to the meat of the code at some point, but there's an awful lot of it and it's hard to see how it fits together.

From: Marc Zyngier <[email protected]>

Add a HYP pgd to the core code (so it can benefit all Linux hypervisors).

Populate this pgd with an identity mapping of the code contained in the .hyp.idmap.text section

Offer a method to drop the this identity mapping through hyp_idmap_teardown and re-create it through hyp_idmap_setup.

Make all the above depend on CONFIG_ARM_VIRT_EXT

Cc Will Deacon <[email protected]>

Signed-off-by Marc Zyngier <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

---
 arch/arm/include/asm/idmap.h                |    7 ++
 arch/arm/include/asm/pgtable-3level-hwdef.h |    1 
 arch/arm/kernel/vmlinux.lds.S               |    6 ++
 arch/arm/mm/idmap.c                         |   88 +++++++++++++++++++++++----
 4 files changed, 89 insertions(+), 13 deletions(-)

arch/arm/include/asm/idmap.h +7 -0

index bf863ed..a1ab8d6 100644
@@ -11,4 +11,11 @@ extern pgd_t *idmap_pgd;
 
 void setup_mm_for_reboot(void);
 
+#ifdef CONFIG_ARM_VIRT_EXT
+extern pgd_t *hyp_pgd;
+
+void hyp_idmap_teardown(void);
+void hyp_idmap_setup(void);
+#endif
+
 #endif	/* __ASM_IDMAP_H */

arch/arm/include/asm/pgtable-3level-hwdef.h +0 -0

index d795282..a2d404e 100644

arch/arm/mm/idmap.c +14 -8

index ab88ed4..7a944af 100644
@@ -1,4 +1,6 @@
+#include <linux/module.h>
 #include <linux/kernel.h>
+#include <linux/slab.h>
 
 #include <asm/cputype.h>
 #include <asm/idmap.h>

@@ -59,11 +61,20 @@ static void idmap_add_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
 	} while (pud++, addr = next, addr != end);
 }
 
-static void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end)
+static void identity_mapping_add(pgd_t *pgd, const char *text_start,
+				 const char *text_end, unsigned long prot)
 {
-	unsigned long prot, next;
+	unsigned long addr, end;
+	unsigned long next;
+
+	addr = virt_to_phys(text_start);
+	end = virt_to_phys(text_end);
+
+	pr_info("Setting up static %sidentity map for 0x%llx - 0x%llx\n",
+		prot ? "HYP " : "",
+		(long long)addr, (long long)end);
+	prot |= PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF;
 
-	prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF;
 	if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
 		prot |= PMD_BIT4;
 

@@ -78,24 +89,77 @@ extern char  __idmap_text_start[], __idmap_text_end[];
 
 static int __init init_static_idmap(void)
 {
-	phys_addr_t idmap_start, idmap_end;
-
 	idmap_pgd = pgd_alloc(&init_mm);
 	if (!idmap_pgd)
 		return -ENOMEM;
 
-	/* Add an identity mapping for the physical address of the section. */
-	idmap_start = virt_to_phys((void *)__idmap_text_start);
-	idmap_end = virt_to_phys((void *)__idmap_text_end);

arch/arm/mm/idmap.c +49 -0

+#ifdef CONFIG_ARM_VIRT_EXT
+pgd_t *hyp_pgd;
+EXPORT_SYMBOL_GPL(hyp_pgd);
+
+static void hyp_idmap_del_pmd(pgd_t *pgd, unsigned long addr)
+{
+	pud_t *pud;
+	pmd_t *pmd;
+
+	pud = pud_offset(pgd, addr);
+	pmd = pmd_offset(pud, addr);
+	pud_clear(pud);
+	clean_pmd_entry(pmd);
+	pmd_free(NULL, (pmd_t *)((unsigned long)pmd & PAGE_MASK));
+}
+
+extern char  __hyp_idmap_text_start[], __hyp_idmap_text_end[];
+
+/*
+ * This version actually frees the underlying pmds for all pgds in range and
+ * clear the pgds themselves afterwards.
+ */
+void hyp_idmap_teardown(void)
+{
+	unsigned long addr, end;
+	unsigned long next;
+	pgd_t *pgd = hyp_pgd;
+
+	addr = virt_to_phys(__hyp_idmap_text_start);
+	end = virt_to_phys(__hyp_idmap_text_end);
+
+	pgd += pgd_index(addr);
+	do {
+		next = pgd_addr_end(addr, end);
+		if (!pgd_none_or_clear_bad(pgd))
+			hyp_idmap_del_pmd(pgd, addr);
+	} while (pgd++, addr = next, addr < end);
+}
+EXPORT_SYMBOL_GPL(hyp_idmap_teardown);
+
+void hyp_idmap_setup(void)
+{
+	identity_mapping_add(hyp_pgd, __hyp_idmap_text_start,
+			     __hyp_idmap_text_end, PMD_SECT_AP1);
+}
+EXPORT_SYMBOL_GPL(hyp_idmap_setup);
+
+static int __init hyp_init_static_idmap(void)
+{

Quoted 9 lines

(quoted diff) +9 -0

+
+static int __init hyp_init_static_idmap(void)
+{
+     hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
+     if (!hyp_pgd)
+             return -ENOMEM;
+
+     hyp_idmap_setup();
+

Review

Quoted 4 lines

(quoted diff) +4 -0

+     return 0;
+}
+early_initcall(hyp_init_static_idmap);
+#endif

I'd rather the alloc/free functions for the hyp pgd were somewhere else, like they are for standard pgds. Then we can just call them here without having to encode knowledge of PGD size etc in the mapping code.

From: Marc Zyngier <[email protected]>

Signed-off-by Marc Zyngier <[email protected]>

---
 arch/arm/mm/idmap.c |    4 ++++
 1 file changed, 4 insertions(+)

Quoted 6 lines · Christoffer Dall

From: Marc Zyngier <[email protected]>

Signed-off-by Marc Zyngier <[email protected]>

---
 arch/arm/mm/idmap.c |    4 ++++
 1 file changed, 4 insertions(+)

Just fold this into the previous patch.

From: Rusty Russell <[email protected]>

We want some of these for use in KVM, so pull them out of arch/arm/kernel/perf_event_v7.c into their own asm/perf_bits.h.

Signed-off-by Rusty Russell <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

---
 arch/arm/include/asm/perf_bits.h |   56 ++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/perf_event_v7.c  |   51 +----------------------------------
 2 files changed, 57 insertions(+), 50 deletions(-)
 create mode 100644 arch/arm/include/asm/perf_bits.h

Quoted 5 lines · Christoffer Dall

From: Rusty Russell <[email protected]>

We want some of these for use in KVM, so pull them out of arch/arm/kernel/perf_event_v7.c into their own asm/perf_bits.h.

Quoted 7 lines

Signed-off-by Rusty Russell <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

---
 arch/arm/include/asm/perf_bits.h |   56 ++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/perf_event_v7.c  |   51 +----------------------------------
 2 files changed, 57 insertions(+), 50 deletions(-)
 create mode 100644 arch/arm/include/asm/perf_bits.h

I don't like this I'm afraid. These bit definitions, although useful for kvm, are only applicable to ARMv7 PMUs. Perf does a reasonable job of separating the low-level CPU-specific code and adding the v7 definitions into their own global header feels like a step backwards. I also want to move a load of this into drivers/ at some point and this won't help with that effort.

Is KVM just using this for world switch? If so, why does it care about the bit definitions (and what do you do for things like debug regs)? Is there anything I could add to perf that you could call instead?

Quoted 5 lines · Christoffer Dall

From: Rusty Russell <[email protected]>

We want some of these for use in KVM, so pull them out of arch/arm/kernel/perf_event_v7.c into their own asm/perf_bits.h.

Quoted 7 lines

Signed-off-by Rusty Russell <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

---
 arch/arm/include/asm/perf_bits.h |   56 ++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/perf_event_v7.c  |   51 +----------------------------------
 2 files changed, 57 insertions(+), 50 deletions(-)
 create mode 100644 arch/arm/include/asm/perf_bits.h

I don't like this I'm afraid. These bit definitions, although useful for kvm, are only applicable to ARMv7 PMUs. Perf does a reasonable job of separating the low-level CPU-specific code and adding the v7 definitions into their own global header feels like a step backwards. I also want to move a load of this into drivers/ at some point and this won't help with that effort.

Is KVM just using this for world switch? If so, why does it care about the bit definitions (and what do you do for things like debug regs)? Is there anything I could add to perf that you could call instead?

Quoted 21 lines · Will Deacon

Quoted 5 lines · Christoffer Dall

From: Rusty Russell <[email protected]>

We want some of these for use in KVM, so pull them out of arch/arm/kernel/perf_event_v7.c into their own asm/perf_bits.h.

Quoted 7 lines

Signed-off-by Rusty Russell <[email protected]>

Signed-off-by Christoffer Dall <[email protected]>

---
 arch/arm/include/asm/perf_bits.h |   56 ++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/perf_event_v7.c  |   51 +----------------------------------
 2 files changed, 57 insertions(+), 50 deletions(-)
 create mode 100644 arch/arm/include/asm/perf_bits.h

I don't like this I'm afraid. These bit definitions, although useful for kvm, are only applicable to ARMv7 PMUs. Perf does a reasonable job of separating the low-level CPU-specific code and adding the v7 definitions into their own global header feels like a step backwards. I also want to move a load of this into drivers/ at some point and this won't help with that effort.

Quoted 3 lines

Is KVM just using this for world switch? If so, why does it care about the bit definitions (and what do you do for things like debug regs)? Is there anything I could add to perf that you could call instead?

No, we need these definitions if we ever want to actually implement PMU for the guest.[1]

But we don't do this yet, so you can defer this patch until then if you want.

[1] Which we should do, since you NAKed the patch which would allow the guest to detect that we don't have a PMU, insisting that "all A15s have a PMU", despite the fact that we don't. I assume this means you're busy implementing it right now :)

Targets KVM support for Cortex A-15 processors.

Contains all the framework components, make files, header files, some tracing functionality, and basic user space API.

Only supported core is Cortex-A15 for now.

Most functionality is in arch/arm/kvm/* or arch/arm/include/asm/kvm_*.h.

?Nothing to see here. Move along, move along..."

arch/arm/include/asm/kvm.h new file +31 -0

new file mode 100644
index 0000000..a13b582
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ARM_KVM_H__
+#define __ARM_KVM_H__
+
+#include <asm/types.h>
+
+#define __KVM_HAVE_GUEST_DEBUG
+
+#define KVM_REG_SIZE(id)                                               \
+       (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
+
+struct kvm_regs {
+       __u32 usr_regs[15];     /* R0_usr - R14_usr */
+       __u32 svc_regs[3];      /* SP_svc, LR_svc, SPSR_svc */

arch/arm/include/asm/kvm_arm.h new file +13 -0

new file mode 100644
index 0000000..2f9d28e
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *

arch/arm/include/asm/kvm_asm.h new file +18 -0

new file mode 100644
index 0000000..44591f9
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+

arch/arm/include/asm/kvm_emulate.h new file +32 -0

new file mode 100644
index 0000000..9e29335
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ARM_KVM_EMULATE_H__
+#define __ARM_KVM_EMULATE_H__
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+
+u32 *vcpu_reg_mode(struct kvm_vcpu *vcpu, u8 reg_num, enum vcpu_mode mode);
+
+static inline u8 __vcpu_mode(u32 cpsr)
+{
+       u8 modes_table[32] = {
+               0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
+               0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
+               MODE_USR,       /* 0x0 */

arch/arm/include/asm/kvm_host.h new file +14 -0

new file mode 100644
index 0000000..24959f4
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License

arch/arm/include/asm/kvm_host.h new file +51 -0

+
+/* We don't currently support large pages. */
+#define KVM_HPAGE_GFN_SHIFT(x) 0
+#define KVM_NR_PAGE_SIZES      1
+#define KVM_PAGES_PER_HPAGE(x) (1UL<<31)
+
+struct kvm_vcpu;
+u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
+int kvm_target_cpu(void);
+int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
+void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
+
+struct kvm_arch {
+       /* The VMID generation used for the virt. memory system */
+       u64    vmid_gen;
+       u32    vmid;
+
+       /* 1-level 2nd stage table and lock */
+       spinlock_t pgd_lock;
+       pgd_t *pgd;
+
+       /* VTTBR value associated with above pgd and vmid */
+       u64    vttbr;
+};
+
+#define EXCEPTION_NONE      0
+#define EXCEPTION_RESET     0x80
+#define EXCEPTION_UNDEFINED 0x40
+#define EXCEPTION_SOFTWARE  0x20
+#define EXCEPTION_PREFETCH  0x10
+#define EXCEPTION_DATA      0x08
+#define EXCEPTION_IMPRECISE 0x04
+#define EXCEPTION_IRQ       0x02
+#define EXCEPTION_FIQ       0x01
+
+#define KVM_NR_MEM_OBJS     40
+
+/*
+ * We don't want allocation failures within the mmu code, so we preallocate
+ * enough memory for a single page fault in a cache.
+ */
+struct kvm_mmu_memory_cache {
+       int nobjs;
+       void *objects[KVM_NR_MEM_OBJS];
+};
+
+/*
+ * Modes used for short-hand mode determinition in the world-switch code and
+ * in emulation code.
+ *
+ * Note: These indices do NOT correspond to the value of the CPSR mode bits!

arch/arm/kvm/arm.c new file +200 -0

new file mode 100644
index 0000000..fd6fa9b
@@ -0,0 +1,345 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/kvm_host.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/mman.h>
+#include <linux/sched.h>
+#include <trace/events/kvm.h>
+
+#define CREATE_TRACE_POINTS
+#include "trace.h"
+
+#include <asm/unified.h>
+#include <asm/uaccess.h>
+#include <asm/ptrace.h>
+#include <asm/mman.h>
+#include <asm/cputype.h>
+
+#ifdef REQUIRES_VIRT
+__asm__(".arch_extension       virt");
+#endif
+
+int kvm_arch_hardware_enable(void *garbage)
+{
+       return 0;
+}
+
+int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
+{
+       return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
+}
+
+void kvm_arch_hardware_disable(void *garbage)
+{
+}
+
+int kvm_arch_hardware_setup(void)
+{
+       return 0;
+}
+
+void kvm_arch_hardware_unsetup(void)
+{
+}
+
+void kvm_arch_check_processor_compat(void *rtn)
+{
+       *(int *)rtn = 0;
+}
+
+void kvm_arch_sync_events(struct kvm *kvm)
+{
+}
+
+int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
+{
+       if (type)
+               return -EINVAL;
+
+       return 0;
+}
+
+int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
+{
+       return VM_FAULT_SIGBUS;
+}
+
+void kvm_arch_free_memslot(struct kvm_memory_slot *free,
+                          struct kvm_memory_slot *dont)
+{
+}
+
+int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
+{
+       return 0;
+}
+
+void kvm_arch_destroy_vm(struct kvm *kvm)
+{
+       int i;
+
+       for (i = 0; i < KVM_MAX_VCPUS; ++i) {
+               if (kvm->vcpus[i]) {
+                       kvm_arch_vcpu_free(kvm->vcpus[i]);
+                       kvm->vcpus[i] = NULL;
+               }
+       }
+}
+
+int kvm_dev_ioctl_check_extension(long ext)
+{
+       int r;
+       switch (ext) {
+       case KVM_CAP_USER_MEMORY:
+       case KVM_CAP_DESTROY_MEMORY_REGION_WORKS:
+       case KVM_CAP_ONE_REG:
+               r = 1;
+               break;
+       case KVM_CAP_COALESCED_MMIO:
+               r = KVM_COALESCED_MMIO_PAGE_OFFSET;
+               break;
+       default:
+               r = 0;
+               break;
+       }
+       return r;
+}
+
+long kvm_arch_dev_ioctl(struct file *filp,
+                       unsigned int ioctl, unsigned long arg)
+{
+       return -EINVAL;
+}
+
+int kvm_arch_set_memory_region(struct kvm *kvm,
+                              struct kvm_userspace_memory_region *mem,
+                              struct kvm_memory_slot old,
+                              int user_alloc)
+{
+       return 0;
+}
+
+int kvm_arch_prepare_memory_region(struct kvm *kvm,
+                                  struct kvm_memory_slot *memslot,
+                                  struct kvm_memory_slot old,
+                                  struct kvm_userspace_memory_region *mem,
+                                  int user_alloc)
+{
+       return 0;
+}
+
+void kvm_arch_commit_memory_region(struct kvm *kvm,
+                                  struct kvm_userspace_memory_region *mem,
+                                  struct kvm_memory_slot old,
+                                  int user_alloc)
+{
+}
+
+void kvm_arch_flush_shadow_all(struct kvm *kvm)
+{
+}
+
+void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
+                                  struct kvm_memory_slot *slot)
+{
+}
+
+struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
+{
+       int err;
+       struct kvm_vcpu *vcpu;
+
+       vcpu = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
+       if (!vcpu) {
+               err = -ENOMEM;
+               goto out;
+       }
+
+       err = kvm_vcpu_init(vcpu, kvm, id);
+       if (err)
+               goto free_vcpu;
+
+       return vcpu;
+free_vcpu:
+       kmem_cache_free(kvm_vcpu_cache, vcpu);
+out:
+       return ERR_PTR(err);
+}
+
+void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
+{
+}
+
+void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
+{
+       kvm_arch_vcpu_free(vcpu);
+}
+
+int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
+{
+       return 0;

arch/arm/kvm/arm.c new file +86 -0

+       default:
+               return -EINVAL;
+       }
+}
+
+int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
+{
+       return 0;
+}
+
+void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
+{
+}
+
+void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
+{
+}
+
+void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
+{
+}
+
+int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
+                                       struct kvm_guest_debug *dbg)
+{
+       return -EINVAL;
+}
+
+
+int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
+                                   struct kvm_mp_state *mp_state)
+{
+       return -EINVAL;
+}
+
+int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
+                                   struct kvm_mp_state *mp_state)
+{
+       return -EINVAL;
+}
+
+int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
+{
+       return 0;
+}
+
+int kvm_arch_vcpu_in_guest_mode(struct kvm_vcpu *v)
+{
+       return 0;
+}
+
+int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+       return -EINVAL;
+}
+
+long kvm_arch_vcpu_ioctl(struct file *filp,
+                        unsigned int ioctl, unsigned long arg)
+{
+       struct kvm_vcpu *vcpu = filp->private_data;
+       void __user *argp = (void __user *)arg;
+
+       switch (ioctl) {
+       case KVM_ARM_VCPU_INIT: {
+               struct kvm_vcpu_init init;
+
+               if (copy_from_user(&init, argp, sizeof init))
+                       return -EFAULT;
+
+               return kvm_vcpu_set_target(vcpu, &init);
+
+       }
+       case KVM_SET_ONE_REG:
+       case KVM_GET_ONE_REG: {
+               struct kvm_one_reg reg;
+               if (copy_from_user(&reg, argp, sizeof(reg)))
+                       return -EFAULT;
+               if (ioctl == KVM_SET_ONE_REG)
+                       return kvm_arm_set_reg(vcpu, &reg);
+               else
+                       return kvm_arm_get_reg(vcpu, &reg);
+       }
+       case KVM_GET_REG_LIST: {
+               struct kvm_reg_list __user *user_list = argp;
+               struct kvm_reg_list reg_list;
+               unsigned n;

arch/arm/kvm/emulate.c new file +114 -0

new file mode 100644
index 0000000..690bbb3
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <asm/kvm_emulate.h>
+
+#define REG_OFFSET(_reg) \
+       (offsetof(struct kvm_regs, _reg) / sizeof(u32))
+
+#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs[_num])
+
+static const unsigned long vcpu_reg_offsets[MODE_SYS + 1][16] = {
+       /* FIQ Registers */
+       {
+               USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+               USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+               USR_REG_OFFSET(6), USR_REG_OFFSET(7),
+               REG_OFFSET(fiq_regs[1]), /* r8 */
+               REG_OFFSET(fiq_regs[1]), /* r9 */
+               REG_OFFSET(fiq_regs[2]), /* r10 */
+               REG_OFFSET(fiq_regs[3]), /* r11 */
+               REG_OFFSET(fiq_regs[4]), /* r12 */
+               REG_OFFSET(fiq_regs[5]), /* r13 */
+               REG_OFFSET(fiq_regs[6]), /* r14 */
+               REG_OFFSET(pc)           /* r15 */
+       },
+
+       /* IRQ Registers */
+       {
+               USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+               USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+               USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+               USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+               USR_REG_OFFSET(12),
+               REG_OFFSET(irq_regs[0]), /* r13 */
+               REG_OFFSET(irq_regs[1]), /* r14 */
+               REG_OFFSET(pc)           /* r15 */
+       },
+
+       /* SVC Registers */
+       {
+               USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+               USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+               USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+               USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+               USR_REG_OFFSET(12),
+               REG_OFFSET(svc_regs[0]), /* r13 */
+               REG_OFFSET(svc_regs[1]), /* r14 */
+               REG_OFFSET(pc)           /* r15 */
+       },
+
+       /* ABT Registers */
+       {
+               USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+               USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+               USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+               USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+               USR_REG_OFFSET(12),
+               REG_OFFSET(abt_regs[0]), /* r13 */
+               REG_OFFSET(abt_regs[1]), /* r14 */
+               REG_OFFSET(pc)           /* r15 */
+       },
+
+       /* UND Registers */
+       {
+               USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+               USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+               USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+               USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+               USR_REG_OFFSET(12),
+               REG_OFFSET(und_regs[0]), /* r13 */
+               REG_OFFSET(und_regs[1]), /* r14 */
+               REG_OFFSET(pc)           /* r15 */
+       },
+
+       /* USR Registers */
+       {
+               USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+               USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+               USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+               USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+               USR_REG_OFFSET(12),
+               REG_OFFSET(usr_regs[13]), /* r13 */
+               REG_OFFSET(usr_regs[14]), /* r14 */
+               REG_OFFSET(pc)            /* r15 */
+       },
+
+       /* SYS Registers */
+       {
+               USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+               USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+               USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+               USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+               USR_REG_OFFSET(12),
+               REG_OFFSET(usr_regs[13]), /* r13 */
+               REG_OFFSET(usr_regs[14]), /* r14 */
+               REG_OFFSET(pc)            /* r15 */
+       },
+};
+

arch/arm/kvm/emulate.c new file +2 -0

+       return reg_array + vcpu_reg_offsets[mode][reg_num];
+}

arch/arm/kvm/exports.c new file +11 -0

new file mode 100644
index 0000000..3e38c95
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

arch/arm/kvm/guest.c new file +88 -0

new file mode 100644
index 0000000..19a5389
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/kvm_host.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_emulate.h>
+
+#define VM_STAT(x) { #x, offsetof(struct kvm, stat.x), KVM_STAT_VM }
+#define VCPU_STAT(x) { #x, offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU }
+
+struct kvm_stats_debugfs_item debugfs_entries[] = {
+       { NULL }
+};
+
+int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
+{
+       return 0;
+}
+
+static u64 core_reg_offset_from_id(u64 id)
+{
+       return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
+}
+
+static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+       u32 __user *uaddr = (u32 __user *)(long)reg->addr;
+       struct kvm_regs *regs = &vcpu->arch.regs;
+       u64 off;
+
+       if (KVM_REG_SIZE(reg->id) != 4)
+               return -ENOENT;
+
+       /* Our ID is an index into the kvm_regs struct. */
+       off = core_reg_offset_from_id(reg->id);
+       if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id))
+               return -ENOENT;
+
+       return put_user(((u32 *)regs)[off], uaddr);
+}
+
+static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+       u32 __user *uaddr = (u32 __user *)(long)reg->addr;
+       struct kvm_regs *regs = &vcpu->arch.regs;
+       u64 off, val;
+
+       if (KVM_REG_SIZE(reg->id) != 4)
+               return -ENOENT;
+
+       /* Our ID is an index into the kvm_regs struct. */
+       off = core_reg_offset_from_id(reg->id);
+       if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id))
+               return -ENOENT;
+
+       if (get_user(val, uaddr) != 0)
+               return -EFAULT;
+
+       if (off == KVM_REG_ARM_CORE_REG(cpsr)) {
+               if (__vcpu_mode(val) == 0xf)
+                       return -EINVAL;
+       }
+
+       ((u32 *)regs)[off] = val;
+       return 0;
+}