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clk: samsung: exynos7: Add clocks for MSCL block

PATCH In review Tony K Nadackal 3 participants 7 messages Dec 17, 2014 – Dec 23, 2014

Subsystems (4)
Device tree bindings Common clk Arm Samsung Exynos Samsung SoC clock drivers
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Tony K Nadackal

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#0 lore raw

PATCH 1/1 clk: samsung: exynos7: Add clocks for MSCL block

Add clock support for the MSCL block for Exynos7.

Signed-off-by Tony K Nadackal <[email protected]>
---
 .../devicetree/bindings/clock/exynos7-clock.txt    |   1 +
 drivers/clk/samsung/clk-exynos7.c                  | 124 +++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h            |  40 ++++++-
 3 files changed, 164 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/exynos7-clock.txt +1 -0
index 6d3d5f8..d0e048c 100644
@@ -34,6 +34,7 @@ Required Properties for Clock Controller:
 	- "samsung,exynos7-clock-peris"
 	- "samsung,exynos7-clock-fsys0"
 	- "samsung,exynos7-clock-fsys1"
+	- "samsung,exynos7-clock-mscl"
 
  - reg: physical base address of the controller and the length of
 	memory mapped region.
drivers/clk/samsung/clk-exynos7.c +124 -0

157 lines not on this page · raw message

include/dt-bindings/clock/exynos7-clk.h +39 -1
index e0bad38..dff504a 100644
@@ -17,7 +17,9 @@
 #define DOUT_SCLK_CC_PLL		4
 #define DOUT_SCLK_MFC_PLL		5
 #define DOUT_ACLK_CCORE_133		6
-#define TOPC_NR_CLK			7
+#define DOUT_ACLK_MSCL_532		7
+#define ACLK_MSCL_532			8
+#define TOPC_NR_CLK			9
 
 /* TOP0 */
 #define DOUT_ACLK_PERIC1		1

@@ -90,4 +92,40 @@
 #define ACLK_MMC0			2
 #define FSYS1_NR_CLK			3
 
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532		1
+#define DOUT_PCLK_MSCL			2
+#define ACLK_MSCL_0			3
+#define ACLK_MSCL_1			4
+#define ACLK_JPEG			5
+#define ACLK_G2D			6
+#define ACLK_LH_ASYNC_SI_MSCL_0		7
+#define ACLK_LH_ASYNC_SI_MSCL_1		8
+#define ACLK_AXI2ACEL_BRIDGE		9
+#define ACLK_XIU_MSCLX_0		10
+#define ACLK_XIU_MSCLX_1		11
+#define ACLK_QE_MSCL_0			12
+#define ACLK_QE_MSCL_1			13
+#define ACLK_QE_JPEG			14
+#define ACLK_QE_G2D			15
+#define ACLK_PPMU_MSCL_0		16
+#define ACLK_PPMU_MSCL_1		17
+#define ACLK_MSCLNP_133			18
+#define ACLK_AHB2APB_MSCL0P		19
+#define ACLK_AHB2APB_MSCL1P		20
+
+#define PCLK_MSCL_0			21
+#define PCLK_MSCL_1			22
+#define PCLK_JPEG			23
+#define PCLK_G2D			24
+#define PCLK_QE_MSCL_0			25
+#define PCLK_QE_MSCL_1			26
+#define PCLK_QE_JPEG			27
+#define PCLK_QE_G2D			28
+#define PCLK_PPMU_MSCL_0		29
+#define PCLK_PPMU_MSCL_1		30
+#define PCLK_AXI2ACEL_BRIDGE		31
+#define PCLK_PMU_MSCL			32
+#define MSCL_NR_CLK			33
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
Signature · 1 line
2.2.0
maintainer
#1 lore raw

PATCH 1/1 clk: samsung: exynos7: Add clocks for MSCL block

Hi,

Quoted 14 lines · Tony K Nadackal

Add clock support for the MSCL block for Exynos7.

Signed-off-by Tony K Nadackal <[email protected]>
---
 .../devicetree/bindings/clock/exynos7-clock.txt    |   1 +
 drivers/clk/samsung/clk-exynos7.c                  | 124 +++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h            |  40 ++++++-
 3 files changed, 164 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/exynos7-clock.txt +0 -0
index 6d3d5f8..d0e048c 100644

Documentation/devicetree/bindings/clock/exynos7-clock.txt Required Properties for Clock Controller: · line 37

Quoted 4 lines
Documentation/devicetree/bindings/clock/exynos7-clock.txt +1 -0
@@ -34,6 +34,7 @@ Required Properties for Clock Controller:
 	- "samsung,exynos7-clock-peris"
 	- "samsung,exynos7-clock-fsys0"
 	- "samsung,exynos7-clock-fsys1"
+	- "samsung,exynos7-clock-mscl"

I can't see anything controversial in the patch, but I've got some doubts regarding the compatible string. Is there a SoC named just "Exynos7"? If not, what are exact SoC names the "samsung,exynos7-clock-mscl" compatible is supposed to cover ?
It would be good to list in this file the exact SoCs names this binding applies to, unless there is indeed Exynos7 SoC.

--
Thanks,
Sylwester

author
#2 lore raw

PATCH 1/1 clk: samsung: exynos7: Add clocks for MSCL block

Hi Sylwester,

On Friday, December 19, 2014 9:52 PM Sylwester Nawrocki wrote,

Quoted 9 lines

Hi,

Quoted 6 lines · Tony K Nadackal

Add clock support for the MSCL block for Exynos7.

Signed-off-by Tony K Nadackal <[email protected]>
---
 .../devicetree/bindings/clock/exynos7-clock.txt    |   1 +
 drivers/clk/samsung/clk-exynos7.c                  | 124

+++++++++++++++++++++

Quoted 15 lines

Documentation/devicetree/bindings/clock/exynos7-clock.txt Required Properties for Clock Controller: · line 37

Quoted 13 lines
 include/dt-bindings/clock/exynos7-clk.h            |  40 ++++++-
 3 files changed, 164 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/exynos7-clock.txt +1 -0
index 6d3d5f8..d0e048c 100644
@@ -34,6 +34,7 @@ Required Properties for Clock Controller:
 	- "samsung,exynos7-clock-peris"
 	- "samsung,exynos7-clock-fsys0"
 	- "samsung,exynos7-clock-fsys1"
+	- "samsung,exynos7-clock-mscl"

I can't see anything controversial in the patch, but I've got some doubts

regarding

Quoted 1 line

the compatible string. Is there a SoC named just "Exynos7"?

Yes, We have an SoC named Exynos7.
Please refer http://www.spinics.net/lists/linux-samsung-soc/msg36765.html

Quoted 3 lines

If not, what are exact SoC names the "samsung,exynos7-clock-mscl" compatible is supposed to cover ?
It would be good to list in this file the exact SoCs names this binding

applies to,

Quoted 5 lines

unless there is indeed Exynos7 SoC.

--
Thanks,
Sylwester

Regards,
Tony

maintainer Applied
#3 lore raw

PATCH 1/1 clk: samsung: exynos7: Add clocks for MSCL block

Quoted 14 lines · Tony K Nadackal
Quoted 13 lines
Quoted 13 lines
(quoted diff) +0 -0
Quoted 9 lines

Documentation/devicetree/bindings/clock/exynos7-clock.txt Required Properties for Clock Controller: · line 37

Quoted 9 lines

b/Documentation/devicetree/bindings/clock/exynos7-clock.txt index 6d3d5f8..d0e048c 100644

Documentation/devicetree/bindings/clock/exynos7-clock.txt +1 -0
@@ -34,6 +34,7 @@ Required Properties for Clock Controller:
 	- "samsung,exynos7-clock-peris"
 	- "samsung,exynos7-clock-fsys0"
 	- "samsung,exynos7-clock-fsys1"
+	- "samsung,exynos7-clock-mscl"

I can't see anything controversial in the patch, but I've got some doubts regarding the compatible string. Is there a SoC named just "Exynos7"?

Quoted 2 lines

Yes, We have an SoC named Exynos7.
Please refer http://www.spinics.net/lists/linux-samsung-soc/msg36765.html

I've queued this patch for 3.20. Would be nice to have a Reviewed-by tag from someone else who has access to the SoC documentation though.

Is Exynos7420 User Manual applicable to this?
Exynos 7 (Octa?) seems like a marketing name to me. In technical documents there are usually more specific names used, like exynos7410 or exynos7420.

Signature · 2 lines
Regards,
Sylwester
author
#4 lore raw

PATCH 1/1 clk: samsung: exynos7: Add clocks for MSCL block

Hi Sylwester,

On Monday, December 22, 2014 8:28 PM Sylwester Nawrocki,

[snip]

Quoted 2 lines

I've queued this patch for 3.20. Would be nice to have a Reviewed-by tag from someone else who has access to the SoC documentation though.

Pankaj Dubey has reviewed this patch [1].
He has pointed out that there is an extra tab space in the patch. You want me to send a revised version of this patch?

[1] http://www.mail-archive.com/[email protected]/msg40329.html

Quoted 8 lines

Is Exynos7420 User Manual applicable to this?
Exynos 7 (Octa?) seems like a marketing name to me. In technical documents there are usually more specific names used, like exynos7410 or exynos7420.

--
Regards,
Sylwester

Regards,
Tony

Reviewed-by on v1 1/1
#5 lore raw
In reply to Tony K Nadackal

Hi Tony,

Quoted 27 lines · tony nadackal

Add clock support for the MSCL block for Exynos7.

Signed-off-by Tony K Nadackal <[email protected]>

---
.../devicetree/bindings/clock/exynos7-clock.txt | 1 +

  drivers/clk/samsung/clk-exynos7.c                  | 124 +++++++++++++++++++++
  include/dt-bindings/clock/exynos7-clk.h            |  40 ++++++-
  3 files changed, 164 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/exynos7-clock.txt +1 -0
index 6d3d5f8..d0e048c 100644
@@ -34,6 +34,7 @@ Required Properties for Clock Controller:
  	- "samsung,exynos7-clock-peris"
  	- "samsung,exynos7-clock-fsys0"
  	- "samsung,exynos7-clock-fsys1"
+	- "samsung,exynos7-clock-mscl"
 
   - reg: physical base address of the controller and the length of
  	memory mapped region.
drivers/clk/samsung/clk-exynos7.c +0 -0
index a79bf23..95c1160 100644

drivers/clk/samsung/clk-exynos7.c line 37

Quoted 4 lines
drivers/clk/samsung/clk-exynos7.c +1 -0
@@ -34,6 +34,7 @@
  #define DIV_TOPC0		0x0600
  #define DIV_TOPC1		0x0604
  #define DIV_TOPC3		0x060C
+#define	ENABLE_ACLK_TOPC1	0x0804

nit: Tab space between #define and ENABLE_ACLK_TOPC1, should be removed.

I verified register settings and clock relationships are as per UM I have with me. So other than above nit, everything looks fine.

Reviewed-by Pankaj Dubey <[email protected]>

Thanks,
Pankaj Dubey

maintainer
#6 lore raw

Hi Pankaj,

Quoted 12 lines · Pankaj Dubey
Quoted 9 lines
drivers/clk/samsung/clk-exynos7.c +0 -0

drivers/clk/samsung/clk-exynos7.c line 37

Quoted 8 lines

index a79bf23..95c1160 100644

drivers/clk/samsung/clk-exynos7.c +1 -0
@@ -34,6 +34,7 @@
  #define DIV_TOPC0		0x0600
  #define DIV_TOPC1		0x0604
  #define DIV_TOPC3		0x060C
+#define	ENABLE_ACLK_TOPC1	0x0804

nit: Tab space between #define and ENABLE_ACLK_TOPC1, should be removed.

Quoted 4 lines

I verified register settings and clock relationships are as per UM I have with me. So other than above nit, everything looks fine.

Reviewed-by Pankaj Dubey <[email protected]>

Thanks for you review, I have already fixed the whitespace issue when applying.

--
Regards,
Sylwester