Microblaze: PULL request

Hi,

Please pull u-boot-microblaze branch.
File changes are below.

Thanks,
Michal Simek

 Makefile                          |    9 +-
 board/xilinx/xupv2p/Makefile      |   21 +--
 board/xilinx/xupv2p/config.mk     |    6 +-
 board/xilinx/xupv2p/xparameters.h |   27 ++--
 common/cmd_jffs2.c                |   52 ++++--
 common/cmd_mfsl.c                 |   11 +-
 cpu/microblaze/cache.c            |    2 +-
 cpu/microblaze/start.S            |    6 +-
 cpu/microblaze/timer.c            |    7 +
 drivers/net/Makefile              |   45 +++++
 drivers/net/xilinx_emac.c         |  372 
++++++++++++++++++++++++++++++++++++
 drivers/net/xilinx_emac.h         |  128 +++++++++++++
 drivers/net/xilinx_emaclite.c     |  378 
+++++++++++++++++++++++++++++++++++++
 drivers/serial_xuartlite.c        |    2 +-
 fs/Makefile                       |    2 +-
 fs/romfs/Makefile                 |   49 +++++
 fs/romfs/romfs.c                  |  270 ++++++++++++++++++++++++++
 include/configs/ml401.h           |    1 +
 include/configs/suzaku.h          |    3 +
 include/configs/xupv2p.h          |   58 +++++-
 lib_microblaze/time.c             |    8 +
 21 files changed, 1385 insertions(+), 72 deletions(-)
 mode change 100755 => 100644 board/xilinx/ml401/xparameters.h
 mode change 100755 => 100644 cpu/microblaze/cache.c
 mode change 100755 => 100644 cpu/microblaze/interrupts.c
 mode change 100755 => 100644 cpu/microblaze/irq.S
 create mode 100644 drivers/net/Makefile
 create mode 100644 drivers/net/xilinx_emac.c
 create mode 100644 drivers/net/xilinx_emac.h
 create mode 100644 drivers/net/xilinx_emaclite.c
 create mode 100644 fs/romfs/Makefile
 create mode 100644 fs/romfs/romfs.c
 mode change 100755 => 100644 include/asm-microblaze/asm.h 

I don't think I've seen any of these changes posted on the list for review. They need to be reviewed before being merged into mainline. Especially considering that some of the changes touch common code (not just microblaze).

Cheers,
g.

Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely at secretlab.ca
(403) 399-0195

On more thing; make sure you add your 'signed-off-by' line to your commits.

Cheers,
g.

Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely at secretlab.ca
(403) 399-0195

Hi Grant,

I thought please pull these changes to u-boot testing branch not to mainline.

These files were send in ROMFS patch 23.June 07

New files for supporting EMAC and EMACLITE interface. Old support files are in repository too.
I want to remove xilinx large files from U-Boot source tree. Emac driver use PPC405 core too (ml300 board).
I tested it for Microblaze CPU and you can test it for PPC405 and give me a respond.
We were talking about at the end of March.

Little name changes - because xuartlite serial interface isn't only one which can be use with Microblaze CPU.
I think that can be helpful for PPC405 embedded core too that can use uartlite serial interface.

cmd_mfsl consist of only Microblaze dependent commands.

Microblaze dependent files

Best regards,
Michal Simek

Even patches pulled into testing need to be reviewed. Wolfgang does merge testing into mainline periodically after all.

Heh, I even posted on that thread. :) Okay, I went back and took a look at this patch. Mostly looks good, but I had a few comments. Take a read through and let me know what you think.

These patches I'm especially interested in. I would like to review them before they are committed.

Fair enough, but you should still post.

ditto

Again, this stuff should hit the list before merging. If there are no comments, then as microblaze custodian, you have discretion to add them to the microblaze tree and get them merged, but they should still hit the list *first* in case there are comments.

Cheers,
g.

Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely at secretlab.ca
(403) 399-0195

Grant,

I know.

I know many developers needs these driver. For Microblaze I created configuration file. You can download it at www.monstr.eu
Emac is supported without DMA support. I plan to add support for simple and scatter gather DMA too.
I will wait for your review.

OK. I will be good guy. If you want I will send all changes to mailing list. Microblaze changes are really cosmetic.

Michal Simek

Hi Grant and everybody,

my patches are below. All patches are in u-boot-microblaze branch.

Emac driver for Microblaze.

Michal Simek

index bfa3846..146f647 100644
@@ -143,7 +143,7 @@ ifeq ($(ARCH),m68k)
 CROSS_COMPILE = m68k-elf-
 endif
 ifeq ($(ARCH),microblaze)
-CROSS_COMPILE = mb-
+CROSS_COMPILE = microblaze-uclinux-
 endif
 ifeq ($(ARCH),blackfin)
 CROSS_COMPILE = bfin-uclinux-

@@ -199,7 +199,7 @@ LIBS += cpu/ixp/npe/libnpe.a
 endif
 LIBS += lib_$(ARCH)/lib$(ARCH).a
 LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a 

fs/jffs2/libjffs2.a \
- fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
+ fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a fs/romfs/libromfs.a LIBS += net/libnet.a
LIBS += disk/libdisk.a
LIBS += rtc/librtc.a
@@ -207,6 +207,7 @@ LIBS += dtt/libdtt.a
LIBS += drivers/libdrivers.a
LIBS += drivers/nand/libnand.a
LIBS += drivers/nand_legacy/libnand_legacy.a
+LIBS += drivers/net/libnetdrv.a
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
endif
@@ -316,14 +317,14 @@ depend dep:
tags ctags:

   ctags -w -o $(OBJTREE)/ctags `find $(SUBDIRS) include \
     lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
-    fs/cramfs fs/fat fs/fdos fs/jffs2 \
+    fs/cramfs fs/fat fs/fdos fs/jffs2 fs/romfs\
     net disk rtc dtt drivers drivers/sk98lin common \
    \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`

etags:

   etags -a -o $(OBJTREE)/etags `find $(SUBDIRS) include \
     lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
-    fs/cramfs fs/fat fs/fdos fs/jffs2 \
+    fs/cramfs fs/fat fs/fdos fs/jffs2 fs/romfs\
     net disk rtc dtt drivers drivers/sk98lin common \
    \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`

0x01 };
+
+static XEmac Emac;
+
+void eth_halt(void)
+{
+ return;
+}
+
+int eth_init(bd_t * bis)
+{
+ u32 HelpReg;
+#ifdef DEBUG
+ printf("EMAC Initialization Started\n\r");
+#endif
+ if (Emac.IsStarted) {
+ puts("Emac is started\n");
+ return 0;
+ }
+
+ memset (&Emac, 0, sizeof (XEmac));
+
+ Emac.BaseAddress = XILINX_EMAC_BASEADDR;
+
+ /* Setting up FIFOs */
+ Emac.RecvFifo.RegBaseAddress = Emac.BaseAddress +
+ XEM_PFIFO_RXREG_OFFSET;
+ Emac.RecvFifo.DataBaseAddress = Emac.BaseAddress +
+ XEM_PFIFO_RXDATA_OFFSET;
+ out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); +
+ Emac.SendFifo.RegBaseAddress = Emac.BaseAddress +
+ XEM_PFIFO_TXREG_OFFSET;
+ Emac.SendFifo.DataBaseAddress = Emac.BaseAddress +
+ XEM_PFIFO_TXDATA_OFFSET;
+ out_be32 (Emac.SendFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); +
+ /* Reset the entire IPIF */
+ out_be32 (Emac.BaseAddress + XIIF_V123B_RESETR_OFFSET,
+ XIIF_V123B_RESET_MASK);
+
+ /* Stopping EMAC for setting up MAC */
+ HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET);
+ HelpReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+ out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg);
+
+ if (!getenv("ethaddr")) {
+ memcpy(bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH);
+ }
+
+ /* Set the device station address high and low registers */
+ HelpReg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1];
+ out_be32 (Emac.BaseAddress + XEM_SAH_OFFSET, HelpReg);
+ HelpReg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) |
+ (bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5];
+ out_be32 (Emac.BaseAddress + XEM_SAL_OFFSET, HelpReg);
+
+
+ HelpReg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
+ XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK |
+ XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK;
+ out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg);
+
+ Emac.IsStarted = 1;
+
+ /* Enable the transmitter, and receiver */
+ HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET);
+ HelpReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
+ HelpReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+ out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg);
+
+ printf("EMAC Initialization complete\n\r");
+ return 0;
+}
+
+int eth_send(volatile void *ptr, int len)
+{
+ u32 IntrStatus;
+ u32 XmitStatus;
+ u32 FifoCount;
+ u32 WordCount;
+ u32 ExtraByteCount;
+ u32 *WordBuffer = (u32 *) ptr;
+
+ if (len > ENET_MAX_MTU)
+ len = ENET_MAX_MTU;
+
+ /*

+  * Check for overruns and underruns for the transmit status and length
+  * FIFOs and make sure the send packet FIFO is not deadlocked.
+  * Any of these conditions is bad enough that we do not want to
+  * continue. The upper layer software should reset the device to resolve
+  * the error.
+  */

+ IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET);
+ if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+ XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+#ifdef DEBUG
+ puts ("Transmitting overrun error\n");
+#endif
+ return 0;
+ } else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+ XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+#ifdef DEBUG
+ puts ("Transmitting underrun error\n");
+#endif
+ return 0;
+ } else if (in_be32 (Emac.SendFifo.RegBaseAddress +
+ XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) {
+#ifdef DEBUG
+ puts("Transmitting fifo error\n");
+#endif
+ return 0;
+ }
+
+ /*

+  * Before writing to the data FIFO, make sure the length FIFO is not
+  * full. The data FIFO might not be full yet even though the length FIFO
+  * is. This avoids an overrun condition on the length FIFO and keeps the
+  * FIFOs in sync.
+  *
+  * Clear the latched LFIFO_FULL bit so next time around the most
+  * current status is represented
+  */

+ if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
+ out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, IntrStatus
+ & XEM_EIR_XMIT_LFIFO_FULL_MASK);
+#ifdef DEBUG
+ puts ("Fifo is full\n");
+#endif
+ return 0;
+ }
+
+ /* get the count of how many words may be inserted into the FIFO */
+ FifoCount = in_be32 (Emac.SendFifo.RegBaseAddress +
+ XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
+ WordCount = len >> 2;
+ ExtraByteCount = len & 0x3;
+
+ if (FifoCount < WordCount) {
+#ifdef DEBUG
+ puts ("Sending packet is larger then size of FIFO\n"); +#endif
+ return 0;
+ }
+
+ for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
+ out_be32 (Emac.SendFifo.DataBaseAddress, WordBuffer[FifoCount]);
+ }
+ if (ExtraByteCount > 0) {
+ u32 LastWord = 0;
+ u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
+
+ if (ExtraByteCount == 1) {
+ LastWord = ExtraBytesBuffer[0] << 24;
+ } else if (ExtraByteCount == 2) {
+ LastWord = ExtraBytesBuffer[0] << 24 |
+ ExtraBytesBuffer[1] << 16;
+ } else if (ExtraByteCount == 3) {
+ LastWord = ExtraBytesBuffer[0] << 24 |
+ ExtraBytesBuffer[1] << 16 |
+ ExtraBytesBuffer[2] << 8;
+ }
+ out_be32 (Emac.SendFifo.DataBaseAddress, LastWord);
+ }
+
+ /* Loop on the MAC's status to wait for any pause to complete */
+ IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET);
+ while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
+ IntrStatus = in_be32 ((Emac.BaseAddress) +
+ XIIF_V123B_IISR_OFFSET);
+ /* Clear the pause status from the transmit status register */
+ out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET,
+ IntrStatus & XEM_EIR_XMIT_PAUSE_MASK);
+ }
+
+ /*
+ * Set the MAC's transmit packet length register to tell it to transmit
+ */
+ out_be32 (Emac.BaseAddress + XEM_TPLR_OFFSET, len);
+
+ /*

+  * Loop on the MAC's status to wait for the transmit to complete.
+  * The transmit status is in the FIFO when the XMIT_DONE bit is set.
+  */

+ do {
+ IntrStatus = in_be32 ((Emac.BaseAddress) +
+ XIIF_V123B_IISR_OFFSET);
+ }
+ while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0); +
+ XmitStatus = in_be32 (Emac.BaseAddress + XEM_TSR_OFFSET); +
+ if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+ XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+#ifdef DEBUG
+ puts ("Transmitting overrun error\n");
+#endif
+ return 0;
+ } else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+ XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+#ifdef DEBUG
+ puts ("Transmitting underrun error\n");
+#endif
+ return 0;
+ }
+
+ /* Clear the interrupt status register of transmit statuses */
+ out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET,
+ IntrStatus & XEM_EIR_XMIT_ALL_MASK);
+
+ /*

+  * Collision errors are stored in the transmit status register
+  * instead of the interrupt status register
+  */

+ if ((XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
+ (XmitStatus & XEM_TSR_LATE_COLLISION_MASK)) {
+#ifdef DEBUG
+ puts ("Transmitting collision error\n");
+#endif
+ return 0;
+ }
+ return 1;
+}
+
+int eth_rx(void)
+{
+ u32 PktLength;
+ u32 IntrStatus;
+ u32 FifoCount;
+ u32 WordCount;
+ u32 ExtraByteCount;
+ u32 LastWord;
+ u8 *ExtraBytesBuffer;
+
+ if (in_be32 (Emac.RecvFifo.RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET)
+ & XPF_DEADLOCK_MASK) {
+ out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); +#ifdef DEBUG
+ puts ("Receiving FIFO deadlock\n");
+#endif
+ return 0;
+ }
+
+ /*
+ * Get the interrupt status to know what happened (whether an error occurred
+ * and/or whether frames have been received successfully). When clearing the
+ * intr status register, clear only statuses that pertain to receive.
+ */
+ IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET);
+ /*

+  * Before reading from the length FIFO, make sure the length FIFO is not
+  * empty. We could cause an underrun error if we try to read from an
+  * empty FIFO.
+  */

+ if (!(IntrStatus & XEM_EIR_RECV_DONE_MASK)) {
+#ifdef DEBUG
+ /* puts("Receiving FIFO is empty\n"); */
+#endif
+ return 0;
+ }
+
+ /*

+  * Determine, from the MAC, the length of the next packet available
+  * in the data FIFO (there should be a non-zero length here)
+  */

+ PktLength = in_be32 (Emac.BaseAddress + XEM_RPLR_OFFSET);
+ if (!PktLength) {
+ return 0;
+ }
+
+ /*

+  * Write the RECV_DONE bit in the status register to clear it. This bit
+  * indicates the RPLR is non-empty, and we know it's set@this point.
+  * We clear it so that subsequent entry into this routine will reflect
+  * the current status. This is done because the non-empty bit is latched
+  * in the IPIF, which means it may indicate a non-empty condition even
+  * though there is something in the FIFO.
+  */

+ out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET,
+ XEM_EIR_RECV_DONE_MASK);
+
+ FifoCount = in_be32 (Emac.RecvFifo.RegBaseAddress +
+ XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
+
+ if ((FifoCount * 4) < PktLength) {
+#ifdef DEBUG
+ puts ("Receiving FIFO is smaller than packet size.\n"); +#endif
+ return 0;
+ }
+
+ WordCount = PktLength >> 2;
+ ExtraByteCount = PktLength & 0x3;
+
+ for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
+ etherrxbuff[FifoCount] =
+ in_be32 (Emac.RecvFifo.DataBaseAddress);
+ }
+
+ /*

+  * if there are extra bytes to handle, read the last word from the FIFO
+  * and insert the extra bytes into the buffer
+  */

+ if (ExtraByteCount > 0) {
+ ExtraBytesBuffer = (u8 *) (etherrxbuff + WordCount); +
+ LastWord = in_be32 (Emac.RecvFifo.DataBaseAddress); +
+ /*

+   * one extra byte in the last word, put the byte into the next
+   * location of the buffer, bytes in a word of the FIFO are
+   * ordered from most significant byte to least
+   */

+ if (ExtraByteCount == 1) {
+ ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
+ } else if (ExtraByteCount == 2) {
+ ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
+ ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
+ } else if (ExtraByteCount == 3) {

+   ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
+   ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
+   ExtraBytesBuffer[2] = (u8) (LastWord >> 8);

+ }
+ }
+ NetReceive((uchar *)etherrxbuff, PktLength);
+ return 1;
+}
+#endif

empty */
+#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */
+#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */
+#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo
+ * overrun */
+#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo
+ * underrun */
+#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo
+ * overrun */
+#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo
+ * underrun */
+#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo
+ * overrun */
+#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo
+ * underrun */
+#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt
+ * received */
+
+/*
+ * EMAC Control Register (ECR)
+ */

+#define XEM_ECR_FULL_DUPLEX_MASK  0x80000000UL /* Full duplex mode */
+#define XEM_ECR_XMIT_RESET_MASK   0x40000000UL /* Reset transmitter */
+#define XEM_ECR_XMIT_ENABLE_MASK  0x20000000UL /* Enable transmitter */
+#define XEM_ECR_RECV_RESET_MASK   0x10000000UL /* Reset receiver */
+#define XEM_ECR_RECV_ENABLE_MASK  0x08000000UL /* Enable receiver */
+#define XEM_ECR_PHY_ENABLE_MASK   0x04000000UL /* Enable PHY */

+#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL /* Enable xmit pad
+ * insert */
+#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL /* Enable xmit FCS
+ * insert */
+#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL /* Enable unicast
+ * addr */
+#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL /* Enable broadcast
+ * addr */
+
+/* Transmit Status Register (TSR) */
+#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */
+#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */

XEL_TSR_PROGRAM_MASK)
+
+/* Transmit packet length upper byte */
+#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
+/* Transmit packet length lower byte */
+#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
+
+/* Recv complete */
+#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
+/* Recv interrupt enable bit */
+#define XEL_RSR_RECV_IE_MASK 0x00000008UL
+
+typedef struct {
+ unsigned int BaseAddress; /* Base address for device (IPIF) */
+ unsigned int NextTxBufferToUse; /* Next TX buffer to write to */
+ unsigned int NextRxBufferToUse; /* Next RX buffer to read from */
+ unsigned char DeviceId; /* Unique ID of device - for future */ +} XEmacLite;
+
+static XEmacLite EmacLite;
+
+static char etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ +
+/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ +#ifdef CFG_ENV_IS_NOWHERE
+static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
+#endif
+
+void XEmacLite_AlignedRead (u32 * SrcPtr, void *DestPtr, unsigned ByteCount)
+{
+ unsigned i;
+ unsigned Length = ByteCount;
+ u32 AlignBuffer;
+ u32 *To32Ptr;
+ u32 *From32Ptr;
+ u8 *To8Ptr;
+ u8 *From8Ptr;
+
+ From32Ptr = (u32 *) SrcPtr;
+
+ /* Word aligned buffer, no correction needed. */
+ To32Ptr = (u32 *) DestPtr;
+ while (Length > 3) {
+ *To32Ptr++ = *From32Ptr++;
+ Length -= 4;
+ }
+ To8Ptr = (u8 *) To32Ptr;
+
+ AlignBuffer = *From32Ptr++;
+ From8Ptr = (u8 *) & AlignBuffer;
+
+ for (i = 0; i < Length; i++) {
+ *To8Ptr++ = *From8Ptr++;
+ }
+}
+
+void XEmacLite_AlignedWrite (void *SrcPtr, u32 * DestPtr, unsigned ByteCount)
+{
+ unsigned i;
+ unsigned Length = ByteCount;
+ u32 AlignBuffer;
+ u32 *To32Ptr;
+ u32 *From32Ptr;
+ u8 *To8Ptr;
+ u8 *From8Ptr;
+ To32Ptr = DestPtr;
+
+ From32Ptr = (u32 *) SrcPtr;
+ while (Length > 3) {
+
+ *To32Ptr++ = *From32Ptr++;
+ Length -= 4;
+ }
+
+ AlignBuffer = 0;
+ To8Ptr = (u8 *) & AlignBuffer;
+ From8Ptr = (u8 *) From32Ptr;
+
+ for (i = 0; i < Length; i++) {
+ *To8Ptr++ = *From8Ptr++;
+ }
+
+ *To32Ptr++ = AlignBuffer;
+}
+
+void eth_halt (void)
+{
+#ifdef DEBUG
+ puts ("eth_halt\n");
+#endif
+}
+
+int eth_init (bd_t * bis)
+{
+#ifdef DEBUG
+ puts ("EmacLite Initialization Started\n");
+#endif
+ memset (&EmacLite, 0, sizeof (XEmacLite));
+ EmacLite.BaseAddress = XILINX_EMACLITE_BASEADDR;
+
+#ifdef CFG_ENV_IS_NOWHERE
+ memcpy (bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH); +#endif
+/*
+ * TX - TX_PING & TX_PONG initialization
+ */
+ /* Restart PING TX */
+ out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, 0);
+ /* Copy MAC address */
+ XEmacLite_AlignedWrite (bis->bi_enetaddr,
+ EmacLite.BaseAddress, ENET_ADDR_LENGTH);
+ /* Set the length */
+ out_be32 (EmacLite.BaseAddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+ /* Update the MAC address in the EMAC Lite */
+ out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
+ /* Wait for EMAC Lite to finish with the MAC address update */
+ while ((in_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET) &
+ XEL_TSR_PROG_MAC_ADDR) != 0) ;
+
+#ifdef XILINX_EMACLITE_TX_PING_PONG
+ /* The same operation with PONG TX */
+ out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
+ XEmacLite_AlignedWrite (bis->bi_enetaddr,
+ EmacLite.BaseAddress + XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
+ out_be32 (EmacLite.BaseAddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+ out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
+ XEL_TSR_PROG_MAC_ADDR);
+ while ((in_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET +
+ XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ;
+#endif
+
+/*
+ * RX - RX_PING & RX_PONG initialization
+ */
+ /* Write out the value to flush the RX buffer */
+ out_be32 (EmacLite.BaseAddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); +#ifdef XILINX_EMACLITE_RX_PING_PONG
+ out_be32 (EmacLite.BaseAddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
+ XEL_RSR_RECV_IE_MASK);
+#endif
+
+#ifdef DEBUG
+ puts ("EmacLite Initialization complete\n");
+#endif
+ return 0;
+}
+
+int XEmacLite_TxBufferAvailable (XEmacLite * InstancePtr)
+{
+ u32 Register;
+ u32 TxPingBusy;
+ u32 TxPongBusy;
+ /*

+  * Read the other buffer register
+  * and determine if the other buffer is available
+  */

+ Register = in_be32 (InstancePtr->BaseAddress +
+ InstancePtr->NextTxBufferToUse + 0);
+ TxPingBusy = ((Register & XEL_TSR_XMIT_BUSY_MASK) ==
+ XEL_TSR_XMIT_BUSY_MASK);
+
+ Register = in_be32 (InstancePtr->BaseAddress +
+ (InstancePtr->NextTxBufferToUse ^ XEL_TSR_OFFSET) + 0);
+ TxPongBusy = ((Register & XEL_TSR_XMIT_BUSY_MASK) ==
+ XEL_TSR_XMIT_BUSY_MASK);
+
+ return (!(TxPingBusy && TxPongBusy));
+}
+
+int eth_send (volatile void *ptr, int len) {
+
+ unsigned int Register;
+ unsigned int BaseAddress;
+
+ unsigned maxtry = 1000;
+
+ if (len > ENET_MAX_MTU)
+ len = ENET_MAX_MTU;
+
+ while (!XEmacLite_TxBufferAvailable (&EmacLite) && maxtry) {
+ udelay (10);
+ maxtry--;
+ }
+
+ if (!maxtry) {

+  printf ("Error: Timeout waiting for ethernet TX buffer\n");
+  /* Restart PING TX */
+  out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, 0);

+#ifdef XILINX_EMACLITE_TX_PING_PONG
+ out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET +
+ XEL_BUFFER_OFFSET, 0);
+#endif
+ return 0;
+ }
+
+ /* Determine the expected TX buffer address */
+ BaseAddress = (EmacLite.BaseAddress + EmacLite.NextTxBufferToUse); +
+ /* Determine if the expected buffer address is empty */
+ Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
+ if (((Register & XEL_TSR_XMIT_BUSY_MASK) == 0)
+ && ((in_be32 ((BaseAddress) + XEL_TSR_OFFSET)
+ & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
+
+#ifdef XILINX_EMACLITE_TX_PING_PONG
+ EmacLite.NextTxBufferToUse ^= XEL_BUFFER_OFFSET; +#endif
+#ifdef DEBUG
+ printf ("Send packet from 0x%x\n", BaseAddress); +#endif

+  /* Write the frame to the buffer */
+  XEmacLite_AlignedWrite (ptr, (u32 *) BaseAddress, len);
+  out_be32 (BaseAddress + XEL_TPLR_OFFSET,(len &
+   (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
+  Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
+  Register |= XEL_TSR_XMIT_BUSY_MASK;
+  if ((Register & XEL_TSR_XMIT_IE_MASK) != 0) {
+   Register |= XEL_TSR_XMIT_ACTIVE_MASK;
+  }
+  out_be32 (BaseAddress + XEL_TSR_OFFSET, Register);
+  return 1;

+ }
+#ifdef XILINX_EMACLITE_TX_PING_PONG
+ /* Switch to second buffer */
+ BaseAddress ^= XEL_BUFFER_OFFSET;
+ /* Determine if the expected buffer address is empty */
+ Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
+ if (((Register & XEL_TSR_XMIT_BUSY_MASK) == 0)
+ && ((in_be32 ((BaseAddress) + XEL_TSR_OFFSET)
+ & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
+#ifdef DEBUG
+ printf ("Send packet from 0x%x\n", BaseAddress); +#endif

+  /* Write the frame to the buffer */
+  XEmacLite_AlignedWrite (ptr, (u32 *) BaseAddress, len);
+  out_be32 (BaseAddress + XEL_TPLR_OFFSET,(len &
+   (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
+  Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
+  Register |= XEL_TSR_XMIT_BUSY_MASK;
+  if ((Register & XEL_TSR_XMIT_IE_MASK) != 0) {
+   Register |= XEL_TSR_XMIT_ACTIVE_MASK;
+  }
+  out_be32 (BaseAddress + XEL_TSR_OFFSET, Register);
+  return 1;

+ }
+#endif
+ puts ("Error while sending frame\n");
+ return 0;
+}
+
+int eth_rx (void)
+{
+ unsigned int Length;
+ unsigned int Register;
+ unsigned int BaseAddress;
+
+ BaseAddress = EmacLite.BaseAddress + EmacLite.NextRxBufferToUse;
+ Register = in_be32 (BaseAddress + XEL_RSR_OFFSET); +#ifdef DEBUG
+ printf ("Testing data at address 0x%x\n", BaseAddress); +#endif
+ if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { +#ifdef XILINX_EMACLITE_RX_PING_PONG
+ EmacLite.NextRxBufferToUse ^= XEL_BUFFER_OFFSET;
+#endif
+ } else {
+#ifndef XILINX_EMACLITE_RX_PING_PONG
+#ifdef DEBUG
+ printf ("No data was available - address 0x%x\n", BaseAddress); +#endif
+ return 0;
+#else

+  BaseAddress ^= XEL_BUFFER_OFFSET;
+  Register = in_be32 (BaseAddress + XEL_RSR_OFFSET);
+  if ((Register & XEL_RSR_RECV_DONE_MASK) !=

+ XEL_RSR_RECV_DONE_MASK) {
+#ifdef DEBUG
+ printf ("No data was available - address 0x%x\n",
+ BaseAddress);
+#endif
+ return 0;
+ }
+#endif
+ }
+ /* Get the length of the frame that arrived */
+ switch(((in_be32(BaseAddress + XEL_RXBUFF_OFFSET + 0xC)) &
+ 0xFFFF0000 ) >> 16) {
+ case 0x806:
+ Length = 42 + 20; /* FIXME size of ARP */
+#ifdef DEBUG
+ puts ("ARP Packet\n");
+#endif
+ break;
+ case 0x800:

+   Length = 14 + 14 +
+   (((in_be32(BaseAddress + XEL_RXBUFF_OFFSET + 0x10)) &
+   0xFFFF0000) >> 16); /* FIXME size of IP packet */

+#ifdef DEBUG
+ puts("IP Packet\n");
+#endif
+ break;
+ default:
+#ifdef DEBUG
+ puts("Other Packet\n");
+#endif
+ Length = ENET_MAX_MTU;
+ break;
+ }
+
+ XEmacLite_AlignedRead ((BaseAddress + XEL_RXBUFF_OFFSET),
+ etherrxbuff, Length);
+
+ /* Acknowledge the frame */
+ Register = in_be32 (BaseAddress + XEL_RSR_OFFSET);
+ Register &= ~XEL_RSR_RECV_DONE_MASK;
+ out_be32 (BaseAddress + XEL_RSR_OFFSET, Register);
+
+#ifdef DEBUG
+ printf ("Packet receive from 0x%x, length %dB\n", BaseAddress, Length); +#endif
+ NetReceive ((uchar *) etherrxbuff, Length);
+ return 1;
+
+}
+#endif

NAK.

Please keep lists sorted.

...

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
HR Manager to job candidate "I see you've had no  computer  training.
Although  that  qualifies  you  for upper management, it means you're
under-qualified for our entry level positions."

Hi,

romfs is at the end of list but ext2 position is wrong. Isn't not my code.

file: Makefile
LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a

I fix this.

Best regards,
Michal Simek

Weird. Looks like you're getting some mailer damage. All your tabs seem to have been converted to single spaces. What are you using to send them?

Cheers,
g.

Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely at secretlab.ca
(403) 399-0195

Emaclite driver for Microblaze

index e69de29..99e7035 100644
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <config.h>
+#include <asm/io.h>
+
+#ifdef XILINX_EMACLITE_BASEADDR
+
+#undef DEBUG
+
+#define ENET_MAX_MTU  PKTSIZE
+#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
+#define ENET_ADDR_LENGTH 6
+
+/* EmacLite constants */
+#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
+#define XEL_TPLR_OFFSET  0x07F4 /* Tx packet length */
+#define XEL_TSR_OFFSET  0x07FC /* Tx status */
+#define XEL_RSR_OFFSET  0x17FC /* Rx status */
+#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
+
+/* Xmit complete */
+#define XEL_TSR_XMIT_BUSY_MASK  0x00000001UL
+/* Xmit interrupt enable bit */
+#define XEL_TSR_XMIT_IE_MASK  0x00000008UL
+/* Buffer is active, SW bit only */
+#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
+/* Program the MAC address */
+#define XEL_TSR_PROGRAM_MASK  0x00000002UL
+/* define for programming the MAC address into the EMAC Lite */
+#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | 

XEL_TSR_PROGRAM_MASK)
+
+/* Transmit packet length upper byte */
+#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
+/* Transmit packet length lower byte */
+#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
+
+/* Recv complete */
+#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
+/* Recv interrupt enable bit */
+#define XEL_RSR_RECV_IE_MASK 0x00000008UL
+
+typedef struct {
+ unsigned int BaseAddress; /* Base address for device (IPIF) */
+ unsigned int NextTxBufferToUse; /* Next TX buffer to write to */
+ unsigned int NextRxBufferToUse; /* Next RX buffer to read from */
+ unsigned char DeviceId; /* Unique ID of device - for future */ +} XEmacLite;
+
+static XEmacLite EmacLite;
+
+static char etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ +
+/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ +#ifdef CFG_ENV_IS_NOWHERE
+static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
+#endif
+
+void XEmacLite_AlignedRead (u32 * SrcPtr, void *DestPtr, unsigned ByteCount)
+{
+ unsigned i;
+ unsigned Length = ByteCount;
+ u32 AlignBuffer;
+ u32 *To32Ptr;
+ u32 *From32Ptr;
+ u8 *To8Ptr;
+ u8 *From8Ptr;
+
+ From32Ptr = (u32 *) SrcPtr;
+
+ /* Word aligned buffer, no correction needed. */
+ To32Ptr = (u32 *) DestPtr;
+ while (Length > 3) {
+ *To32Ptr++ = *From32Ptr++;
+ Length -= 4;
+ }
+ To8Ptr = (u8 *) To32Ptr;
+
+ AlignBuffer = *From32Ptr++;
+ From8Ptr = (u8 *) & AlignBuffer;
+
+ for (i = 0; i < Length; i++) {
+ *To8Ptr++ = *From8Ptr++;
+ }
+}
+
+void XEmacLite_AlignedWrite (void *SrcPtr, u32 * DestPtr, unsigned ByteCount)
+{
+ unsigned i;
+ unsigned Length = ByteCount;
+ u32 AlignBuffer;
+ u32 *To32Ptr;
+ u32 *From32Ptr;
+ u8 *To8Ptr;
+ u8 *From8Ptr;
+ To32Ptr = DestPtr;
+
+ From32Ptr = (u32 *) SrcPtr;
+ while (Length > 3) {
+
+ *To32Ptr++ = *From32Ptr++;
+ Length -= 4;
+ }
+
+ AlignBuffer = 0;
+ To8Ptr = (u8 *) & AlignBuffer;
+ From8Ptr = (u8 *) From32Ptr;
+
+ for (i = 0; i < Length; i++) {
+ *To8Ptr++ = *From8Ptr++;
+ }
+
+ *To32Ptr++ = AlignBuffer;
+}
+
+void eth_halt (void)
+{
+#ifdef DEBUG
+ puts ("eth_halt\n");
+#endif
+}
+
+int eth_init (bd_t * bis)
+{
+#ifdef DEBUG
+ puts ("EmacLite Initialization Started\n");
+#endif
+ memset (&EmacLite, 0, sizeof (XEmacLite));
+ EmacLite.BaseAddress = XILINX_EMACLITE_BASEADDR;
+
+#ifdef CFG_ENV_IS_NOWHERE
+ memcpy (bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH); +#endif
+/*
+ * TX - TX_PING & TX_PONG initialization
+ */
+ /* Restart PING TX */
+ out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, 0);
+ /* Copy MAC address */
+ XEmacLite_AlignedWrite (bis->bi_enetaddr,
+ EmacLite.BaseAddress, ENET_ADDR_LENGTH);
+ /* Set the length */
+ out_be32 (EmacLite.BaseAddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+ /* Update the MAC address in the EMAC Lite */
+ out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
+ /* Wait for EMAC Lite to finish with the MAC address update */
+ while ((in_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET) &
+ XEL_TSR_PROG_MAC_ADDR) != 0) ;
+
+#ifdef XILINX_EMACLITE_TX_PING_PONG
+ /* The same operation with PONG TX */
+ out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
+ XEmacLite_AlignedWrite (bis->bi_enetaddr,
+ EmacLite.BaseAddress + XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
+ out_be32 (EmacLite.BaseAddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+ out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
+ XEL_TSR_PROG_MAC_ADDR);
+ while ((in_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET +
+ XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ;
+#endif
+
+/*
+ * RX - RX_PING & RX_PONG initialization
+ */
+ /* Write out the value to flush the RX buffer */
+ out_be32 (EmacLite.BaseAddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); +#ifdef XILINX_EMACLITE_RX_PING_PONG
+ out_be32 (EmacLite.BaseAddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
+ XEL_RSR_RECV_IE_MASK);
+#endif
+
+#ifdef DEBUG
+ puts ("EmacLite Initialization complete\n");
+#endif
+ return 0;
+}
+
+int XEmacLite_TxBufferAvailable (XEmacLite * InstancePtr)
+{
+ u32 Register;
+ u32 TxPingBusy;
+ u32 TxPongBusy;
+ /*

+  * Read the other buffer register
+  * and determine if the other buffer is available
+  */

+ Register = in_be32 (InstancePtr->BaseAddress +
+ InstancePtr->NextTxBufferToUse + 0);
+ TxPingBusy = ((Register & XEL_TSR_XMIT_BUSY_MASK) ==
+ XEL_TSR_XMIT_BUSY_MASK);
+
+ Register = in_be32 (InstancePtr->BaseAddress +
+ (InstancePtr->NextTxBufferToUse ^ XEL_TSR_OFFSET) + 0);
+ TxPongBusy = ((Register & XEL_TSR_XMIT_BUSY_MASK) ==
+ XEL_TSR_XMIT_BUSY_MASK);
+
+ return (!(TxPingBusy && TxPongBusy));
+}
+
+int eth_send (volatile void *ptr, int len) {
+
+ unsigned int Register;
+ unsigned int BaseAddress;
+
+ unsigned maxtry = 1000;
+
+ if (len > ENET_MAX_MTU)
+ len = ENET_MAX_MTU;
+
+ while (!XEmacLite_TxBufferAvailable (&EmacLite) && maxtry) {
+ udelay (10);
+ maxtry--;
+ }
+
+ if (!maxtry) {

+  printf ("Error: Timeout waiting for ethernet TX buffer\n");
+  /* Restart PING TX */
+  out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, 0);

+#ifdef XILINX_EMACLITE_TX_PING_PONG
+ out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET +
+ XEL_BUFFER_OFFSET, 0);
+#endif
+ return 0;
+ }
+
+ /* Determine the expected TX buffer address */
+ BaseAddress = (EmacLite.BaseAddress + EmacLite.NextTxBufferToUse); +
+ /* Determine if the expected buffer address is empty */
+ Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
+ if (((Register & XEL_TSR_XMIT_BUSY_MASK) == 0)
+ && ((in_be32 ((BaseAddress) + XEL_TSR_OFFSET)
+ & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
+
+#ifdef XILINX_EMACLITE_TX_PING_PONG
+ EmacLite.NextTxBufferToUse ^= XEL_BUFFER_OFFSET; +#endif
+#ifdef DEBUG
+ printf ("Send packet from 0x%x\n", BaseAddress); +#endif

+  /* Write the frame to the buffer */
+  XEmacLite_AlignedWrite (ptr, (u32 *) BaseAddress, len);
+  out_be32 (BaseAddress + XEL_TPLR_OFFSET,(len &
+   (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
+  Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
+  Register |= XEL_TSR_XMIT_BUSY_MASK;
+  if ((Register & XEL_TSR_XMIT_IE_MASK) != 0) {
+   Register |= XEL_TSR_XMIT_ACTIVE_MASK;
+  }
+  out_be32 (BaseAddress + XEL_TSR_OFFSET, Register);
+  return 1;

+ }
+#ifdef XILINX_EMACLITE_TX_PING_PONG
+ /* Switch to second buffer */
+ BaseAddress ^= XEL_BUFFER_OFFSET;
+ /* Determine if the expected buffer address is empty */
+ Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
+ if (((Register & XEL_TSR_XMIT_BUSY_MASK) == 0)
+ && ((in_be32 ((BaseAddress) + XEL_TSR_OFFSET)
+ & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
+#ifdef DEBUG
+ printf ("Send packet from 0x%x\n", BaseAddress); +#endif

+  /* Write the frame to the buffer */
+  XEmacLite_AlignedWrite (ptr, (u32 *) BaseAddress, len);
+  out_be32 (BaseAddress + XEL_TPLR_OFFSET,(len &
+   (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
+  Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
+  Register |= XEL_TSR_XMIT_BUSY_MASK;
+  if ((Register & XEL_TSR_XMIT_IE_MASK) != 0) {
+   Register |= XEL_TSR_XMIT_ACTIVE_MASK;
+  }
+  out_be32 (BaseAddress + XEL_TSR_OFFSET, Register);
+  return 1;

+ }
+#endif
+ puts ("Error while sending frame\n");
+ return 0;
+}
+
+int eth_rx (void)
+{
+ unsigned int Length;
+ unsigned int Register;
+ unsigned int BaseAddress;
+
+ BaseAddress = EmacLite.BaseAddress + EmacLite.NextRxBufferToUse;
+ Register = in_be32 (BaseAddress + XEL_RSR_OFFSET); +#ifdef DEBUG
+ printf ("Testing data at address 0x%x\n", BaseAddress); +#endif
+ if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { +#ifdef XILINX_EMACLITE_RX_PING_PONG
+ EmacLite.NextRxBufferToUse ^= XEL_BUFFER_OFFSET;
+#endif
+ } else {
+#ifndef XILINX_EMACLITE_RX_PING_PONG
+#ifdef DEBUG
+ printf ("No data was available - address 0x%x\n", BaseAddress); +#endif
+ return 0;
+#else

+  BaseAddress ^= XEL_BUFFER_OFFSET;
+  Register = in_be32 (BaseAddress + XEL_RSR_OFFSET);
+  if ((Register & XEL_RSR_RECV_DONE_MASK) !=

+ XEL_RSR_RECV_DONE_MASK) {
+#ifdef DEBUG
+ printf ("No data was available - address 0x%x\n",
+ BaseAddress);
+#endif
+ return 0;
+ }
+#endif
+ }
+ /* Get the length of the frame that arrived */
+ switch(((in_be32(BaseAddress + XEL_RXBUFF_OFFSET + 0xC)) &
+ 0xFFFF0000 ) >> 16) {
+ case 0x806:
+ Length = 42 + 20; /* FIXME size of ARP */
+#ifdef DEBUG
+ puts ("ARP Packet\n");
+#endif
+ break;
+ case 0x800:

+   Length = 14 + 14 +
+   (((in_be32(BaseAddress + XEL_RXBUFF_OFFSET + 0x10)) &
+   0xFFFF0000) >> 16); /* FIXME size of IP packet */

+#ifdef DEBUG
+ puts("IP Packet\n");
+#endif
+ break;
+ default:
+#ifdef DEBUG
+ puts("Other Packet\n");
+#endif
+ Length = ENET_MAX_MTU;
+ break;
+ }
+
+ XEmacLite_AlignedRead ((BaseAddress + XEL_RXBUFF_OFFSET),
+ etherrxbuff, Length);
+
+ /* Acknowledge the frame */
+ Register = in_be32 (BaseAddress + XEL_RSR_OFFSET);
+ Register &= ~XEL_RSR_RECV_DONE_MASK;
+ out_be32 (BaseAddress + XEL_RSR_OFFSET, Register);
+
+#ifdef DEBUG
+ printf ("Packet receive from 0x%x, length %dB\n", BaseAddress, Length); +#endif
+ NetReceive ((uchar *) etherrxbuff, Length);
+ return 1;
+
+}
+#endif

NAK.

Please clean up coding style (indentation, trailing white space, etc.). Also please use variable and function names according to coding style rules, i. e. "do not use cute names like ThisVariableIsATemporaryCounter." ... "mixed-case names are frowned upon".

Best regards,

Wolfgang Denk

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
That said, there may be good reasons for what you did beyond obsequi-
ous sycophantic parody. Perhaps you might be so kind as to elucidate.
         -- Tom Christiansen in <[email protected]>

I fix cute name from emac drivers but I think you have cute code in your code too.

You can see net/net.c file and following functions.

void NetReceive
ushort getenv_VLAN
IPaddr_t getenv_IPaddr
print_IPaddr
ushort string_to_VLAN

I think mixed-case names are really frowned.

Best regards,
Michal Simek

Not in *my* code.

You are right. I don't catch everything...

Best regards,

Wolfgang Denk

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"There are three principal ways to lose money: wine, women,  and  en-
gineers.  While  the first two are more pleasant, the third is by far
the more certain."                      -- Baron Rothschild, ca. 1800

Minor microblaze changes. Change setting for XUPV2P. Resolve problem with Barrel shifter
Repair cmd_mfsl code.

index 9ab5633..99e7047 100644
@@ -22,32 +22,17 @@
 #
 
 include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-$(shell mkdir -p $(obj)../xilinx_enet)
-endif
-
-INCS  := -I../common -I../xilinx_enet
-CFLAGS  += $(INCS)
-HOST_CFLAGS += $(INCS)
 
 LIB = $(obj)lib$(BOARD).a
 
-COBJS = $(BOARD).o \
-   ../xilinx_enet/emac_adapter.o  ../xilinx_enet/xemac.o \
-   ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
-   ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
-   ../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \
-   ../common/xbasic_types.o ../common/xdma_channel.o \
-   ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
-   ../common/xversion.o \
+COBJS = $(BOARD).o
 
 SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS := $(addprefix $(obj),$(COBJS))
 SOBJS := $(addprefix $(obj),$(SOBJS))
 
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
  rm -f $(SOBJS) $(OBJS)

index c07b0b3..eedfb24 100644
@@ -25,8 +25,8 @@
 # Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
 #
 
-TEXT_BASE = 0x38000000
+TEXT_BASE = 0x30000000
 
+PLATFORM_CPPFLAGS += -mxl-pattern-compare
 PLATFORM_CPPFLAGS += -mno-xl-soft-mul
-PLATFORM_CPPFLAGS += -mno-xl-soft-div
-PLATFORM_CPPFLAGS += -mxl-barrel-shift
+PLATFORM_CPPFLAGS += -mcpu=v5.00.c

b/board/xilinx/xupv2p/xparameters.h
index a96c693..0bb7a80 100644

@@ -28,17 +28,24 @@
 /* System Clock Frequency */
 #define XILINX_CLOCK_FREQ 100000000
 
+/* Microblaze is microblaze_0 */
+#define XILINX_USE_MSR_INSTR 1
+#define XILINX_PVR 0
+#define XILINX_FSL_NUMBER 0
+
 /* Interrupt controller is opb_intc_0 */
 #define XILINX_INTC_BASEADDR 0x41200000
-#define XILINX_INTC_NUM_INTR_INPUTS 11
+#define XILINX_INTC_NUM_INTR_INPUTS 7
 
 /* Timer pheriphery is opb_timer_1 */
 #define XILINX_TIMER_BASEADDR 0x41c00000
-#define XILINX_TIMER_IRQ 1
+#define XILINX_TIMER_IRQ 0
 
 /* Uart pheriphery is RS232_Uart_1 */
-#define XILINX_UART_BASEADDR 0x40600000
-#define XILINX_UART_BAUDRATE 115200
+#define XILINX_UARTLITE_BASEADDR 0x40600000
+#define XILINX_UARTLITE_BAUDRATE 115200
+
+/* IIC doesn't exist */
 
 /* GPIO is LEDs_4Bit*/
 #define XILINX_GPIO_BASEADDR 0x40000000

@@ -51,14 +58,10 @@
 
 /* Sysace Controller is SysACE_CompactFlash */
 #define XILINX_SYSACE_BASEADDR 0x41800000
-#define XILINX_SYSACE_HIGHADDR 0x4180ffff
 #define XILINX_SYSACE_MEM_WIDTH 16
 
 /* Ethernet controller is Ethernet_MAC */
-#define XPAR_XEMAC_NUM_INSTANCES 1
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
-#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
+#define XILINX_EMAC_BASEADDR 0x40c00000
+#define XILINX_EMAC_DMA_PRESENT 3
+#define XILINX_EMAC_HALF_DUPLEX_EXIST 1
+#define XILINX_EMAC_MII_EXIST 1

index ffa2666..337dfbb 100644
@@ -357,7 +357,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char 

*argv[])

reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
- if (argc < 1) {
+ if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
@@ -382,6 +382,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
puts ("ESR");
break;
default:
+ puts ("Unsupported register\n");
return 1;
}
printf (": 0x%08lx\n", val);
@@ -408,10 +409,10 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
" 3 - blocking control write\n");

U_BOOT_CMD (rspr, 3, 1, do_rspr,

-  "rmsr    - read/write special purpose register\n",
+  "rspr    - read/write special purpose register\n",
   "- reg_num [write value] read/write special purpose register\n"
-  " 0 - MSR - Machine status register\n"
-  " 1 - EAR - Exception address register\n"
-  " 2 - ESR - Exception status register\n");
+  " 1 - MSR - Machine status register\n"
+  " 3 - EAR - Exception address register\n"
+  " 5 - ESR - Exception status register\n");

#endif /* CONFIG_MICROBLAZE & CFG_CMD_MFSL */

index 3c027ff..8740284 100644
@@ -33,15 +33,13 @@ _start:
  addi r1, r0, CFG_INIT_SP_OFFSET
  addi r1, r1, -4 /* Decrement SP to top of memory */
  /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
- addi r6, r0, 0xb000 /* hex b000 opcode imm */
- bslli r6, r6, 16 /* shift */
+ addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
  swi r6, r0, 0x0 /* reset address */
  swi r6, r0, 0x8 /* user vector exception */
  swi r6, r0, 0x10 /* interrupt */
  swi r6, r0, 0x20 /* hardware exception */
 
- addi r6, r0, 0xb808 /* hew b808 opcode brai*/
- bslli r6, r6, 16
+ addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/
  swi r6, r0, 0x4 /* reset address */
  swi r6, r0, 0xC /* user vector exception */
  swi r6, r0, 0x14 /* interrupt */

index ab1cb12..b350453 100644
@@ -33,10 +33,17 @@ void reset_timer (void)
  timestamp = 0;
 }
 
+#ifdef CFG_TIMER_0
 ulong get_timer (ulong base)
 {
  return (timestamp - base);
 }
+#else
+ulong get_timer (ulong base)
+{
+ return (timestamp++ - base);
+}
+#endif
 
 void set_timer (ulong t)
 {

index 3db2877..8b74b7c 100644
@@ -32,6 +32,7 @@
 #define CONFIG_ML401  1 /* ML401 Board */
 
 /* uart */
+#define XILINX_UARTLITE
 #define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
 #define CONFIG_BAUDRATE  XILINX_UART_BAUDRATE
 #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }

@@ -86,7 +87,7 @@
  * 0x11FB_F000 CFG_MONITOR_BASE
  *     MONITOR_CODE 256kB Env
  * 0x13FF_F000 CFG_GBL_DATA_OFFSET
- *      GLOBAL_DATA 4kB bd, gd
+ *     GLOBAL_DATA 4kB bd, gd
  * 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
  */
 

@@ -99,7 +100,7 @@
 /* global pointer */
 #define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
 /* start of global data */
-#define CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - 

CFG_GBL_DATA_SIZE)
+#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)

/* monitor code */
#define SIZE 0x40000
@@ -242,10 +243,10 @@
#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME "ml401"
-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" +#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
#define CONFIG_IPADDR 192.168.0.3
-#define CONFIG_SERVERIP 192.168.0.5
-#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.5
+#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD

/* architecture dependent code */

index 8224555..9661726 100644
@@ -48,6 +48,7 @@
 #define CFG_MALLOC_LEN  (256 << 10) /* Reserve 256 kB for malloc */
 #define CFG_MALLOC_BASE  (CFG_MONITOR_BASE - (1024 * 1024))
 
+#define XILINX_UARTLITE
 #define CONFIG_BAUDRATE  115200
 #define CFG_BAUDRATE_TABLE { 115200 }
 

@@ -97,4 +98,6 @@
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
 
+#define XILINX_CLOCK_FREQ 50000000
+
 #endif /* __CONFIG_H */

*/
#include <cmd_confdefs.h>
@@ -150,7 +194,7 @@

#define CONFIG_BOOTDELAY 30

 #define CONFIG_BOOTARGS  "root=romfs"
-#define CONFIG_HOSTNAME  "ml401"
+#define CONFIG_HOSTNAME  "xupv2p"

#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" #define CONFIG_IPADDR 192.168.0.3
#define CONFIG_SERVERIP 192.168.0.5
@@ -166,11 +210,13 @@
"echo"

/* system ace */
+#ifdef XILINX_SYSACE_BASEADDR
#define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
#define SYSTEMACE_CONFIG_FPGA
#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR #define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH #define CONFIG_DOS_PARTITION
+#endif

#endif /* __CONFIG_H */

NAK.

...

Please clean up coding style here, too.

...

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Don't put off for tomorrow what you can  do  today,  because  if  you
enjoy it today you can do it again tomorrow.

Romfs support.

index 7fd1fa3..147ab10 100644
@@ -28,7 +28,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License

@@ -85,7 +85,7 @@
  */
 
 /*
- * JFFS2/CRAMFS support
+ * JFFS2/CRAMFS/ROMFS support
  */
 #include <common.h>
 #include <command.h>

@@ -110,7 +110,7 @@
 #define DEBUG_JFFS
 #undef DEBUG_JFFS
 
-#ifdef  DEBUG_JFFS
+#ifdef DEBUG_JFFS
 # define DEBUGF(fmt, args...) printf(fmt ,##args)
 #else
 # define DEBUGF(fmt, args...)

@@ -175,6 +175,11 @@ extern int cramfs_load (char *loadoffset, struct 

part_info *info, char *filename
extern int cramfs_ls (struct part_info *info, char *filename); extern int cramfs_info (struct part_info *info);

+extern int romfs_check (struct part_info *info);
+extern int romfs_load (char *loadoffset, struct part_info *info, char *filename);
+extern int romfs_ls (struct part_info *info, char *filename); +extern int romfs_info (struct part_info *info);
+
static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned
int part_num);

/* command line only routines */
@@ -184,10 +189,10 @@ static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_
static int device_del(struct mtd_device *dev);

/**
- * Parses a string into a number. The number stored at ptr is
+ * Parses a string into a number. The number stored at ptr is
* potentially suffixed with K (for kilobytes, or 1024 bytes),
* M (for megabytes, or 1048576 bytes), or G (for gigabytes, or
- * 1073741824). If the number is suffixed with K, M, or G, then
+ * 1073741824). If the number is suffixed with K, M, or G, then
* the return value is the number multiplied by one kilobyte, one
* megabyte, or one gigabyte, respectively.
*
@@ -676,7 +681,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i
return 1;
}

- /* allocate memory */
+ /* allocate memory */
part = (struct part_info *)malloc(sizeof(struct part_info) + name_len); if (!part) {
printf("out of memory\n");
@@ -1832,9 +1837,9 @@ static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int pa
return NULL;
}

-/***************************************************/
-/* U-boot commands */
-/***************************************************/ +/*************************************************/
+/* U-boot commands */
+/*************************************************/

/**
* Routine implementing fsload u-boot command. This routine tries to load
@@ -1874,14 +1879,22 @@ int do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

  if ((part = jffs2_part_info(current_dev, current_partnum))){

-  /* check partition type for cramfs */
-  fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2");
+  /* check partition type for JFFS2, cramfs, romfs */
+  if (cramfs_check(part)) {

+ fsname = "CRAMFS";
+ } else if (romfs_check(part)) {
+ fsname = "ROMFS";
+ } else {
+ fsname = "JFFS2";
+ }
printf("### %s loading '%s' to 0x%lx\n", fsname, filename, offset);

   if (cramfs_check(part)) {
    size = cramfs_load ((char *) offset, part, filename);

+ } else if (romfs_check(part)){
+ size = romfs_load ((char *) offset, part, filename);
} else {
- /* if this is not cramfs assume jffs2 */
+ /* if this is not cramfs or romfs assume jffs2 */

    size = jffs2_1pass_load((char *)offset, part, filename);

}

@@ -1928,8 +1941,10 @@ int do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* check partition type for cramfs */

   if (cramfs_check(part)) {
    ret = cramfs_ls (part, filename);

+ } else if (romfs_check(part)) {
+ ret = romfs_ls (part, filename);
} else {
- /* if this is not cramfs assume jffs2 */
+ /* if this is not cramfs or romfs assume jffs2 */

    ret = jffs2_1pass_ls(part, filename);

}

@@ -1951,7 +1966,6 @@ int do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
struct part_info *part;
- char *fsname;
int ret;

/* make sure we are in sync with env variables */
@@ -1961,13 +1975,17 @@ int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if ((part = jffs2_part_info(current_dev, current_partnum))){

/* check partition type for cramfs */

-  fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2");
-  printf("### filesystem type is %s\n", fsname);
+  puts("### filesystem type is ");

if (cramfs_check(part)) {

+   puts("CRAMFS\n");
    ret = cramfs_info (part);

+ } else if (romfs_check(part)) {
+ puts("ROMFS\n");
+ ret = romfs_info (part);
} else {

-   /* if this is not cramfs assume jffs2 */
+   /* if this is not cramfs or romfs assume jffs2 */
+   puts("JFFS2\n");
    ret = jffs2_1pass_info(part);

}

index 273d90e..118ae78 100644
@@ -22,7 +22,7 @@
 #
 #
 
-SUBDIRS := jffs2 cramfs fdos fat reiserfs ext2
+SUBDIRS := romfs jffs2 cramfs fdos fat reiserfs ext2
 
 $(obj).depend all:
  @for dir in $(SUBDIRS) ; do \

offset,
+ unsigned long size, int raw, char *filename)
+{
+ unsigned long inodeoffset = 0, nextoffset;
+ struct romfs_inode *inode;
+#ifdef DEBUG_ROMFS
+ printf ("ROMFS_resolve: begin 0x%x, offset 0x%x, size 0x%x, raw 0x%x, \
+ filename %s\n", begin, offset, size, raw, filename); +#endif
+
+ while (inodeoffset < size) {

+  inode = (struct romfs_inode *)(begin + offset + inodeoffset);
+  offset = 0;
+  nextoffset = ALIGN (inode->next);
+#ifdef DEBUG_ROMFS
+  printf("inode 0x%x, name %s - len 0x%x, next inode 0x%x, \
+   compare names 0x%x\n",
+   inode, inode->name, strlen (inode->name), nextoffset,
+   strncmp (filename, inode->name, strlen (filename)));

+#endif
+ if (!strncmp (filename, inode->name, strlen (inode->name))) {
+ char *p = strtok (NULL, "/");
+ if (raw && (p == NULL || *p == '\0')) {
+ return offset + inodeoffset;
+ }
+ return romfs_resolve (begin,
+ inodeoffset + HEADERSIZE (inode->name),
+ size, raw, p);
+ }
+ inodeoffset = nextoffset;
+ }
+
+ printf ("can't find corresponding entry\n");
+ return 0;
+}
+
+int romfs_load (char *loadoffset, struct part_info *info, char *filename) +{
+ struct romfs_inode *inode;
+ struct romfs_super *sb;
+ char *data;
+ int pocet;
+ sb = (struct romfs_super *) PART_OFFSET (info);
+
+ unsigned long offset;
+
+ offset = romfs_resolve (PART_OFFSET (info), HEADERSIZE (sb->name),
+ sb->size, 1, strtok (filename, "/"));
+ if (offset <= 0)
+ return offset;
+
+ inode = (struct romfs_inode *)(PART_OFFSET (info) + offset);
+ data = (char *)((int)inode + HEADERSIZE (inode->name));
+ pocet = inode->size;
+ while (pocet--) {
+ *loadoffset++ = *data++;
+ }
+ return inode->size;
+}
+
+static int romfs_list_inode (struct part_info *info, unsigned long offset) +{
+ struct romfs_inode *inode =
+ (struct romfs_inode *)(PART_OFFSET (info) + offset);
+ struct romfs_inode *hardlink = NULL;
+ char str[3], *data;
+
+/* mapping spec.info means
+ * 0 hard link link destination [file header]
+ * 1 directory first file's header
+ * 2 regular file unused, must be zero [MBZ]
+ * 3 symbolic link unused, MBZ (file data is the link content)
+ * 4 block device 16/16 bits major/minor number
+ * 5 char device - " -
+ * 6 socket unused, MBZ
+ * 7 fifo unused, MBZ
+ */
+ switch (inode->next & 0x7) {
+ case 0:
+ str[0] = 'h';
+ break;
+ case 1:
+ str[0] = 'd';
+ break;
+ case 2:
+ str[0] = 'f';
+ break;
+ case 3:
+ str[0] = 'l';
+ break;
+ case 4:
+ str[0] = 'b';
+ break;
+ case 5:
+ str[0] = 'c';
+ break;
+ case 6:
+ str[0] = 's';
+ break;
+ case 7:
+ str[0] = 'p';
+ break;
+ default:
+ str[0] = '?';
+ }
+
+ if (inode->next & 0x8) {
+ str[1] = 'x';
+ } else {
+ str[1] = '-';
+ }
+ str[2] = '\0';
+
+ if ((str[0] == 'b') || (str[0] == 'c')) {
+#ifdef DEBUG_ROMFS
+ printf (" %s %3d,%3d %12s 0x%08x 0x%08x", str,

+   (inode->spec & 0xffff0000) >> 16,
+   inode->spec & 0x0000ffff, inode->name, inode,
+   inode->spec);

+#else
+ printf (" %s %3d,%3d %12s", str,
+ (inode->spec & 0xffff0000) >> 16,
+ inode->spec & 0x0000ffff);
+#endif
+ } else {
+#ifdef DEBUG_ROMFS
+ printf (" %s %7d %12s 0x%08x 0x%08x", str, inode->size,
+ inode->name, inode, inode->spec);
+#else
+ printf (" %s %7d %12s", str, inode->size, inode->name); +#endif
+ if (str[0] == 'l') {

+   data = (char *)((int)inode + HEADERSIZE (inode->name));
+   puts (" -> ");
+   puts (data);

+ }
+ if (str[0] == 'h') {
+ hardlink = (struct romfs_inode *)(PART_OFFSET (info) +
+ inode->spec);
+ puts (" -> ");
+ puts (hardlink->name);
+ }
+ }
+ puts ("\n");
+ return ALIGN (inode->next);
+}
+
+int romfs_ls (struct part_info *info, char *filename) +{
+ struct romfs_inode *inode;
+ unsigned long inodeoffset = 0, nextoffset;
+ unsigned long offset, size;
+ struct romfs_super *sb;
+ sb = (struct romfs_super *)PART_OFFSET (info); +
+ if (strlen (filename) == 0 || !strcmp (filename, "/")) {
+ offset = HEADERSIZE (sb->name);
+ size = sb->size;
+ } else {
+ offset = romfs_resolve (PART_OFFSET (info),
+ HEADERSIZE (sb->name), sb->size, 1,
+ strtok (filename, "/"));
+
+ if (offset == 0) {
+ return offset;

+  }
+  inode = (struct romfs_inode *)(PART_OFFSET (info) + offset);
+  if ((inode->next & 0x7) != 1) {

+ return (romfs_list_inode (info, offset) > 0);
+ }
+
+ size = sb->size;
+ offset = offset + HEADERSIZE (inode->name);
+ }
+
+ inodeoffset = offset + inodeoffset;
+ while (inodeoffset < size) {
+ nextoffset = romfs_list_inode (info, inodeoffset);
+ if (nextoffset == 0)
+ break;
+ inodeoffset = nextoffset;
+ }
+ return 1;
+}
+
+int romfs_info (struct part_info *info)
+{
+ struct romfs_super *sb;
+ sb = (struct romfs_super *)PART_OFFSET (info);
+
+ printf ("name: \t\t%s, len %d B\n", sb->name, strlen (sb->name));
+ printf ("size of SB:\t%d B\n", HEADERSIZE (sb->name));
+ printf ("full size:\t%d B\n", sb->size);
+ printf ("checksum:\t0x%x\n", sb->checksum);
+ return 0;
+}
+
+int romfs_check (struct part_info *info)
+{
+ struct romfs_super *sb;
+ if (info->dev->id->type != MTD_DEV_TYPE_NOR)
+ return 0;
+
+ sb = (struct romfs_super *)PART_OFFSET (info);
+ if ((sb->word0 != 0x2D726F6D) || (sb->word1 != 0x3166732D)) {
+ return 0;
+ }
+ return 1;
+}
+
+#endif

Seems your patch has been corrupted by your mailer (line wrap). Please fix that.

Please do not implement such "improvements". The original code was better, so please undo your "optimizations".

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"There's always been Tower of Babel sort of  bickering  inside  Unix,
but  this  is the most extreme form ever. This means at least several
years of confusion." - Bill Gates, founder and chairman of Microsoft,
about the Open Systems Foundation

Why do we need such complexity in U-Boot? U-Boot is a boot loader...

Best regards,

Wolfgang Denk

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Compassion -- that's the one things no machine ever had.  Maybe it's
the one thing that keeps men ahead of them.
	-- McCoy, "The Ultimate Computer", stardate 4731.3

The EMAC is a funny thing. If the FPGA design includes EMAC DMA, then programmed IO no longer works.

g.

Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely at secretlab.ca
(403) 399-0195

And SG ?

Best regards,

Wolfgang Denk

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If you want strict real-time behavior, run in the real  time  schedu-
ling class.  But there are no seatbelts or airbags;  main(){for(;;);}
can hard hang your system.                          -- Bart Smaalders

Yup, I believe so

g.

Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely at secretlab.ca
(403) 399-0195

I will test it.

Michal Simek

u-boot-testing is just a step intomainlain. And pull requests normally always get pulled into mainline.

So the same rules always apply.

And what about the other changes?

And what about the missing signed-off-by lines?

Because that and Grant's other comments I think it would be a bad idea to pull from the microblaze tree as it. I suggest you roll back and re-add the stuff (with signed-off-by) after review on the mailing list.

Best regards,

Wolfgang Denk

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The rule on staying alive as a program manager is to give 'em a  num-
ber or give 'em a date, but never give 'em both at once.