Hello
From: Stephen C. Tweedie <[email protected]>
Quoted 3 lines
NT's VLM support only gives you access to the high memory if you use a special API. We plan on supporting clean access to all of physical memory quite transparently for Linux, without any such restrictions.
Do you plan that for 2.2 or 2.3?
Do you think that this will be backported to 2.2?
If not, then I'll write a quick and dirty shm modification which supports more memory, and I'll disable swapping for that memory.
A note about VLM:
* VLM is a Microsoft invention for Windows NT on Alpha:
the user mode program is 64 bit, the kernel mostly 32 bit. Pointers are sign extended by the processor.
A special kernel extension allows user mode processes to map up to 28 GB memory into the middle of the memory space. The rest of the OS knows nothing about this memory.
Quoted 6 lines
From the MSDN Library:
VLM is supported only on processors that directly support native 64-bit addressing. At present, these include the Compaq DIGITAL AlphaServer processors and specifically exclude the Intel 80286, 80386, 80486, Pentium, and Pentium II processors.
* I read something on the Intel website about a kernel extension which Intel wrote for the Pentium Processor.
If Linux supports more than 2 GB memory on 32 Bit processor, then the implementation will be similar to that.
Do you have any details about PSE-36?
This seems to be a page table extention for the Xeon CPU's AFAIK, this is not identical to PAE (available since PPro).
And: AFAIK, there are no chipsets which support > 4 GB memory for PPro's, so there is no need to support PAE if PSE-36 is easier to implement.
Regards,
Manfred
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Hi,
Quoted 1 line · Manfred Spraul
Do you have any details about PSE-36?
Yes, the PDF docsets on Intel's developer pages cover it pretty well.
Quoted 2 lines
This seems to be a page table extention for the Xeon CPU's AFAIK, this is not identical to PAE (available since PPro).
There are two separate extensions. Since PPro, the CPUs have supported large page tables. Currently these can address 36 bits of physical memory, but given that you have to deal with it in 4MB or 2MB chunks, it is much less convenient than normal addressing and cannot easily be used to support transparently the existing kernel behaviour.
The newer addressing mode is the 3-level page tables available in PIIIs (and in later stepping PIIs, I think), which allow transparent access to all of physical memory up to 64G. That's what I'm aiming for.
--Stephen
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