AT572D940HF-EB Support v2 (board folder)

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+/*
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
+	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};

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+/*
+ * (C) Copyright 2008 Atmel Corporation
+ * 
+ * Antonio R. Costa <antonio.costa  <at> atmel.com>
+ *                  <costa.antonior <at> gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_MMC
+
+#include <part.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/byteorder.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/memory-map.h>
+#include <asm/arch/timer.h>
+#include <fat.h>
+
+#include <asm/arch/atmel_mci.h>
+
+#ifdef DEBUG
+#define pr_debug(fmt, args...) printf(fmt, ##args)
+#else
+#define pr_debug(...) do { } while(0)
+#endif
+
+#ifndef CFG_MMC_CLK_OD
+#define CFG_MMC_CLK_OD		150000
+#endif
+
+#ifndef CFG_MMC_CLK_PP
+#define CFG_MMC_CLK_PP		5000000
+#endif
+
+#ifndef CFG_MMC_OP_COND
+#define CFG_MMC_OP_COND		0x401f8000
+#endif
+
+#define MMC_DEFAULT_BLKLEN	512
+#define MMC_DEFAULT_RCA		1
+
+static unsigned int mmc_rca;
+static int mmc_card_is_sd;
+static block_dev_desc_t mmc_blkdev;
+
+block_dev_desc_t *mmc_get_dev(int dev)
+{
+	return &mmc_blkdev;
+}
+
+static int mci_reset(void)
+{
+
+	mmci_writel(CR, MMCI_BIT(SWRST));
+	mmci_writel(CR, MMCI_BIT(MCIEN));
+	mmci_writel(CR, MMCI_BIT(PWSDIS));
+
+	mmci_writel(CMDR, (1 << 11) | (1 << 8));	/* Init command */
+	while (!(mmci_readl(SR) & MMCI_BIT(CMDRDY))) ;
+	return 0;
+}
+
+static void mci_set_mode(unsigned long hz, unsigned long blklen)
+{
+	unsigned long bus_hz;
+	unsigned long clkdiv;
+
+	bus_hz = get_mci_clk_rate();
+	clkdiv = (bus_hz / hz) / 2 - 1;
+
+	pr_debug("mmc: setting clock %lu Hz, clkdiv %lu, block size %lu\n",
+		 hz, clkdiv, blklen);
+
+	if (clkdiv & ~255UL) {
+		clkdiv = 255;
+		printf("mmc: clock %lu too low; setting CLKDIV to 255\n",
+				hz);
+	}
+
+	blklen &= 0xfffc;
+	mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv)
+			 | MMCI_BF(BLKLEN, blklen)
+			 | MMCI_BIT(RDPROOF)
+			 | MMCI_BIT(WRPROOF)));
+}
+
+#define RESP_NO_CRC	1
+#define R1		MMCI_BF(RSPTYP, 1)	/* 48-bit CRC */
+#define R2		MMCI_BF(RSPTYP, 2)	/* 136-bit CRC*/
+#define R3		(R1 | RESP_NO_CRC)
+#define R6		R1
+#define R7		R1
+#define NID		MMCI_BF(MAXLAT, 0)
+#define NCR		MMCI_BF(MAXLAT, 1)
+#define TRCMD_START	MMCI_BF(TRCMD, 1)
+#define TRDIR_READ	MMCI_BF(TRDIR, 1)
+#define TRTYP_BLOCK	MMCI_BF(TRTYP, 0)
+#define INIT_CMD	MMCI_BF(SPCMD, 1)
+#define OPEN_DRAIN	MMCI_BF(OPDCMD, 1)
+
+#define ERROR_FLAGS	(MMCI_BIT(DTOE)			\
+			 | MMCI_BIT(RDIRE)		\
+			 | MMCI_BIT(RENDE)		\
+			 | MMCI_BIT(RINDE)		\
+			 | MMCI_BIT(RTOE))
+
+static int
+mmc_cmd(unsigned long cmd, unsigned long arg, void *resp,
+		unsigned long flags)
+{
+	unsigned long *response = resp;
+	int i, response_words = 0;
+	unsigned long error_flags;
+	u32 status;
+
+	pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n", cmd, arg, flags);
+
+	error_flags = ERROR_FLAGS;
+	if (!(flags & RESP_NO_CRC))
+		error_flags |= MMCI_BIT(RCRCE);
+
+	flags &= ~MMCI_BF(CMDNB, ~0UL);
+
+	if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_48_BIT_RESP)
+		response_words = 1;
+	else if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_136_BIT_RESP)
+		response_words = 4;
+
+	mmci_writel(ARGR, arg);
+	mmci_writel(CMDR, cmd | flags);
+	do {
+		udelay(40);
+		status = mmci_readl(SR);
+	} while (!(status & MMCI_BIT(CMDRDY)));
+
+	pr_debug("mmc: status 0x%08lx\n", status);
+
+	if (status & ERROR_FLAGS) {
+		printf("mmc: command %lu failed (status: 0x%08lx)\n",
+		       cmd, status);
+		return -EIO;
+	}
+
+	if (response_words)
+		pr_debug("mmc: response:");
+
+	for (i = 0; i < response_words; i++) {
+		response[i] = mmci_readl(RSPR);
+		pr_debug(" %08lx", response[i]);
+	}
+	pr_debug("\n");
+
+	return 0;
+}
+
+static int mmc_acmd(unsigned long cmd, unsigned long arg,  void *resp,
+		unsigned long flags) __attribute ((noinline));
+
+static int mmc_acmd(unsigned long cmd, unsigned long arg,
+		    void *resp, unsigned long flags)
+{
+	unsigned long aresp[4];
+	int ret;
+
+	/*
+	 * Seems like the APP_CMD part of an ACMD has 64 cycles max
+	 * latency even though the ACMD part doesn't. This isn't
+	 * entirely clear in the SD Card spec, but some cards refuse
+	 * to work if we attempt to use 5 cycles max latency here...
+	 */
+
+	pr_debug("acmd: flags 0x%lx \n", flags);
+	ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp,
+		      R1 | NCR | (flags & OPEN_DRAIN));
+	if (ret)
+		return ret;
+	if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD)
+		return -EIO;
+
+	ret = mmc_cmd(cmd, arg, resp, flags);
+
+	return ret;
+}
+
+static unsigned long
+mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
+		unsigned long *buffer)
+{
+	int ret, start_inc = 0, i = 0;
+	unsigned long resp[4];
+	unsigned long card_status;
+	unsigned long wordcount;
+	u32 status;
+
+	if (blkcnt == 0)
+		return 0;
+
+	/*
+	 * ARC: 
+	 * For SDHC cards start is the number of the first block to read;
+	 * for regular SD cards start is the address of the first byte to
+	 * read
+	 */
+	start = (mmc_blkdev.if_type == IF_TYPE_SDHC) ? start : start * 512;
+	start_inc = (mmc_blkdev.if_type == IF_TYPE_SDHC) ? 1 : 512;
+
+	pr_debug("mmc_bread: dev %d, type %u, start %lx," \
+		 " blkcnt %lx buffer: 0x%p\n",dev, 
+		 mmc_blkdev.if_type, start, blkcnt, buffer);
+
+	/* Put the device into Transfer state */
+	ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
+
+	if (ret)
+		goto out;
+
+	/* 
+	 * ARC: set the bus width to 4-bits 
+	 * 0x1 1-bit, 0x2 4-bits
+	 */
+	if ((mmc_blkdev.if_type == IF_TYPE_SD)
+	    || (mmc_blkdev.if_type == IF_TYPE_SDHC)) {
+		unsigned long resp[4];
+		ret = mmc_cmd(MMC_CMD_APP_CMD, mmc_rca << 16,
+				resp, R1 | NCR);
+		if (ret)
+			return ret;
+		if ((resp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != 
+				R1_APP_CMD)
+			return -ENODEV;
+
+		ret = mmc_cmd(MMC_ACMD_BUS_WIDTH, 0x2, resp, R1 | NCR);
+	}
+
+	/* Set block length */
+	/*
+	 * ARC: useless but not dungerous for SDHC 
+	 */
+	ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp,
+			R1 | NCR);
+	if (ret)
+		goto out;
+
+	/*
+	 * ARC: wait for card in ready state
+	 */
+	do {
+		ret = mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, resp,
+				R1 | NCR);
+	} while ((ret != 0) && (resp[0] & (1 << 8)));
+
+	for (i = 0; i < blkcnt; i++, start += start_inc) {
+		/*
+		 * ARC: enables and configure PDC
+		 */
+		pr_debug("bread: buffer address: 0x%p\n", buffer);
+		ret = mmci_readl(MR);
+		mmci_writel(MR, (ret | MMCI_BIT(PDCMODE)));
+		mmci_writel(PTCR, (MMCI_PTCR_TXTDIS | MMCI_PTCR_RXTDIS));
+		mmci_writel(RPR, (u32) buffer);
+		mmci_writel(RCR, mmc_blkdev.blksz / 4);
+		mmci_writel(PTCR, MMCI_PTCR_RXTEN);
+
+		ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK,
+			      start, resp,
+			      (R1 | NCR | TRCMD_START | TRDIR_READ |
+			       TRTYP_BLOCK));
+		if (ret)
+			goto read_error;
+
+		do {
+			status = mmci_readl(SR);
+		} while (!(status & MMCI_BIT(RXBUFF))
+			 && !(status & ERROR_FLAGS));
+		/*
+		 * ARC: disable PDC
+		 */
+
+		ret = mmci_readl(MR);
+		mmci_writel(MR, (ret & ~MMCI_BIT(PDCMODE)));
+
+		if (status & ERROR_FLAGS) {
+			ret = mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16,
+					resp, R1 | NCR);
+			printf("Error reading from card: 0x%08x," \
+				" status: 0x%08x\n", mmc_rca, resp[0]);
+			goto read_error;
+		}
+
+		wordcount = (mmc_blkdev.blksz / 4) - mmci_readl(RCR);
+		buffer += wordcount;
+		mmci_writel(PTCR, (MMCI_PTCR_TXTDIS | MMCI_PTCR_RXTDIS));
+
+		pr_debug("mmc: read %u words, waiting for BLKE\n",
+				wordcount);
+
+		while (!(status & MMCI_BIT(BLKE)))
+			status = mmci_readl(SR);
+	}
+
+      out:
+	/* Put the device back into Standby state */
+	mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
+	return i;
+
+      read_error:
+	mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
+	printf("mmc: bread failed, rca = 0x%08x, status = 0x%08x," \
+		" card status = 0x%08x\n", mmc_rca, status, card_status);
+	goto out;
+}
+
+static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp)
+{
+	cid->mid = resp[0] >> 24;
+	cid->oid = (resp[0] >> 8) & 0xffff;
+	cid->pnm[0] = resp[0];
+	cid->pnm[1] = resp[1] >> 24;
+	cid->pnm[2] = resp[1] >> 16;
+	cid->pnm[3] = resp[1] >> 8;
+	cid->pnm[4] = resp[1];
+	cid->pnm[5] = resp[2] >> 24;
+	cid->pnm[6] = 0;
+	cid->prv = resp[2] >> 16;
+	cid->psn = (resp[2] << 16) | (resp[3] >> 16);
+	cid->mdt = resp[3] >> 8;
+}
+
+static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp)
+{
+	cid->mid = resp[0] >> 24;
+	cid->oid = (resp[0] >> 8) & 0xffff;
+	cid->pnm[0] = resp[0];
+	cid->pnm[1] = resp[1] >> 24;
+	cid->pnm[2] = resp[1] >> 16;
+	cid->pnm[3] = resp[1] >> 8;
+	cid->pnm[4] = resp[1];
+	cid->pnm[5] = 0;
+	cid->pnm[6] = 0;
+	cid->prv = resp[2] >> 24;
+	cid->psn = (resp[2] << 8) | (resp[3] >> 24);
+	cid->mdt = (resp[3] >> 8) & 0x0fff;
+}
+
+static void mmc_dump_cid(const struct mmc_cid *cid)
+{
+	puts("----- CID -----\n");
+	printf("Manufacturer ID:       %02lX\n", cid->mid);
+	printf("OEM/Application ID:    %04lX\n", cid->oid);
+	printf("Product name:          %s\n", cid->pnm);
+	printf("Product Revision:      %lu.%lu\n",
+	       cid->prv >> 4, cid->prv & 0x0f);
+	printf("Product Serial Number: %lu\n", cid->psn);
+	printf("Manufacturing Date:    %02lu/%02lu\n",
+	       cid->mdt >> 4, cid->mdt & 0x0f);
+	puts("----- CID -----\n");
+}
+
+static void mmc_dump_csd(const mmc_csd_t pcsd)
+{
+	printf("CSD data: %08lx %08lx %08lx %08lx\n",
+	       pcsd[0], pcsd[1], pcsd[2], pcsd[3]);
+	printf("CSD structure version:   %u\n",
+			1 + SD_CSD_FIELD(VER, pcsd));
+	printf("TAAC: %u\n", SD_CSD_FIELD(TAAC, pcsd));
+	printf("NSAC: %u\n", SD_CSD_FIELD(NSAC, pcsd));
+	printf("Card command classes:    %03x\n",
+			SD_CSD_FIELD(CCC, pcsd));
+	printf("Read block length:       %u\n",
+			1 << SD_CSD_FIELD(RBLEN, pcsd));
+	if (SD_CSD_FIELD(RBP, pcsd))
+		puts("Supports partial reads\n");
+	else
+		puts("Does not support partial reads\n");
+	printf("Write block length:      %u\n",
+			1 << SD_CSD_FIELD(WBL, pcsd));
+	if (SD_CSD_FIELD(WBP, pcsd))
+		puts("Supports partial writes\n");
+	else
+		puts("Does not support partial writes\n");
+	if (SD_CSD_FIELD(WPGE, pcsd))
+		printf("Supports group WP:      %u\n",
+		       SD_CSD_FIELD(WPGS, pcsd) + 1);
+	else
+		puts("Does not support group WP\n");
+
+	/*
+	 * ARC: capacity is computed dependig on CSD version:
+	 * SD cards capacity depends on read_block_len parameter
+	 * and a multiplier, SDHC cadrs capacity depend on the #
+	 * of blocks insted, block length is fixed to 512K
+	 */
+	printf("Card capacity:		%llu MB\n",
+	       (unsigned long long)
+	       ((SD_CSD_VER(pcsd) == 0) ?
+		(SD_CSD_1x_CSIZE(pcsd) + 1) *
+		((1 << (SD_CSD_1x_FIELD(CSMUL, pcsd) + 2)) *
+		(1 << SD_CSD_1x_FIELD(RBLEN, pcsd))) :
+		((unsigned long long)
+		(SD_CSD_2x_CSIZE(pcsd) + 1ULL) * 512ULL * 1024ULL))
+	       / 1048576);
+
+	printf("File format:            %u/%u\n",
+	       SD_CSD_FIELD(FFG, pcsd), SD_CSD_FIELD(FF, pcsd));
+	puts("Write protection:        ");
+	if (SD_CSD_FIELD(PWP, pcsd))
+		puts(" permanent");
+	if (SD_CSD_FIELD(TWP, pcsd))
+		puts(" temporary");
+	putc('\n');
+}
+
+static int mmc_idle_cards(void)
+{
+	int ret;
+
+	/* Reset and initialize all cards */
+	/* Send CMD0 */
+	ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
+	if (ret)
+		return ret;
+
+	/* Keep the bus idle for 74 clock cycles */
+	return mmc_cmd(0, 0, NULL, INIT_CMD);
+}
+
+static int sd_init_card(struct mmc_cid *cid, block_dev_desc_t * mmc_blkdev_p,
+			int verbose) __attribute__((noinline));
+
+static int sd_init_card(struct mmc_cid *cid, block_dev_desc_t * mmc_blkdev_p,
+			int verbose)
+{
+	unsigned long resp[4];
+	int i, ret = 0;
+	u32 status;
+
+	mci_reset();
+	mmc_idle_cards();
+	if(verbose)
+		puts("mmc: Probing for SDHC ...\n");
+	/* Send supported voltage range */
+	/* SD cards 1.x do not answer to CMD8 */
+	ret = mmc_cmd(MMC_CMD_IF_COND, ((1 << 8) | 0xAA), resp, R7 | NCR);
+	if (ret == -EIO) {
+		/* 
+		 * ARC: No answer let's try SD 1.x 
+		 */
+		if(verbose)
+			puts("mmc: No answer to CMD8 trying SD\n");
+		mmc_blkdev_p->if_type = IF_TYPE_SD;
+	} else if (ret) {
+		/* Other errors or most probably 2.0 voltage mismatch */
+		puts("mmc: Unknown error on CMD8\n");
+		mmc_blkdev_p->if_type = IF_TYPE_UNKNOWN;
+		return -ENODEV;
+	} else {
+		/*
+		 * ARC: probably an SDHC card
+		 */
+		mmc_blkdev_p->if_type = IF_TYPE_SDHC;
+		if(verbose)
+			puts("mmc: SD 2.0 or later card found\n");
+
+		/* Check if the card supports this voltage */
+		if (resp[0] != ((1 << 8) | 0xAA)) {
+			pr_debug("mmc: Invalid voltage range\n");
+			return -ENODEV;
+		}
+	}
+
+	/* 
+	 * ARC: HC (30) bit set according to response to 
+	 * CMD8 command
+	 */
+
+	pr_debug("mmc: Sending ACMD41 %s HC set\n",
+		 ((mmc_blkdev_p->if_type ==
+		   IF_TYPE_SDHC) ? "with" : "without"));
+
+	for (i = 1; i <= SD_MAX_RETRIES; i++) {
+		pr_debug("ACMD41 arg: 0x%08x \n",
+			 CFG_MMC_OP_COND &
+			 ((mmc_blkdev_p->if_type ==
+			   IF_TYPE_SDHC) ? 0xffffffff : 0xbfffffff));
+		{
+			/*
+			 * ARC: Some cards need this delay 
+			 * during voltage negotiation otherwise
+			 * they report an error between two ACMD41 probes
+			 * More investigation needed.
+			 */
+			int volatile i =100000;
+			while(i-->0);
+		}
+
+		ret =
+		    mmc_acmd(MMC_ACMD_SD_SEND_OP_COND,
+			     CFG_MMC_OP_COND &
+			     ((mmc_blkdev_p->if_type ==
+			      IF_TYPE_SDHC) ? 0xffffffff : 0xbfffffff), resp,
+			     R3 | NCR);
+		/*
+		 * ARC: if no answer try again
+		 */
+		if (ret == -EIO) {
+			if(verbose)
+				printf("Retrying (%d/%d) ... \n",
+						i, SD_MAX_RETRIES);
+			continue;
+		}
+		if (ret || (resp[0] & 0x80000000))
+			break;
+		ret = -ETIMEDOUT;
+	}
+
+	/*
+	 * ARC: Card did not answer to ACMD41
+	 * so it's a MMC card
+	 */
+	if (ret) {
+		mmc_blkdev.if_type = IF_TYPE_MMC;
+		puts("No answer to ACMD41 trying mmc card\n");
+		return ret;
+	}
+
+	/*
+	 * ARC: check for HC bit, if its not set
+	 * sd card is SD
+	 */
+	if ((resp[0] & 0xc0000000) == 0x80000000) {
+		mmc_blkdev.if_type = IF_TYPE_SD;
+	}
+
+	ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID);
+	if (ret)
+		return ret;
+	sd_parse_cid(cid, resp);
+	if (verbose)
+		mmc_dump_cid(cid);
+
+	/* Get RCA of the card that responded */
+	ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR);
+	if (ret)
+		return ret;
+
+	mmc_rca = resp[0] >> 16;
+	if (verbose)
+		printf("SD Card detected RCA: 0x%x type: %s\n",
+		       mmc_rca,
+		       ((mmc_blkdev.if_type ==
+			 IF_TYPE_SDHC) ? "SDHC" : ((mmc_blkdev.if_type ==
+						    IF_TYPE_SD) ? "SD" :
+						   "MMC")));
+
+	mmc_card_is_sd = 1;
+	return 0;
+}
+
+static int mmc_init_card(struct mmc_cid *cid, int verbose)
+{
+	unsigned long resp[4];
+	int i, ret = 0;
+
+	mmc_idle_cards();
+	for (i = 0; i < 1000; i++) {
+		ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp,
+			      R3 | NID | OPEN_DRAIN);
+		if (ret || (resp[0] & 0x80000000))
+			break;
+		ret = -ETIMEDOUT;
+	}
+
+	if (ret)
+		return ret;
+
+	/* Get CID of all cards. FIXME: Support more than one card */
+	ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN);
+	if (ret)
+		return ret;
+	mmc_parse_cid(cid, resp);
+	if (verbose)
+		mmc_dump_cid(cid);
+
+	/* Set Relative Address of the card that responded */
+	ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp,
+		      R1 | NCR | OPEN_DRAIN);
+	return ret;
+}
+
+static void mci_set_data_timeout(mmc_csd_t * pu_csd)
+{
+	static const unsigned int dtomul_to_shift[] = {
+		0, 4, 7, 8, 10, 12, 16, 20,
+	};
+	static const unsigned int taac_exp[] = {
+		1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
+	};
+	static const unsigned int taac_mant[] = {
+		0, 10, 12, 13, 15, 60, 25, 30,
+		35, 40, 45, 50, 55, 60, 70, 80,
+	};
+	unsigned int timeout_ns, timeout_clks;
+	unsigned int e, m;
+	unsigned int dtocyc, dtomul;
+	unsigned int shift;
+	u32 dtor;
+
+	unsigned long sys_freq = 0;
+
+	sys_get_freq(AT91_MASTER_FREQ, &sys_freq);
+	pr_debug("mmc: sys_frequency: %lu\n", sys_freq);
+
+	if ((mmc_blkdev.if_type == IF_TYPE_SD) ||
+	    (mmc_blkdev.if_type == IF_TYPE_SDHC)) {
+		/* SDHC cards maximum timeout is 100ms
+		 * 100ms = dtocyc * mci_cycle_period s =>
+		 * 0.1s = dtocyc * (sys_freq/(2*(clkdiv+1)))^-1 s =>
+		 * dtocyc = 0.1*(sys_freq/(2*(clkdiv+1))) =>
+		 * dtocyc = sys_freq/(20*(clkdiv+1))
+		 */
+		unsigned long clkdiv = mmci_readl(MR);
+
+		clkdiv = MMCI_BF(CLKDIV, clkdiv);
+		timeout_clks = sys_freq / (20 * (clkdiv + 1));
+		pr_debug("mmc: timeout cycles %lu\n", timeout_clks);
+	} else {
+		e = MMC_CSD_FIELD(TAAC, pu_csd) & 0x07;
+		m = (MMC_CSD_FIELD(TAAC, pu_csd) >> 3) & 0x0f;
+
+		timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10;
+		timeout_clks = MMC_CSD_FIELD(NSAC, pu_csd) * 100;
+
+		timeout_clks += (((timeout_ns + 9) / 10)
+				 * ((CFG_MMC_CLK_PP + 99999) / 100000) +
+				 9999) / 10000;
+		if (!mmc_card_is_sd)
+			timeout_clks *= 10;
+		else
+			timeout_clks *= 100;
+	}
+
+	dtocyc = timeout_clks;
+
+	dtomul = 0;
+	while (dtocyc > 15 && dtomul < 8) {
+		dtomul++;
+		shift = dtomul_to_shift[dtomul];
+		dtocyc = (timeout_clks + (1 << shift) - 1) >> shift;
+	}
+
+	if (dtomul >= 8) {
+		dtomul = 7;
+		dtocyc = 15;
+		puts("Warning: Using maximum data timeout\n");
+	}
+
+	dtor = (MMCI_BF(DTOMUL, dtomul)
+		| MMCI_BF(DTOCYC, dtocyc + 1));
+	mmci_writel(DTOR, dtor);
+
+	pr_debug("mmc: Using %u cycles data timeout (DTOR=0x%x)\n",
+		 dtocyc << shift, dtor);
+}
+
+int mmc_init(int verbose)
+{
+	struct mmc_cid cid;
+	mmc_csd_t u_csd;
+	unsigned int max_blksz;
+	int ret;
+
+	/* Initialize controller */
+	mmci_writel(CR, MMCI_BIT(SWRST));
+	mmci_writel(CR, MMCI_BIT(MCIEN));
+	mmci_writel(DTOR, 0x5f);
+	mmci_writel(IDR, ~0UL);
+	mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+
+	mmc_card_is_sd = 0;
+	mmc_blkdev.if_type = IF_TYPE_UNKNOWN;
+
+	ret = sd_init_card(&cid, &mmc_blkdev, verbose);
+
+	/* No SD card so try MMC */
+	if (ret) {
+		mmc_rca = MMC_DEFAULT_RCA;
+		ret = mmc_init_card(&cid, verbose);
+	}
+	/* No MMC card so abort */
+	if (ret)
+		return ret;
+
+	/* Get CSD from the card */
+	ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &u_csd, R2 | NCR);
+	if (ret)
+		return ret;
+	if (verbose)
+		mmc_dump_csd((void *)&u_csd);
+
+	/*
+	 * ARC: If the card type is not MMC then
+	 * check for SD CSD version:
+	 * 0  => SD
+	 * !0 => SDHC
+	 */
+	/*
+	   if(mmc_blkdev.if_type != IF_TYPE_MMC)
+	   if(SD_CSD_FIELD(VER,&u_csd) == 0)
+	   mmc_blkdev.if_type = IF_TYPE_SD;
+	   else
+	   mmc_blkdev.if_type = IF_TYPE_SDHC;
+	 */
+
+	mci_set_data_timeout(&u_csd);
+
+	/* Initialize the blockdev structure */
+	if (mmc_blkdev.if_type == IF_TYPE_UNKNOWN)
+		mmc_blkdev.if_type = IF_TYPE_MMC;
+
+	mmc_blkdev.part_type = PART_TYPE_DOS;
+	mmc_blkdev.block_read = mmc_bread;
+	sprintf((char *)mmc_blkdev.vendor,
+		"Man %02x%04x Snr %08x", cid.mid, cid.oid, cid.psn);
+	strncpy((char *)mmc_blkdev.product, cid.pnm,
+		sizeof(mmc_blkdev.product));
+	sprintf((char *)mmc_blkdev.revision, "%x %x",
+		cid.prv >> 4, cid.prv & 0x0f);
+
+	/*
+	 * If we can't use 512 byte blocks, refuse to deal with the
+	 * card. Tons of code elsewhere seems to depend on this.
+	 */
+	max_blksz = 1 << MMC_CSD_FIELD(RBLEN, &u_csd);
+	if ((mmc_blkdev.if_type == IF_TYPE_MMC) &
+	    ((max_blksz < 512)
+	     || ((max_blksz > 512) && !MMC_CSD_FIELD(RBP, &u_csd)))
+	    ) {
+		printf("Card does not support 512 byte reads, aborting.\n");
+		return -ENODEV;
+	}
+	mmc_blkdev.blksz = 512;
+	if (MMC_CSD_VER(&u_csd) == 0)
+		/* CSD ver 1.x */
+		mmc_blkdev.lba =
+		    (MMC_CSD_FIELD(CSIZE, &u_csd) +
+		     1) * (1 << (MMC_CSD_FIELD(CSMUL, &u_csd) + 2));
+	else
+		/* CSD ver 2.0 */
+		mmc_blkdev.lba =
+		    (SD_CSD_FIELD(CSIZE, &u_csd) + 1) * (512 * 1024);
+
+	mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz);
+
+	init_part(&mmc_blkdev);
+	if (fat_register_device(&mmc_blkdev, 1))
+		printf("Could not register MMC fat device\n");
+	if(verbose)
+		print_part_dos(&mmc_blkdev);
+	return 0;
+}
+
+int mmc_read(ulong src, uchar * dst, int size)
+{
+	return -ENOSYS;
+}
+
+int mmc_write(uchar * src, ulong dst, int size)
+{
+	return -ENOSYS;
+}
+
+int mmc2info(ulong addr)
+{
+	return 0;
+}
+
+#endif /* CONFIG_MMC */

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index b22a637..1bf4a24 100644
@@ -62,6 +62,7 @@ typedef struct block_dev_desc {
 #define IF_TYPE_MMC		6
 #define IF_TYPE_SD		7
 #define IF_TYPE_SATA		8
+#define IF_TYPE_SDHC		9
 
 /* Part types */
 #define PART_TYPE_UNKNOWN	0x00

new file mode 100644
index 0000000..ba0da8c
@@ -0,0 +1,44 @@
+/*
+ * include/asm-arm/arch-at572d940/at91_aic.h
+ *
+ * Copyright (C) 2008 Antonio R. Costa
+ * Copyright (C) ATMEL
+ *
+ * Advanced Interrupt Controller (AIC).
+ * Based on AT572D940 datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#define AIC_BASE 	0xfffff000
+
+#define AIC_SMR0	0x0
+#define AIC_SVR0	0x80
+#define AIC_IVR		0x100
+#define AIC_FIQ		0x104
+#define AIC_ISR		0x108
+#define AIC_IPR		0x10c
+#define AIC_IMR		0x110
+#define AIC_ICR		0x114
+#define AIC_IECR	0x120
+#define AIC_IDCR	0x124
+#define AIC_ICCR	0x128
+#define AIC_ISCR	0x12c
+#define AIC_EOICR	0x130
+#define AIC_SPU		0x134
+
+#define AIC_SMR(n)	\
+	((unsigned long) (((unsigned long*) AIC_SMR0) + (n)))
+#define AIC_SVR(n)	\
+	((unsigned long) (((unsigned long*) AIC_SVR0) + (n)))
+
+#define AIC_WRITE(reg,value) \
+	(*((volatile unsigned long*) (AIC_BASE + (reg))) = value)
+#define AIC_READ(reg,value)  \
+	(value = *((volatile unsigned long*) (AIC_BASE + (reg))))
+
+#define AIC_REG(reg)	\
+	(*((volatile unsigned long*) (AIC_BASE + (reg))))

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new file mode 100644
index 0000000..b854ff9
@@ -0,0 +1,29 @@
+/*
+ * include/asm-arm/arch-at91/at91_pit.h
+ *
+ * Periodic Interval Timer (PIT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIT_H
+#define AT91_PIT_H
+
+#define AT91_PIT_MR		(AT91_PIT + 0x00)	/* Mode Register */
+#define		AT91_PIT_PITIEN		(1 << 25)	/* Timer Interrupt Enable */
+#define		AT91_PIT_PITEN		(1 << 24)	/* Timer Enabled */
+#define		AT91_PIT_PIV		(0xfffff)	/* Periodic Interval Value */
+
+#define AT91_PIT_SR		(AT91_PIT + 0x04)	/* Status Register */
+#define		AT91_PIT_PITS		(1 << 0)	/* Timer Status */
+
+#define AT91_PIT_PIVR		(AT91_PIT + 0x08)	/* Periodic Interval Value Register */
+#define AT91_PIT_PIIR		(AT91_PIT + 0x0c)	/* Periodic Interval Image Register */
+#define		AT91_PIT_PICNT		(0xfff << 20)	/* Interval Counter */
+#define		AT91_PIT_CPIV		(0xfffff)	/* Inverval Value */
+
+#endif

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new file mode 100644
index 0000000..aae10c0
@@ -0,0 +1,38 @@
+/*
+ * include/asm-arm/arch-at91/at91_rstc.h
+ *
+ * Reset Controller (RSTC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RSTC_H
+#define AT91_RSTC_H
+
+#define AT91_RSTC_CR		(AT91_RSTC + 0x00)	/* Reset Controller Control Register */
+#define	AT91_RSTC_PROCRST	(1 << 0)	/* Processor Reset */
+#define	AT91_RSTC_PERRST	(1 << 2)	/* Peripheral Reset */
+#define	AT91_RSTC_EXTRST	(1 << 3)	/* External Reset */
+#define	AT91_RSTC_KEY		(0xa5 << 24)	/* KEY Password */
+
+#define AT91_RSTC_SR			(AT91_RSTC + 0x04)	/* Reset Controller Status Register */
+#define	AT91_RSTC_URSTS			(1 << 0)	/* User Reset Status */
+#define	AT91_RSTC_RSTTYP		(7 << 8)	/* Reset Type */
+#define	AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
+#define	AT91_RSTC_RSTTYP_WAKEUP		(1 << 8)
+#define	AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
+#define	AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
+#define	AT91_RSTC_RSTTYP_USER		(4 << 8)
+#define	AT91_RSTC_NRSTL			(1 << 16)	/* NRST Pin Level */
+#define	AT91_RSTC_SRCMP			(1 << 17)	/* Software Reset Command in Progress */
+
+#define AT91_RSTC_MR		(AT91_RSTC + 0x08)	/* Reset Controller Mode Register */
+#define	AT91_RSTC_URSTEN	(1 << 0)	/* User Reset Enable */
+#define	AT91_RSTC_URSTIEN	(1 << 4)	/* User Reset Interrupt Enable */
+#define	AT91_RSTC_ERSTL		(0xf << 8)	/* External Reset Length */
+
+#endif

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new file mode 100644
index 0000000..f649b41
@@ -0,0 +1,36 @@
+/*
+ * include/asm-arm/arch-at91/hardware.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *  Copyright (C) 2003 ATMEL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+#if defined(CONFIG_AT572D940HF)
+#include <asm/arch/at572d940hf.h>
+#else
+#error "Unsupported AT572D940HF processor"
+#endif
+
+/*
+ * container_of - cast a member of a structure out to the containing structure
+ *
+ * @ptr:	the pointer to the member.
+ * @type:	the type of the container struct this is embedded in.
+ * @member:	the name of the member within the struct.
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof(((type *)0)->member) *__mptr = (ptr);	\
+	(type *)((char *)__mptr - offsetof(type, member)); })
+
+#endif

new file mode 100644
index 0000000..be9e9ab
@@ -0,0 +1,40 @@
+/*
+ * include/asm-arm/arch-at91/io.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include <asm/io.h>
+
+static inline unsigned int at91_sys_read(unsigned int reg_offset)
+{
+	void *addr = (void *)AT91_BASE_SYS;
+
+	return __raw_readl(addr + reg_offset);
+}
+
+static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
+{
+	void *addr = (void *)AT91_BASE_SYS;
+
+	__raw_writel(value, addr + reg_offset);
+}
+
+#endif

new file mode 100644
index 0000000..a590d59
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_ARCH_MEMORYMAP_H__
+#define __ASM_ARM_ARCH_MEMORYMAP_H__
+
+#include <asm/arch/hardware.h>
+
+#define USART0_BASE AT91_USART0
+#define USART1_BASE AT91_USART1
+#define USART2_BASE AT91_USART2
+#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU)
+
+#define AT572D940_SDRAM_BASE 0x20000000
+
+#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */

new file mode 100644
index 0000000..53f049b
@@ -0,0 +1,147 @@
+/*
+ * include/asm-arm/arch-at91/AT572D940HFhf.h
+ *
+ * (C) 2008 Antonio R. Costa
+ *
+ * Common definitions.
+ * Based on AT572D940HFHF datasheet rev A.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT572D940HFHF_H
+#define AT572D940HFHF_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ		0  /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS		1  /* System Peripherals */
+#define AT572D940HF_ID_PIOA	2  /* Parallel IO Controller A */
+#define AT572D940HF_ID_PIOB	3  /* Parallel IO Controller B */
+#define AT572D940HF_ID_PIOC	4  /* Parallel IO Controller C */
+#define AT572D940HF_ID_EMAC	5  /* Ethernet */
+#define AT572D940HF_ID_US0	6  /* USART 0 */
+#define AT572D940HF_ID_US1	7  /* USART 1 */
+#define AT572D940HF_ID_US2	8  /* USART 2 */
+#define AT572D940HF_ID_MCI	9  /* Multimedia Card Interface */
+#define AT572D940HF_ID_UDP	10 /* USB Device Port */
+#define AT572D940HF_ID_TWI	11 /* Two-Wire Interface */
+#define AT572D940HF_ID_TWI0	11 /* Two-Wire Interface */
+#define AT572D940HF_ID_SPI0	12 /* Serial Peripheral Interface 0 */
+#define AT572D940HF_ID_SPI1	13 /* Serial Peripheral Interface 1 */
+#define AT572D940HF_ID_SSC	14 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC0	14 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC1	15 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC2	16 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_TC0	17 /* Timer Counter 0 */
+#define AT572D940HF_ID_TC1	18 /* Timer Counter 1 */
+#define AT572D940HF_ID_TC2	19 /* Timer Counter 2 */
+#define AT572D940HF_ID_UHP	20 /* USB Host port */
+#define AT572D940HF_ID_SSC3	21 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_TWI1	22 /* Two-Wire Interface */
+#define AT572D940HF_ID_CAN0	23 /* CAN Controller */
+#define AT572D940HF_ID_CAN1	24 /* CAN Controller */
+#define AT572D940HF_ID_mHALT	25 /* mAgicV DSP halt int */
+#define AT572D940HF_ID_mSIRQ1	26 /* mAgicV DSP SIRQ1 int */
+#define AT572D940HF_ID_mEXC	27 /* mAgicV DSP Exception int */
+#define AT572D940HF_ID_mEDMA	28 /* mAgicV DSP end of DMA transfer int */
+#define AT572D940HF_ID_IRQ0	29 /* Advanced Interrupt Controller (IRQ0) */
+#define AT572D940HF_ID_IRQ1	30 /* Advanced Interrupt Controller (IRQ1) */
+#define AT572D940HF_ID_IRQ2	31 /* Advanced Interrupt Controller (IRQ2) */
+
+#define AT91_ID_US0 		AT572D940HF_ID_US0
+#define AT91_ID_US1 		AT572D940HF_ID_US1
+#define AT91_ID_US2 		AT572D940HF_ID_US2
+#define AT91_ID_US3 		AT572D940HF_ID_US3
+
+#define AT91_ID_UHP	AT572D940HF_ID_UHP
+#define AT91_PMC_UHP	AT572D940HF_ID_UHP
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT572D940HF_BASE_TCB0		0xfffa0000
+#define AT572D940HF_BASE_TC0		0xfffa0000
+#define AT572D940HF_BASE_TC1		0xfffa0040
+#define AT572D940HF_BASE_TC2		0xfffa0080
+#define AT572D940HF_BASE_UDP		0xfffa4000
+#define AT572D940HF_BASE_MCI		0xfffa8000
+#define AT572D940HF_BASE_TWI		0xfffac000
+#define AT572D940HF_BASE_US0		0xfffb0000
+#define AT572D940HF_BASE_US1		0xfffb4000
+#define AT572D940HF_BASE_US2		0xfffb8000
+#define AT572D940HF_BASE_SSC		0xfffbc000
+#define AT572D940HF_BASE_ISI		0xfffc0000
+#define AT572D940HF_BASE_EMAC		0xfffd8000
+#define AT572D940HF_BASE_SPI0		0xfffc8000
+#define AT572D940HF_BASE_SPI1		0xfffcc000
+#define AT572D940HF_BASE_US3		0xfffd0000
+#define AT572D940HF_BASE_US4		0xfffd4000
+#define AT572D940HF_BASE_US5		0xfffd8000
+#define AT572D940HF_BASE_TCB1		0xfffdc000
+#define AT572D940HF_BASE_TC3		0xfffdc000
+#define AT572D940HF_BASE_TC4		0xfffdc040
+#define AT572D940HF_BASE_TC5		0xfffdc080
+#define AT572D940HF_BASE_ADC		0xfffe0000
+#define AT572D940HF_BASE_RSTC		0xfffffd00
+#define AT91_BASE_SYS			0xffffea00
+
+#define AT91_BASE_EMAC	AT572D940HF_BASE_EMAC
+#define AT91_BASE_SPI	AT572D940HF_BASE_SPI0
+#define MMCI_BASE	AT572D940HF_BASE_MCI
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC	(0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC	(0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC	(0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG	(0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA	(0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB	(0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC	(0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR	(0xfffffd50 - AT91_BASE_SYS)
+
+#define AT91_USART0	AT572D940HF_BASE_US0
+#define AT91_USART1	AT572D940HF_BASE_US1
+#define AT91_USART2	AT572D940HF_BASE_US2
+#define AT91_USART3	AT572D940HF_BASE_US3
+#define AT91_USART4	AT572D940HF_BASE_US4
+#define AT91_USART5	AT572D940HF_BASE_US5
+
+/*
+ * Internal Memory.
+ */
+#define AT572D940HF_ROM_BASE	0x00400000 /* Internal ROM base address    */
+#define AT572D940HF_ROM_SIZE	SZ_32K     /* Internal ROM size (32Kb)     */
+
+#define AT572D940HF_SRAM0_BASE	0x00100000 /* Internal SRAM 0 base address */
+#define AT572D940HF_SRAM0_SIZE	SZ_16K	   /* Internal SRAM 0 size (4Kb)   */
+#define AT572D940HF_SRAM1_BASE	0x00200000 /* Internal SRAM 0 base address */
+#define AT572D940HF_SRAM1_SIZE	SZ_16K	   /* Internal SRAM 0 size (4Kb)   */
+#define AT572D940HF_SRAM2_BASE	0x00300000 /* Internal SRAM 1 base address */
+#define AT572D940HF_SRAM2_SIZE	SZ_16K	   /* Internal SRAM 1 size (4Kb)   */
+
+//SDRAM
+#define AT572D940HF_SDRAM_BASE	0x20000000
+
+// USB Host
+#define AT572D940HF_UHP_BASE	0x00500000 /* USB Host controller          */
+
+#define AT91SAM9XE_FLASH_BASE	0x00200000 /* Internal FLASH base address  */
+#define AT91SAM9XE_SRAM_BASE	0x00300000 /* Internal SRAM base address   */
+
+#endif

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new file mode 100644
index 0000000..8878d06
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Author: Antonio R. Costa
+ */
+
+#ifndef _AT91_TIMER_H_
+#define _AT91_TIMER_H_
+
+#define AT91_SLOW_FREQ    0
+#define AT91_MAIN_FREQ    1
+#define AT91_PLLA_FREQ    2
+#define AT91_PLLB_FREQ    3
+#define AT91_MASTER_FREQ  4
+#define AT91_SYS_FREQ     4
+#define AT91_PROC_FREQ    5
+
+extern int sys_get_freq(unsigned long mode, unsigned long *pfreq);
+
+#endif /* _AT91_TIMER_H_ */

index e5733f6..eb446d1 100644
@@ -417,15 +417,15 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 
 	/* choose RMII or MII mode. This depends on the board */
 #ifdef CONFIG_RMII
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
-    defined(CONFIG_AT91SAM9263)
+#if defined(CONFIG_AT91CAP9)    || defined(CONFIG_AT91SAM9260) || \
+    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT572D940HFEB)
 	macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
 #else
 	macb_writel(macb, USRIO, 0);
 #endif
 #else
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
-    defined(CONFIG_AT91SAM9263)
+#if defined(CONFIG_AT91CAP9)    || defined(CONFIG_AT91SAM9260) || \
+    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT572D940HFEB)
 	macb_writel(macb, USRIO, MACB_BIT(CLKEN));
 #else
 	macb_writel(macb, USRIO, MACB_BIT(MII));

index 21d1496..e782731 100644
@@ -65,6 +65,7 @@ extern int atngw100_eth_initialize(bd_t *);
 extern int mcffec_initialize(bd_t*);
 extern int mcdmafec_initialize(bd_t*);
 extern int at91sam9_eth_initialize(bd_t *);
+extern int at572d940hf_eth_initialize(bd_t *);
 
 #ifdef CONFIG_API
 extern void (*push_packet)(volatile void *, int);

@@ -292,6 +293,9 @@ int eth_initialize(bd_t *bis)
     defined(CONFIG_AT91SAM9263)
 	at91sam9_eth_initialize(bis);
 #endif
+#if defined(CONFIG_AT572D940HF)
+	at572d940hf_eth_initialize(bis);
+#endif
 
 	if (!eth_devices) {
 		puts ("No ethernet found.\n");

index 3fc9975..4c995ea 100644
@@ -126,6 +126,7 @@
 #define CFG_NR_PIOS			5
 #define CFG_HSDRAMC			1
 #define CONFIG_MMC			1
+#define CONFIG_ATMEL_MCI		1
 
 #define CFG_DCACHE_LINESZ		32
 #define CFG_ICACHE_LINESZ		32

index ba18eb6..90910bb 100644
@@ -153,6 +153,7 @@
 #define CFG_NR_PIOS			5
 #define CFG_HSDRAMC			1
 #define CONFIG_MMC			1
+#define CONFIG_ATMEL_MCI		1
 
 #define CFG_DCACHE_LINESZ		32
 #define CFG_ICACHE_LINESZ		32

index a528ddf..03472a8 100644
@@ -136,6 +136,7 @@
 #define CONFIG_PIO2			1
 #define CFG_HSDRAMC			1
 #define CONFIG_MMC			1
+#define CONFIG_ATMEL_MCI		1
 
 #define CFG_DCACHE_LINESZ		32
 #define CFG_ICACHE_LINESZ		32

index fc9585e..07add82 100644
@@ -136,6 +136,7 @@
 #define CONFIG_PIO2			1
 #define CFG_HSDRAMC			1
 #define CONFIG_MMC			1
+#define CONFIG_ATMEL_MCI		1
 
 #define CFG_DCACHE_LINESZ		32
 #define CFG_ICACHE_LINESZ		32

index 9fd49a5..f9af675 100644
@@ -153,6 +153,7 @@
 #define CFG_NR_PIOS			5
 #define CFG_HSDRAMC			1
 #define CONFIG_MMC			1
+#define CONFIG_ATMEL_MCI		1
 
 #define CFG_DCACHE_LINESZ		32
 #define CFG_ICACHE_LINESZ		32

similarity index 100%
rename from cpu/at32ap/atmel_mci.c
rename to drivers/mmc/atmel_mci.c

similarity index 100%
rename from cpu/at32ap/atmel_mci.h
rename to drivers/mmc/atmel_mci.h