x86: Document irq router device tree bindings

PATCH New Bin Meng 3 participants 8 messages May 20, 2015 2 messages not in the archive x86

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Bin Meng

author

2015-05-20 07:55 UTC #1 lore raw

PATCH 2/4 x86: Document irq router device tree bindings

Describe all required properties needed by the irq router device tree.

Signed-off-by Bin Meng <[email protected]>

---

 doc/device-tree-bindings/misc/intel,irq-router.txt | 50 ++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 doc/device-tree-bindings/misc/intel,irq-router.txt

doc/device-tree-bindings/misc/intel,irq-router.txt new file +50 -0

new file mode 100644
index 0000000..54112f4
@@ -0,0 +1,50 @@
+Intel Interrupt Router Device Binding
+=====================================
+
+The device tree node which describes the operation of the Intel Interrupt Router
+device is as follows:
+
+Required properties :
+- reg : Specifies the interrupt router's PCI configuration space address as
+    defined by the Open Firmware spec.
+- compatible = "intel,irq-router"
+- intel,pirq-config : Specifies the IRQ routing register programming mechanism.
+    Valid values are:
+      "pci": IRQ routing is controlled by PCI configuraiton registers
+      "ibase": IRQ routing is in the memory-mapped IBASE register block
+- intel,ibase-offset : IBASE register offset in the interrupt router's PCI
+    configuration space, required only if intel,pirq-config = "ibase".
+- intel,pirq-link : Specifies the PIRQ link information with two cells. The
+    first cell is the register offset that controls the first PIRQ link routing.
+    The second cell is the total number of PIRQ links the router supports.
+- intel,pirq-mask : Specifies the IRQ mask reprenting the 16 IRQs in 8259 PIC.
+    Bit N is 1 means IRQ N is available to be routed.
+- intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
+   encoded as 3 cells a group for a device. The first cell is the device's PCI
+   bus number, device number and function number encoding with PCI_BDF() macro.
+   The second cell is the PCI interrupt pin used by this device. The last cell
+   is which PIRQ line the PCI interrupt pin is routed to.
+
+
+Example
+-------
+
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+	irq-router at 1f,0 {
+		reg = <0x0000f800 0 0 0 0>;
+		compatible = "intel,irq-router";
+		intel,pirq-config = "pci";
+		intel,pirq-link = <0x60 8>;
+		intel,pirq-mask = <0xdef8>;
+		intel,pirq-routing = <
+			PCI_BDF(0, 2, 0) INTA PIRQA
+			PCI_BDF(0, 3, 0) INTA PIRQB
+			PCI_BDF(0, 8, 0) INTA PIRQC
+			PCI_BDF(0, 8, 1) INTB PIRQD
+			PCI_BDF(1, 6, 0) INTA PIRQE
+			PCI_BDF(1, 6, 1) INTB PIRQF
+			PCI_BDF(1, 6, 2) INTC PIRQG
+			PCI_BDF(1, 6, 3) INTD PIRQH
+		>;
+	};

Signature · 1 line

1.8.2.1

Andy Pont

2015-05-20 08:06 UTC #2 lore raw

PATCH 2/4 x86: Document irq router device tree bindings

Hi Bin,

Quoted 1 line

+ "pci": IRQ routing is controlled by PCI configuraiton registers

^^^

One small typo to correct.

Andy.

A message that is not in the archive (sent off-list or not yet received): [email protected]

Bin Meng

author

2015-05-20 09:06 UTC #4 lore raw

PATCH 2/4 x86: Document irq router device tree bindings

Hi Andy,

Quoted 7 lines · Andy Pont

Hi Bin,
Quoted 1 line
+ "pci": IRQ routing is controlled by PCI configuraiton registers
                                                         ^^^
One small typo to correct.

Thanks for pointing it out. I found myself easy to spell wrong 'configuration' :(

Quoted 2 lines

Andy.

Regards,
Bin

Simon Glass

2015-05-20 17:45 UTC #5 lore raw

PATCH 2/4 x86: Document irq router device tree bindings

Quoted 11 lines · Bin Meng

Hi Andy,
Quoted 7 lines · Andy Pont
Hi Bin,
Quoted 1 line
+ "pci": IRQ routing is controlled by PCI configuraiton registers
                                                         ^^^
One small typo to correct.

Quoted 8 lines

Thanks for pointing it out. I found myself easy to spell wrong 'configuration' :(
Quoted 2 lines
Andy.
Regards,
Bin

Acked-by Simon Glass <[email protected]>

Bin Meng

author

2015-05-20 07:55 UTC #6 lore raw

PATCH 3/4 x86: quark: Implement PIRQ routing

In reply to a message not in the archive

Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely.

Signed-off-by Bin Meng <[email protected]>

---

 arch/x86/cpu/quark/quark.c               | 31 ++++++++++++++
 arch/x86/dts/galileo.dts                 | 22 ++++++++++
 arch/x86/include/asm/arch-quark/device.h | 70 +++++++++++++++++++++++++-------
 arch/x86/include/asm/arch-quark/quark.h  | 15 +++++++
 configs/galileo_defconfig                |  1 +
 include/configs/galileo.h                |  1 +
 6 files changed, 125 insertions(+), 15 deletions(-)

arch/x86/cpu/quark/quark.c +31 -0

index e78a271..20cc09e 100644
@@ -9,6 +9,7 @@
 #include <netdev.h>
 #include <phy.h>
 #include <asm/io.h>
+#include <asm/irq.h>
 #include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/processor.h>

@@ -147,3 +148,33 @@ int cpu_eth_init(bd_t *bis)
 	else
 		return 0;
 }
+
+void cpu_irq_init(void)
+{
+	struct quark_rcba *rcba;
+	u32 base;
+
+	base = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, LB_RCBA);
+	base &= ~MEM_BAR_EN;
+	rcba = (struct quark_rcba *)base;
+
+	/*
+	 * Route Quark PCI device interrupt pin to PIRQ
+	 *
+	 * Route device#23's INTA/B/C/D to PIRQA/B/C/D
+	 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
+	 */
+	writew(PIRQC, &rcba->rmu_ir);
+	writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
+	       &rcba->d23_ir);
+	writew(PIRQD, &rcba->core_ir);
+	writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
+	       &rcba->d20d21_ir);
+}
+
+int arch_misc_init(void)
+{
+	pirq_init();
+
+	return 0;
+}

arch/x86/dts/galileo.dts +22 -0

index 60dbc5f..2ba081e 100644
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <dt-bindings/mrc/quark.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
 
 /include/ "skeleton.dtsi"

@@ -67,6 +68,27 @@
 			clock-frequency = <44236800>;
 			current-speed = <115200>;
 		};
+
+		irq-router at 1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,irq-router";
+			intel,pirq-config = "pci";
+			intel,pirq-link = <0x60 8>;
+			intel,pirq-mask = <0xdef8>;
+			intel,pirq-routing = <
+				PCI_BDF(0, 20, 0) INTA PIRQE
+				PCI_BDF(0, 20, 1) INTB PIRQF
+				PCI_BDF(0, 20, 2) INTC PIRQG
+				PCI_BDF(0, 20, 3) INTD PIRQH
+				PCI_BDF(0, 20, 4) INTA PIRQE
+				PCI_BDF(0, 20, 5) INTB PIRQF
+				PCI_BDF(0, 20, 6) INTC PIRQG
+				PCI_BDF(0, 20, 7) INTD PIRQH
+				PCI_BDF(0, 21, 0) INTA PIRQE
+				PCI_BDF(0, 21, 1) INTB PIRQF
+				PCI_BDF(0, 21, 2) INTC PIRQG
+			>;
+		};
 	};
 
 	gpioa {

arch/x86/include/asm/arch-quark/device.h +55 ~~-15~~

75 lines not on this page · raw message

arch/x86/include/asm/arch-quark/quark.h +15 -0

index 6dd02fd..c997928 100644
@@ -76,4 +76,19 @@
 #define LB_BC			0xd8
 #define LB_RCBA			0xf0
 
+#ifndef __ASSEMBLY__
+
+/* Root Complex Register Block */
+struct quark_rcba {
+	u32	rctl;
+	u32	esd;
+	u32	rsvd1[3150];
+	u16	rmu_ir;
+	u16	d23_ir;
+	u16	core_ir;
+	u16	d20d21_ir;
+};
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* _QUARK_H_ */

configs/galileo_defconfig +1 -0

index 1a54ba5..7273acc 100644
@@ -7,3 +7,4 @@ CONFIG_DEFAULT_DEVICE_TREE="galileo"
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_NETDEVICES=y
 CONFIG_NET=y
+CONFIG_GENERATE_PIRQ_TABLE=y

include/configs/galileo.h +1 -0

index 083d8b4..fd89bf3 100644
@@ -15,6 +15,7 @@
 
 #define CONFIG_SYS_MONITOR_LEN		(1 << 20)
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_MISC_INIT
 
 #define CONFIG_X86_SERIAL

Signature · 1 line

1.8.2.1

Simon Glass

2015-05-20 22:20 UTC #7 lore raw

PATCH 3/4 x86: quark: Implement PIRQ routing

Quoted 9 lines · Bin Meng

Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by Bin Meng <[email protected]>
---

Quoted 7 lines

 arch/x86/cpu/quark/quark.c               | 31 ++++++++++++++
 arch/x86/dts/galileo.dts                 | 22 ++++++++++
 arch/x86/include/asm/arch-quark/device.h | 70 +++++++++++++++++++++++++-------
 arch/x86/include/asm/arch-quark/quark.h  | 15 +++++++
 configs/galileo_defconfig                |  1 +
 include/configs/galileo.h                |  1 +
 6 files changed, 125 insertions(+), 15 deletions(-)

Acked-by Simon Glass <[email protected]>

Bin Meng

author

2015-05-20 07:55 UTC #8 lore raw

PATCH 4/4 x86: Do sanity test on pirq table before writing

In reply to a message not in the archive

If pirq_routing_table points to NULL, that means U-Boot fails to generate the table before in create_pirq_routing_table(), so we test it against NULL before actually writing it.

Signed-off-by Bin Meng <[email protected]>

---

 arch/x86/cpu/irq.c | 3 +++
 1 file changed, 3 insertions(+)

arch/x86/cpu/irq.c +3 -0

index 32dc6f2..ce6334b 100644
@@ -217,5 +217,8 @@ void pirq_init(void)
 
 u32 write_pirq_routing_table(u32 addr)
 {
+	if (!pirq_routing_table)
+		return addr;
+
 	return copy_pirq_routing_table(addr, pirq_routing_table);
 }

Signature · 1 line

1.8.2.1

Simon Glass

2015-05-20 22:20 UTC #9 lore raw

PATCH 4/4 x86: Do sanity test on pirq table before writing

Quoted 9 lines · Bin Meng

If pirq_routing_table points to NULL, that means U-Boot fails to generate the table before in create_pirq_routing_table(), so we test it against NULL before actually writing it.
Signed-off-by Bin Meng <[email protected]>
---
 arch/x86/cpu/irq.c | 3 +++
 1 file changed, 3 insertions(+)

Acked-by Simon Glass <[email protected]>

Quoted 17 lines

arch/x86/cpu/irq.c +3 -1

index 32dc6f2..ce6334b 100644
@@ -217,5 +217,8 @@ void pirq_init(void)
 
 u32 write_pirq_routing_table(u32 addr)
 {
+       if (!pirq_routing_table)
+               return addr;
+
        return copy_pirq_routing_table(addr, pirq_routing_table);
 }
--

1.8.2.1