SystemACE

Hi,
I have debugged systemace driver and ported it on Microblaze. I use SystemACE for loading bitstream to FPGA. But if the SystemACE initializes FPGA this part of code sets to zero CFGDONE bit in STATUSREG. And then release_cf_lock function resets SystemACE.
I add this part of code to microblaze-git repository. Please test it if you can.

Best regards,
Michal Simek

+/*
+ * For FPGA configuration via SystemACE is reset unacceptable
+ * CFGDONE bit in STATUSREG is not set to 1.
+ */

+#ifndef SYSTEMACE_CONFIG_FPGA

                /* Reset the configruation controller */
                val = ace_readw(0x18);
                val |= 0x0080;
                ace_writew(val, 0x18);

+#endif

                retry = trans * 16;
                while (retry > 0) {

Cool, thanks Michal. I'll try it on my ml403 ppc design in the next couple of days and provide feedback. I've also got a handful of systemace patches pending in my tree, so I'll try to get those cleaned up and out for you to take a look at.

Cheers,
g.

Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely at secretlab.ca
(403) 399-0195