support for mainstone development board

Attached are files to add support for the Mainstone development board (PXA270 CPU). This work was based on the Lubbock module.

CHANGELOG:
* Add support for the Mainstone development board
Patch by Frank Agius, 26 Oct 2005

________________________________________
Frank?Agius
SAMSys Technologies, Inc.

Index: MAKEALL
===================================================================
RCS file: /cvsroot/u-boot/u-boot/MAKEALL,v
retrieving revision 1.128

diff -p -u -r1.128 MAKEALL
@@ -202,8 +202,8 @@ LIST_ARM11="	\
 
 LIST_pxa="	\
 	adsvix		cerf250		cradle		csb226		\
-	innokom		lubbock		pxa255_idp	wepep250	\
-	xaeniax		xm250		xsengine			\
+	innokom		lubbock		mainstone	pxa255_idp	\
+	wepep250	xaeniax		xm250		xsengine	\
 "
 
 LIST_ixp="ixdp425"

Index: Makefile
===================================================================
RCS file: /cvsroot/u-boot/u-boot/Makefile,v
retrieving revision 1.212

diff -p -u -r1.212 Makefile
@@ -1601,6 +1601,9 @@ lubbock_config	:	unconfig
 logodl_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa logodl
 
+mainstone_config:	unconfig
+	@./mkconfig $(@:_config=) arm pxa mainstone 
+
 pxa255_idp_config:	unconfig
 	@./mkconfig $(@:_config=) arm pxa pxa255_idp
 

Index: README
===================================================================
RCS file: /cvsroot/u-boot/u-boot/README,v
retrieving revision 1.138

diff -p -u -r1.138 README
@@ -308,9 +308,9 @@ The following options need to be configu
 		CONFIG_H2_OMAP1610,	CONFIG_HHP_CRADLE,

CONFIG_IMPA7,
CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
CONFIG_KB9202,
CONFIG_LART, CONFIG_LPD7A400,
CONFIG_LUBBOCK,
- CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4,
CONFIG_SHANNON,
- CONFIG_P2_OMAP730, CONFIG_SMDK2400,
CONFIG_SMDK2410,
- CONFIG_TRAB, CONFIG_VCMA9
+ CONFIG_MAINSTONE, CONFIG_OSK_OMAP5912,
CONFIG_OMAP2420H4,
+ CONFIG_SHANNON, CONFIG_P2_OMAP730,
CONFIG_SMDK2400,
+ CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9

MicroBlaze based boards:
------------------------
Index: drivers/smc91111.c
===================================================================
RCS file: /cvsroot/u-boot/u-boot/drivers/smc91111.c,v retrieving revision 1.19

upper code will abort if not set */
return (-1); /* upper code ignores this, but NOT
bi_enetaddr */
}
+#ifdef CONFIG_SMC_PXA270
+ /* writes must be on a 32 bit boundary. write first 4 bytes of mac
addr,
+ * then the last 2 bytes.
+ */
+ addr0_3 = smc_mac_addr[3]<<24 | smc_mac_addr[2]<<16 |
smc_mac_addr[1] <<8 | smc_mac_addr[0];
+ /* write first 4 bytes. write address should be on a 32 bit boundary
*/
+ SMC_outl (addr0_3, ADDR0_REG);
+ addr4_5 = smc_mac_addr[5]<<8 | smc_mac_addr[4];
+ PRINTK2("writing smc_mac_addr=0x%06x%x\n",addr0_3,addr4_5);
+ /* write last 2 bytes. write address should be on a 32 bit boundary
*/
+ SMC_outw (addr4_5, ADDR0_REG+4);
+#else
#ifdef USE_32_BIT
for (i = 0; i < 6; i += 2) {
word address;
@@ -840,7 +886,7 @@ static int smc_open (bd_t * bd)
for (i = 0; i < 6; i++)
SMC_outb (smc_mac_addr[i], (ADDR0_REG + i));
#endif
-
+#endif /* end CONFIG_SMC_PXA270 */
return 0;
}

@@ -882,7 +928,12 @@ static int smc_rcv()

PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
/* start reading from the start of the packet */
+#ifndef CONFIG_SMC_PXA270
SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
+#else
+ SMC_outl ((PTR_READ | PTR_RCV |
+ PTR_AUTOINC)<<16, 4);
+#endif

/* First two words are status and packet_length */
#ifdef USE_32_BIT
@@ -952,7 +1003,7 @@ static int smc_rcv()
udelay(1); /* Wait until not busy */

/* restore saved registers */
-#ifndef CONFIG_XAENIAX
+#ifndef SMC_WRITE_32
SMC_outb( saved_pnr, PN_REG );
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
@@ -1381,7 +1432,11 @@ static void smc_phy_configure ()

/* Configure the Receive/Phy Control register */ SMC_SELECT_BANK (0);
+#ifdef CONFIG_SMC_PXA270
+ SMC_outl (RPC_DEFAULT<<16, RPC_REG-2);
+#else
SMC_outw (RPC_DEFAULT, RPC_REG);
+#endif

/* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
@@ -1459,7 +1514,11 @@ static void smc_phy_configure ()
}

/* Re-Configure the Receive/Phy Control register */
+#ifdef CONFIG_SMC_PXA270
+ SMC_outl (RPC_DEFAULT<<16, RPC_REG-2);
+#else
SMC_outw (RPC_DEFAULT, RPC_REG);
+#endif

smc_phy_configure_exit: ;

Index: drivers/smc91111.h
===================================================================
RCS file: /cvsroot/u-boot/u-boot/drivers/smc91111.h,v retrieving revision 1.11

diff -p -u -r1.11 smc91111.h
@@ -74,7 +74,12 @@ typedef unsigned long int 		dword;
 
 #define	SMC_IO_EXTENT	16
 
-#ifdef CONFIG_PXA250
+/* XANEIAX and other boards can only do 32-bit writes */
+#if defined (CONFIG_XAENIX) ||  defined (CONFIG_SMC_PXA270)
+#define SMC_WRITE_32
+#endif
+
+#if defined (CONFIG_PXA250) ||  defined (CONFIG_PXA27X)
 
 #ifdef CONFIG_XSENGINE
 #define	SMC_inl(r) 	(*((volatile dword

*)(SMC_BASE_ADDRESS+(r<<1))))
@@ -176,7 +181,7 @@ typedef unsigned long int dword;
}; \
})

-#else /* if not CONFIG_PXA250 */
+#else /* if not (CONFIG_PXA250 || CONFIG_PXA27X) */

#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ /*
@@ -678,8 +683,11 @@ enum {

--------------------------------------------------------------------------*/

/* select a register bank, 0 to 3 */
-
+#ifdef CONFIG_SMC_PXA270
+#define SMC_SELECT_BANK(x) { SMC_outl( (x)<<16, 12 ); } +#else
#define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); }
+#endif

/* this enables an interrupt in the interrupt mask register */ #define SMC_ENABLE_INT(x) {\

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