mach:omap: some correction in Clock 34XX

This patch modifies the I2C clock nodes as per LDM, corrects usage of DPLL mask and updates the flags of 96M clock nodes

Signed-off-by Chandra Shekhar <[email protected]>

---
arch/arm/mach-omap2/clock34xx.c | 4 +---
arch/arm/mach-omap2/clock34xx.h | 27 ++++++++++++++++++---------

2 files changed, 19 insertions(+), 12 deletions(-)

Index: linux-omap-git/arch/arm/mach-omap2/clock34xx.c
===================================================================

arch/arm/mach-omap2/clock34xx.c +1 -3

@@ -37,8 +37,6 @@
 #include "cm.h"
 #include "cm_regbits_34xx.h"
 
-/* CM_CLKEN_PLL*.EN* bit values */
-#define DPLL_LOCKED		0x7
 
 /**
 * omap3_dpll_recalc - recalculate DPLL rate

@@ -79,7 +77,7 @@
 	WARN_ON(!dd->control_reg || !dd->enable_mask);
 
 	v = cm_read_reg(dd->control_reg) & dd->enable_mask;
-	if (v != DPLL_LOCKED)
+	if (v != dd->enable_mask)
 		clk->rate = clk->parent->rate;
 	else
 		clk->rate = clk->parent->rate * 2;

Index: linux-omap-git/arch/arm/mach-omap2/clock34xx.h
===================================================================

arch/arm/mach-omap2/clock34xx.h +18 -9

@@ -437,14 +437,16 @@
 static struct clk omap_96m_alwon_fck = {
 	.name		= "omap_96m_alwon_fck",
 	.parent		= &dpll4_m2x2_ck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				 PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 
 static struct clk omap_96m_fck = {
 	.name		= "omap_96m_fck",
 	.parent		= &omap_96m_alwon_fck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -830,7 +832,8 @@
 static struct clk core_96m_fck = {
 	.name		= "core_96m_fck",
 	.parent		= &omap_96m_fck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -862,7 +865,8 @@
 };
 
 static struct clk i2c3_fck = {
-	.name		= "i2c3_fck",
+	.name		= "i2c_fck",
+	.id		= 3,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C3_SHIFT,

@@ -871,7 +875,8 @@
 };
 
 static struct clk i2c2_fck = {
-	.name		= "i2c2_fck",
+	.name		= "i2c_fck",
+	.id 		= 2,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C2_SHIFT,

@@ -880,7 +885,8 @@
 };
 
 static struct clk i2c1_fck = {
-	.name		= "i2c1_fck",
+	.name		= "i2c_fck",
+	.id		= 1,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C1_SHIFT,

@@ -1222,7 +1228,8 @@
 };
 
 static struct clk i2c3_ick = {
-	.name		= "i2c3_ick",
+	.name		= "i2c_ick",
+	.id		= 3,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C3_SHIFT,

@@ -1231,7 +1238,8 @@
 };
 
 static struct clk i2c2_ick = {
-	.name		= "i2c2_ick",
+	.name		= "i2c_ick",
+	.id		= 2,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C2_SHIFT,

@@ -1240,7 +1248,8 @@
 };
 
 static struct clk i2c1_ick = {
-	.name		= "i2c1_ick",
+	.name		= "i2c_ick",
+	.id		= 1,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C1_SHIFT,

_______________________________________________
Linux-omap-open-source mailing list
[email protected]
http://linux.omap.com/mailman/listinfo/linux-omap-open-source

Your changes to clock34xx.h look good. But the change to clock34xx.c isn't quite right. The dpll_params.enable_mask field is intended to be a
mask for the register's enable bits - i.e., something one would logical-AND with the shifted contents of CM_CLKEN_PLL* -

rather than the
value to logical-OR into those bits to indicate a locked DPLL. The two
values happen to coincide, so the change is functionally harmless; but
semantically, not what was intended for the enable_mask field. Would you
care to resubmit the patch with the clock34xx.c change dropped?

When we were debugging the clock code, we found that the change in clock.c was required to reflect the correct rate of dpll4_x2_ck.

arch/arm/mach-omap2/clock34xx.c +0 -0

 	v = cm_read_reg(dd->control_reg) & dd->enable_mask;
 -	if (v != DPLL_LOCKED)
 +	if (v != dd->enable_mask)
 		clk->rate = clk->parent->rate;
 	else
 		clk->rate = clk->parent->rate * 2;

Previously, DPLL_LOCKED was defined as 0x7 - this worked for DPLL3 but for DPLL4, the value is supposed to be 0x7000.

If there was an enable_bit in dpll_data structure, we could have shifted DPLL_LOCKED by enable_bit and compared with the register value. Since the current implementation will return wrong rate for DPLL4, we made this modification.
Can you suggest some other way of implementing this.