arch: arm64: Enable support for Samsung Exynos7 SoC

Cc Tomasz Figa <[email protected]>

Cc Mike Turquette <[email protected]>

---
 drivers/clk/samsung/clk-pll.c | 25 ++++++++++++++++++++-----
 drivers/clk/samsung/clk-pll.h |  4 ++++
 2 files changed, 24 insertions(+), 5 deletions(-)

drivers/clk/samsung/clk-pll.c +20 -5

index b07fad2..9d70e5c 100644
@@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
 
 #define PLL46XX_VSEL_MASK	(1)
 #define PLL46XX_MDIV_MASK	(0x1FF)
+#define PLL1460X_MDIV_MASK	(0x3FF)
+
 #define PLL46XX_PDIV_MASK	(0x3F)
 #define PLL46XX_SDIV_MASK	(0x7)
 #define PLL46XX_VSEL_SHIFT	(27)

@@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
 
 	pll_con0 = __raw_readl(pll->con_reg);
 	pll_con1 = __raw_readl(pll->con_reg + 4);
-	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
+				PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
 	pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
 	kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
 					pll_con1 & PLL46XX_KDIV_MASK;
 
-	shift = pll->type == pll_4600 ? 16 : 10;
+	shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
+
 	fvco *= (mdiv << shift) + kdiv;
 	do_div(fvco, (pdiv << sdiv));
 	fvco >>= shift;

@@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
 		lock = 0xffff;
 
 	/* Set PLL PMS and VSEL values. */
-	con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+	if (pll->type == pll_1460x) {
+		con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+			(PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
+			(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
+	} else {
+		con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
 			(PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
 			(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
 			(PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
+		con0 |=	rate->vsel << PLL46XX_VSEL_SHIFT;
+	}
+
 	con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
 			(rate->pdiv << PLL46XX_PDIV_SHIFT) |
-			(rate->sdiv << PLL46XX_SDIV_SHIFT) |
-			(rate->vsel << PLL46XX_VSEL_SHIFT);
+			(rate->sdiv << PLL46XX_SDIV_SHIFT);
 
 	/* Set PLL K, MFR and MRR values. */
 	con1 = __raw_readl(pll->con_reg + 0x4);

@@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 	/* clk_ops for 35xx and 2550 are similar */
 	case pll_35xx:
 	case pll_2550:
+	case pll_1450x:
+	case pll_1451x:
+	case pll_1452x:
 		if (!pll->rate_table)
 			init.ops = &samsung_pll35xx_clk_min_ops;
 		else

@@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 	case pll_4600:
 	case pll_4650:
 	case pll_4650c:
+	case pll_1460x:
 		if (!pll->rate_table)
 			init.ops = &samsung_pll46xx_clk_min_ops;
 		else

drivers/clk/samsung/clk-pll.h +4 -0

index c0ed4d4..213de9a 100644
@@ -33,6 +33,10 @@ enum samsung_pll_type {
 	pll_s3c2440_mpll,
 	pll_2550xx,
 	pll_2650xx,
+	pll_1450x,
+	pll_1451x,
+	pll_1452x,
+	pll_1460x,
 };
 
 #define PLL_35XX_RATE(_rate, _m, _p, _s)			\

Signature · 1 line

2.1.0

Abhilash Kesavan

author

2014-09-22 04:47 UTC #2 lore raw

PATCH v5 2/8 clk: samsung: Factor out the common code to clk.c

From: Naveen Krishna Ch <[email protected]>

While adding clock support for Exynos5260, the infrastructure to register multiple clock controllers was introduced. Factor out the support for registering multiple clock controller from Exynos5260 clock code to common samsung clock code so that it can be used by other Exynos SoC which have multiple clock controllers.

Signed-off-by Naveen Krishna Ch <[email protected]>

Cc Tomasz Figa <[email protected]>

Cc Mike Turquette <[email protected]>

---
 drivers/clk/samsung/clk-exynos5260.c | 185 +++++------------------------------
 drivers/clk/samsung/clk.c            |  95 ++++++++++++++++++
 drivers/clk/samsung/clk.h            |  34 +++++++
 3 files changed, 155 insertions(+), 159 deletions(-)

drivers/clk/samsung/clk-exynos5260.c +26 ~~-159~~

index ce3de97..64aeadf 100644
@@ -11,10 +11,8 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/syscore_ops.h>
 
 #include "clk-exynos5260.h"
 #include "clk.h"

@@ -22,39 +20,6 @@
 
 #include <dt-bindings/clock/exynos5260-clk.h>
 
-static LIST_HEAD(clock_reg_cache_list);
-
-struct exynos5260_clock_reg_cache {
-	struct list_head node;
-	void __iomem *reg_base;
-	struct samsung_clk_reg_dump *rdump;
-	unsigned int rd_num;
-};
-
-struct exynos5260_cmu_info {
-	/* list of pll clocks and respective count */
-	struct samsung_pll_clock *pll_clks;
-	unsigned int nr_pll_clks;
-	/* list of mux clocks and respective count */
-	struct samsung_mux_clock *mux_clks;
-	unsigned int nr_mux_clks;
-	/* list of div clocks and respective count */
-	struct samsung_div_clock *div_clks;
-	unsigned int nr_div_clks;
-	/* list of gate clocks and respective count */
-	struct samsung_gate_clock *gate_clks;
-	unsigned int nr_gate_clks;
-	/* list of fixed clocks and respective count */
-	struct samsung_fixed_rate_clock *fixed_clks;
-	unsigned int nr_fixed_clks;
-	/* total number of clocks with IDs assigned*/
-	unsigned int nr_clk_ids;
-
-	/* list and number of clocks registers */
-	unsigned long *clk_regs;
-	unsigned int nr_clk_regs;
-};
-
 /*
  * Applicable for all 2550 Type PLLS for Exynos5260, listed below
  * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.

@@ -113,104 +78,6 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = {
 	PLL_36XX_RATE(66000000, 176, 2, 5, 0),
 };
 
-#ifdef CONFIG_PM_SLEEP
-
-static int exynos5260_clk_suspend(void)
-{
-	struct exynos5260_clock_reg_cache *cache;
-
-	list_for_each_entry(cache, &clock_reg_cache_list, node)
-		samsung_clk_save(cache->reg_base, cache->rdump,
-				cache->rd_num);
-
-	return 0;
-}
-
-static void exynos5260_clk_resume(void)
-{
-	struct exynos5260_clock_reg_cache *cache;
-
-	list_for_each_entry(cache, &clock_reg_cache_list, node)
-		samsung_clk_restore(cache->reg_base, cache->rdump,
-				cache->rd_num);
-}
-
-static struct syscore_ops exynos5260_clk_syscore_ops = {
-	.suspend = exynos5260_clk_suspend,
-	.resume = exynos5260_clk_resume,
-};
-
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
-			unsigned long *rdump,
-			unsigned long nr_rdump)
-{
-	struct exynos5260_clock_reg_cache *reg_cache;
-
-	reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
-			GFP_KERNEL);
-	if (!reg_cache)
-		panic("could not allocate register cache.\n");
-
-	reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
-
-	if (!reg_cache->rdump)
-		panic("could not allocate register dump storage.\n");
-
-	if (list_empty(&clock_reg_cache_list))
-		register_syscore_ops(&exynos5260_clk_syscore_ops);
-
-	reg_cache->rd_num = nr_rdump;
-	reg_cache->reg_base = reg_base;
-	list_add_tail(&reg_cache->node, &clock_reg_cache_list);
-}
-
-#else
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
-			unsigned long *rdump,
-			unsigned long nr_rdump){}
-#endif
-
-/*
- * Common function which registers plls, muxes, dividers and gates
- * for each CMU. It also add CMU register list to register cache.
- */
-
-void __init exynos5260_cmu_register_one(struct device_node *np,
-			struct exynos5260_cmu_info *cmu)
-{
-	void __iomem *reg_base;
-	struct samsung_clk_provider *ctx;
-
-	reg_base = of_iomap(np, 0);
-	if (!reg_base)
-		panic("%s: failed to map registers\n", __func__);
-
-	ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
-	if (!ctx)
-		panic("%s: unable to alllocate ctx\n", __func__);
-
-	if (cmu->pll_clks)
-		samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
-			reg_base);
-	if (cmu->mux_clks)
-		samsung_clk_register_mux(ctx,  cmu->mux_clks,
-			cmu->nr_mux_clks);
-	if (cmu->div_clks)
-		samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
-	if (cmu->gate_clks)
-		samsung_clk_register_gate(ctx, cmu->gate_clks,
-			cmu->nr_gate_clks);
-	if (cmu->fixed_clks)
-		samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
-			cmu->nr_fixed_clks);
-	if (cmu->clk_regs)
-		exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
-			cmu->nr_clk_regs);
-
-	samsung_clk_of_add_provider(np, ctx);
-}
-
-
 /* CMU_AUD */
 
 static unsigned long aud_clk_regs[] __initdata = {

@@ -268,7 +135,7 @@ struct samsung_gate_clock aud_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_aud_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.mux_clks = aud_mux_clks;
 	cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks);

@@ -280,7 +147,7 @@ static void __init exynos5260_clk_aud_init(struct device_node *np)
 	cmu.clk_regs = aud_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",

@@ -458,7 +325,7 @@ struct samsung_gate_clock disp_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_disp_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.mux_clks = disp_mux_clks;
 	cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks);

@@ -470,7 +337,7 @@ static void __init exynos5260_clk_disp_init(struct device_node *np)
 	cmu.clk_regs = disp_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",

@@ -522,7 +389,7 @@ static struct samsung_pll_clock egl_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_egl_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.pll_clks = egl_pll_clks;
 	cmu.nr_pll_clks =  ARRAY_SIZE(egl_pll_clks);

@@ -534,7 +401,7 @@ static void __init exynos5260_clk_egl_init(struct device_node *np)
 	cmu.clk_regs = egl_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(egl_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",

@@ -624,7 +491,7 @@ struct samsung_gate_clock fsys_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_fsys_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.mux_clks = fsys_mux_clks;
 	cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks);

@@ -634,7 +501,7 @@ static void __init exynos5260_clk_fsys_init(struct device_node *np)
 	cmu.clk_regs = fsys_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",

@@ -713,7 +580,7 @@ struct samsung_gate_clock g2d_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_g2d_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.mux_clks = g2d_mux_clks;
 	cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks);

@@ -725,7 +592,7 @@ static void __init exynos5260_clk_g2d_init(struct device_node *np)
 	cmu.clk_regs = g2d_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",

@@ -774,7 +641,7 @@ static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_g3d_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.pll_clks = g3d_pll_clks;
 	cmu.nr_pll_clks =  ARRAY_SIZE(g3d_pll_clks);

@@ -788,7 +655,7 @@ static void __init exynos5260_clk_g3d_init(struct device_node *np)
 	cmu.clk_regs = g3d_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",

@@ -909,7 +776,7 @@ struct samsung_gate_clock gscl_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_gscl_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.mux_clks = gscl_mux_clks;
 	cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks);

@@ -921,7 +788,7 @@ static void __init exynos5260_clk_gscl_init(struct device_node *np)
 	cmu.clk_regs = gscl_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",

@@ -1028,7 +895,7 @@ struct samsung_gate_clock isp_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_isp_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.mux_clks = isp_mux_clks;
 	cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks);

@@ -1040,7 +907,7 @@ static void __init exynos5260_clk_isp_init(struct device_node *np)
 	cmu.clk_regs = isp_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(isp_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",

@@ -1092,7 +959,7 @@ static struct samsung_pll_clock kfc_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_kfc_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.pll_clks = kfc_pll_clks;
 	cmu.nr_pll_clks =  ARRAY_SIZE(kfc_pll_clks);

@@ -1104,7 +971,7 @@ static void __init exynos5260_clk_kfc_init(struct device_node *np)
 	cmu.clk_regs = kfc_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",

@@ -1148,7 +1015,7 @@ struct samsung_gate_clock mfc_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_mfc_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.mux_clks = mfc_mux_clks;
 	cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks);

@@ -1160,7 +1027,7 @@ static void __init exynos5260_clk_mfc_init(struct device_node *np)
 	cmu.clk_regs = mfc_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",

@@ -1295,7 +1162,7 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_mif_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.pll_clks = mif_pll_clks;
 	cmu.nr_pll_clks =  ARRAY_SIZE(mif_pll_clks);

@@ -1309,7 +1176,7 @@ static void __init exynos5260_clk_mif_init(struct device_node *np)
 	cmu.clk_regs = mif_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(mif_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",

@@ -1503,7 +1370,7 @@ struct samsung_gate_clock peri_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_peri_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.mux_clks = peri_mux_clks;
 	cmu.nr_mux_clks = ARRAY_SIZE(peri_mux_clks);

@@ -1515,7 +1382,7 @@ static void __init exynos5260_clk_peri_init(struct device_node *np)
 	cmu.clk_regs = peri_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(peri_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",

@@ -1959,7 +1826,7 @@ static struct samsung_pll_clock top_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_top_init(struct device_node *np)
 {
-	struct exynos5260_cmu_info cmu = {0};
+	struct samsung_cmu_info cmu = {0};
 
 	cmu.pll_clks = top_pll_clks;
 	cmu.nr_pll_clks =  ARRAY_SIZE(top_pll_clks);

@@ -1975,7 +1842,7 @@ static void __init exynos5260_clk_top_init(struct device_node *np)
 	cmu.clk_regs = top_clk_regs;
 	cmu.nr_clk_regs = ARRAY_SIZE(top_clk_regs);
 
-	exynos5260_cmu_register_one(np, &cmu);
+	samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",

drivers/clk/samsung/clk.c +95 -0

104 lines not on this page · raw message

drivers/clk/samsung/clk.h +34 -0

index 66ab36b..b3d0f4d 100644
@@ -324,6 +324,37 @@ struct samsung_pll_clock {
 	__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,	\
 		_lock, _con, _rtable, _alias)
 
+struct samsung_clock_reg_cache {
+	struct list_head node;
+	void __iomem *reg_base;
+	struct samsung_clk_reg_dump *rdump;
+	unsigned int rd_num;
+};
+
+struct samsung_cmu_info {
+	/* list of pll clocks and respective count */
+	struct samsung_pll_clock *pll_clks;
+	unsigned int nr_pll_clks;
+	/* list of mux clocks and respective count */
+	struct samsung_mux_clock *mux_clks;
+	unsigned int nr_mux_clks;
+	/* list of div clocks and respective count */
+	struct samsung_div_clock *div_clks;
+	unsigned int nr_div_clks;
+	/* list of gate clocks and respective count */
+	struct samsung_gate_clock *gate_clks;
+	unsigned int nr_gate_clks;
+	/* list of fixed clocks and respective count */
+	struct samsung_fixed_rate_clock *fixed_clks;
+	unsigned int nr_fixed_clks;
+	/* total number of clocks with IDs assigned*/
+	unsigned int nr_clk_ids;
+
+	/* list and number of clocks registers */
+	unsigned long *clk_regs;
+	unsigned int nr_clk_regs;
+};
+
 extern struct samsung_clk_provider *__init samsung_clk_init(
 			struct device_node *np, void __iomem *base,
 			unsigned long nr_clks);

@@ -362,6 +393,9 @@ extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 			struct samsung_pll_clock *pll_list,
 			unsigned int nr_clk, void __iomem *base);
 
+extern void __init samsung_cmu_register_one(struct device_node *,
+			struct samsung_cmu_info *);
+
 extern unsigned long _get_rate(const char *clk_name);
 
 extern void samsung_clk_save(void __iomem *base,

Signature · 1 line

2.1.0

Abhilash Kesavan

author

2014-09-22 04:47 UTC #3 lore raw

PATCH v5 3/8 clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info

From: Naveen Krishna Ch <[email protected]>

Add the fields "fixed_factor_clks" and "nr_fixed_factor_clks" to "struct exynos_cmu_info" to allow registering of fixed factor clocks as well with exynos_cmu_register_one().

Signed-off-by Naveen Krishna Ch <[email protected]>

Cc Tomasz Figa <[email protected]>

Cc Mike Turquette <[email protected]>

---
 drivers/clk/samsung/clk.c | 3 +++
 drivers/clk/samsung/clk.h | 3 +++
 2 files changed, 6 insertions(+)

drivers/clk/samsung/clk.c +3 -0

index a648236..dd1f7c9 100644
@@ -402,6 +402,9 @@ void __init samsung_cmu_register_one(struct device_node *np,
 	if (cmu->fixed_clks)
 		samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
 			cmu->nr_fixed_clks);
+	if (cmu->fixed_factor_clks)
+		samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
+			cmu->nr_fixed_factor_clks);
 	if (cmu->clk_regs)
 		samsung_clk_sleep_init(reg_base, cmu->clk_regs,
 			cmu->nr_clk_regs);

drivers/clk/samsung/clk.h +3 -0

index b3d0f4d..3f471e9 100644
@@ -347,6 +347,9 @@ struct samsung_cmu_info {
 	/* list of fixed clocks and respective count */
 	struct samsung_fixed_rate_clock *fixed_clks;
 	unsigned int nr_fixed_clks;
+	/* list of fixed factor clocks and respective count */
+	struct samsung_fixed_factor_clock *fixed_factor_clks;
+	unsigned int nr_fixed_factor_clks;
 	/* total number of clocks with IDs assigned*/
 	unsigned int nr_clk_ids;

Signature · 1 line

2.1.0

Abhilash Kesavan

author

2014-09-22 04:47 UTC #4 lore raw

PATCH v5 4/8 clk: samsung: add initial clock support for Exynos7 SoC

From: Naveen Krishna Ch <[email protected]>

Add initial clock support for Exynos7 SoC which is required to bring up platforms based on Exynos7.

Signed-off-by Naveen Krishna Ch <[email protected]>

Cc Tomasz Figa <[email protected]>

Cc Mike Turquette <[email protected]>

---
 .../devicetree/bindings/clock/exynos7-clock.txt    |  67 ++++
 drivers/clk/samsung/Makefile                       |   1 +
 drivers/clk/samsung/clk-exynos7.c                  | 425 +++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h            |  49 +++
 4 files changed, 542 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt
 create mode 100644 drivers/clk/samsung/clk-exynos7.c
 create mode 100644 include/dt-bindings/clock/exynos7-clk.h

Documentation/devicetree/bindings/clock/exynos7-clock.txt new file +67 -0

new file mode 100644
index 0000000..789f761
@@ -0,0 +1,67 @@
+* Samsung Exynos7 Clock Controller
+
+Exynos7 clock controller has various blocks which are instantiated
+independently from the device-tree. These clock controllers
+generate and supply clocks to various hardware blocks within
+the SoC.
+
+Each clock is assigned an identifier and client nodes can use
+this identifier to specify the clock which they consume. All
+available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos7-clk.h header and can be used in
+device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - "fin_pll" - PLL input clock from XXTI
+
+Required Properties for Clock Controller:
+
+ - compatible: clock controllers will use one of the following
+	compatible strings to indicate the clock controller
+	functionality.
+
+	- "samsung,exynos7-clock-topc"
+	- "samsung,exynos7-clock-top0"
+	- "samsung,exynos7-clock-peric0"
+	- "samsung,exynos7-clock-peric1"
+	- "samsung,exynos7-clock-peris"
+
+ - reg: physical base address of the controller and the length of
+	memory mapped region.
+
+ - #clock-cells: should be 1.
+
+ - clocks: list of clock identifiers which are fed as the input to
+	the given clock controller. Please refer the next section to
+	find the input clocks for a given controller.
+
+- clock-names: list of names of clocks which are fed as the input
+	to the given clock controller.
+
+Input clocks for top0 clock controller:
+	- fin_pll
+	- dout_sclk_bus0_pll
+	- dout_sclk_bus1_pll
+	- dout_sclk_cc_pll
+	- dout_sclk_mfc_pll
+
+Input clocks for peric0 clock controller:
+	- fin_pll
+	- dout_aclk_peric0_66
+	- sclk_uart0
+
+Input clocks for peric1 clock controller:
+	- fin_pll
+	- dout_aclk_peric1_66
+	- sclk_uart1
+	- sclk_uart2
+	- sclk_uart3
+
+Input clocks for peris clock controller:
+	- fin_pll
+	- dout_aclk_peris_66

drivers/clk/samsung/Makefile +1 -0

index 6fb4bc6..137bf9b 100644
@@ -12,6 +12,7 @@ obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o
 obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-clkout.o
+obj-$(CONFIG_ARCH_EXYNOS7)	+= clk-exynos7.o
 obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
 obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
 obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o

drivers/clk/samsung/clk-exynos7.c new file +425 -0

425 lines not on this page · raw message

include/dt-bindings/clock/exynos7-clk.h new file +49 -0

49 lines not on this page · raw message

Signature · 1 line

2.1.0

Abhilash Kesavan

author

2014-09-22 04:47 UTC #5 lore raw

PATCH v5 5/8 arm64: dts: Add initial device tree support for EXYNOS7

From: Naveen Krishna Ch <[email protected]>

Add initial device tree nodes for EXYNOS7 SoC and board dts file to support Espresso board based on Exynos7 SoC.

Signed-off-by Naveen Krishna Ch <[email protected]>

Acked-by Kukjin Kim <[email protected]>

Cc Rob Herring <[email protected]>

Cc Catalin Marinas <[email protected]>

---
 arch/arm64/boot/dts/Makefile                    |   1 +
 arch/arm64/boot/dts/exynos/Makefile             |   5 +
 arch/arm64/boot/dts/exynos/exynos7-espresso.dts |  39 +++++
 arch/arm64/boot/dts/exynos/exynos7.dtsi         | 183 ++++++++++++++++++++++++
 4 files changed, 228 insertions(+)
 create mode 100644 arch/arm64/boot/dts/exynos/Makefile
 create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
 create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi

arch/arm64/boot/dts/Makefile +1 -0

index 309c3dc..b13bf21 100644
@@ -1,5 +1,6 @@
 dts-dirs += apm
 dts-dirs += arm
+dts-dirs += exynos
 
 always		:= $(dtb-y)
 subdir-y	:= $(dts-dirs)

arch/arm64/boot/dts/exynos/Makefile new file +5 -0

new file mode 100644
index 0000000..20310e5
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always		:= $(dtb-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb

arch/arm64/boot/dts/exynos/exynos7-espresso.dts new file +39 -0

new file mode 100644
index 0000000..e2c8283
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos7.dtsi"
+
+/ {
+	model = "Samsung Exynos7 Espresso board based on EXYNOS7";
+	compatible = "samsung,exynos7-espresso", "samsung,exynos7";
+
+	aliases {
+		serial0 = &serial_2;
+	};
+
+	chosen {
+		linux,stdout-path = &serial_2;
+	};
+
+	memory at 40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0xC0000000>;
+	};
+};
+
+&fin_pll {
+	clock-frequency = <24000000>;
+};
+
+&serial_2 {
+	status = "okay";
+};

arch/arm64/boot/dts/exynos/exynos7.dtsi new file +183 -0

183 lines not on this page · raw message

Signature · 1 line

2.1.0

Abhilash Kesavan

author

2014-09-22 04:47 UTC #6 lore raw

PATCH v5 6/8 arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support

From: Alim Akhtar <[email protected]>

This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC.

Signed-off-by Alim Akhtar <[email protected]>

Signed-off-by Naveen Krishna Ch <[email protected]>

Cc Rob Herring <[email protected]>

Cc Catalin Marinas <[email protected]>

---
 arch/arm64/Kconfig | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm64/Kconfig +12 -0

index 2ca2ebd..1874e1a 100644
@@ -137,6 +137,18 @@ source "kernel/Kconfig.freezer"
 
 menu "Platform selection"
 
+config ARCH_EXYNOS
+	bool
+	help
+	  This enables support for Samsung Exynos SoC family
+
+config ARCH_EXYNOS7
+	bool "ARMv8 based Samsung Exynos7"
+	select ARCH_EXYNOS
+	select COMMON_CLK_SAMSUNG
+	help
+	  This enables support for Samsung Exynos7 SoC family
+
 config ARCH_VEXPRESS
 	bool "ARMv8 software model (Versatile Express)"
 	select ARCH_REQUIRE_GPIOLIB

Signature · 1 line

2.1.0

Abhilash Kesavan

author

2014-09-22 04:47 UTC #7 lore raw

PATCH v5 7/8 arm64: Enable Exynos7 SOC in the defconfig

From: Alim Akhtar <[email protected]>

Enable Exynos7 SOC in the arm64 defconfig. Also enable the samsung serial driver needed by this SoC.

Signed-off-by Alim Akhtar <[email protected]>

---
 arch/arm64/configs/defconfig | 4 ++++
 1 file changed, 4 insertions(+)

arch/arm64/configs/defconfig +4 -0

index d92ef3c..f6db9b2 100644
@@ -32,6 +32,8 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS7=y
 CONFIG_ARCH_VEXPRESS=y
 CONFIG_ARCH_XGENE=y
 CONFIG_SMP=y

@@ -82,6 +84,8 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_VIRTIO_CONSOLE=y
 # CONFIG_HW_RANDOM is not set

Signature · 1 line

2.1.0

Abhilash Kesavan

author

2014-09-22 04:47 UTC #8 lore raw

PATCH v5 8/8 arm64: dts: add <dt-bindings/> symlink

From: Pankaj Dubey <[email protected]>

Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to match the ones in ARM architectures so that preprocessed device tree files can include various useful constant definitions.

See commit c58299aa8754 ("kbuild: create an "include chroot" for DT bindings") merged in v3.10-rc1 for details.

CC Catalin Marinas <[email protected]>

Signed-off-by Pankaj Dubey <[email protected]>

[1] http://www.spinics.net/lists/linux-kbuild/msg08656.html

---
 arch/arm64/boot/dts/include/dt-bindings | 1 +
 1 file changed, 1 insertion(+)
 create mode 120000 arch/arm64/boot/dts/include/dt-bindings

arch/arm64/boot/dts/include/dt-bindings new file +1 -0

new file mode 120000
index 0000000..1e89bce
@@ -0,0 +1 @@
+../../../../../include/dt-bindings/
\ No newline at end of file

Signature · 1 line

2.1.0

Chanho Park

2014-09-23 07:46 UTC #9 lore raw

PATCH v5 8/8 arm64: dts: add <dt-bindings/> symlink

Hi,

Quoted 38 lines

-----Original Message-----
From: linux-arm-kernel [mailto:linux-arm-kernel- bounces at lists.infradead.org] On Behalf Of Abhilash Kesavan
Sent: Monday, September 22, 2014 1:47 PM
To: linux-samsung-soc at vger.kernel.org; linux-arm- kernel at lists.infradead.org; devicetree at vger.kernel.org; catalin.marinas at arm.com
Cc: naveenkrishna.ch at gmail.com; kesavan.abhilash at gmail.com; tomasz.figa at gmail.com
Subject: [PATCH v5 8/8] arm64: dts: add <dt-bindings/> symlink
From: Pankaj Dubey <[email protected]>
Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to match the ones in ARM architectures so that preprocessed device tree files can include various useful constant definitions.
See commit c58299aa8754 ("kbuild: create an "include chroot" for DT bindings")
merged in v3.10-rc1 for details.
CC Catalin Marinas <[email protected]>
Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Abhilash Kesavan <[email protected]>
Reviewed-by Thomas Abraham <[email protected]>
Tested-by Thomas Abraham <[email protected]>
---
 arch/arm64/boot/dts/include/dt-bindings | 1 +
 1 file changed, 1 insertion(+)
 create mode 120000 arch/arm64/boot/dts/include/dt-bindings
arch/arm64/boot/dts/include/dt-bindings new file +0 -0
new file mode 120000
index 0000000..1e89bce

arch/arm64/boot/dts/include/dt-bindings line 1

Quoted 2 lines

arch/arm64/boot/dts/include/dt-bindings new file +1 -0
@@ -0,0 +1 @@
+../../../../../include/dt-bindings/
\ No newline at end of file

^
It generates incorrect symlink. Please remove last line like below:

(quoted diff) +0 -0

b/arch/arm64/boot/dts/include/dt-bindings
new file mode 120000
index 0000000..499472b

arch/arm64/boot/dts/include/dt-bindings new file +1 -0

@@ -0,0 +1 @@
+../../../../../include/dt-bindings/

Best Regards,
Chanho Park

Abhilash Kesavan

2014-09-23 08:54 UTC #10 lore raw

PATCH v5 8/8 arm64: dts: add <dt-bindings/> symlink

Hi Chanho,

Quoted 52 lines · Chanho Park

Hi,
Quoted 38 lines
-----Original Message-----
From: linux-arm-kernel [mailto:linux-arm-kernel- bounces at lists.infradead.org] On Behalf Of Abhilash Kesavan
Sent: Monday, September 22, 2014 1:47 PM
To: linux-samsung-soc at vger.kernel.org; linux-arm- kernel at lists.infradead.org; devicetree at vger.kernel.org; catalin.marinas at arm.com
Cc: naveenkrishna.ch at gmail.com; kesavan.abhilash at gmail.com; tomasz.figa at gmail.com
Subject: [PATCH v5 8/8] arm64: dts: add <dt-bindings/> symlink
From: Pankaj Dubey <[email protected]>
Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to match the ones in ARM architectures so that preprocessed device tree files can include various useful constant definitions.
See commit c58299aa8754 ("kbuild: create an "include chroot" for DT bindings")
merged in v3.10-rc1 for details.
CC Catalin Marinas <[email protected]>
Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Abhilash Kesavan <[email protected]>
Reviewed-by Thomas Abraham <[email protected]>
Tested-by Thomas Abraham <[email protected]>
---
 arch/arm64/boot/dts/include/dt-bindings | 1 +
 1 file changed, 1 insertion(+)
 create mode 120000 arch/arm64/boot/dts/include/dt-bindings
arch/arm64/boot/dts/include/dt-bindings new file +0 -0
new file mode 120000
index 0000000..1e89bce
arch/arm64/boot/dts/include/dt-bindings line 1
Quoted 2 lines
arch/arm64/boot/dts/include/dt-bindings new file +1 -0
@@ -0,0 +1 @@
+../../../../../include/dt-bindings/
\ No newline at end of file
^
It generates incorrect symlink. Please remove last line like below:
arch/arm64/boot/dts/include/dt-bindings new file +0 -0
new file mode 120000
index 0000000..499472b

arch/arm64/boot/dts/include/dt-bindings line 1

Quoted 1 line

arch/arm64/boot/dts/include/dt-bindings new file +1 -0
@@ -0,0 +1 @@
+../../../../../include/dt-bindings/

I just re-checked this patch and it seems to be working fine. I did find a thread where patchwork appeared to be changing the patch causing issues [1]. Are you downloading this via patchwork ?

Regards,
Abhilash

Quoted 5 lines

--
Best Regards,
Chanho Park

Tomasz Figa

2014-09-22 08:52 UTC #11 lore raw

v5 cover arch: arm64: Enable support for Samsung Exynos7 SoC

Hi Abhilash,

Quoted 10 lines · Abhilash Kesavan

Changes since v4:
- Fixed comments from Tomasz Figa:
- Changed the namespace prefix from exynos to samsung
- Defined bindings to take all input clocks
- Sorted the Kconfig entries alphabetically in clock Makefile
- Used consistent 1 tab line breaks across the clock file
- Statically initialized the samsung_cmu_info struct
- Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment.
- Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed tags.

The clock patches look good to me, but since they are doing quite a lot of code moving I'd prefer to take them through clk tree. Based on the fact that there are no code dependencies between clock patches and remaining ones and Exynos7 is a new material for 3.18, I'm inclined to apply them to my tree if nobody minds.

Best regards,
Tomasz

Abhilash Kesavan

2014-09-30 15:12 UTC #12 lore raw

v5 cover arch: arm64: Enable support for Samsung Exynos7 SoC

Hi Tomasz,

Quoted 14 lines · Tomasz Figa

Hi Abhilash,
Quoted 10 lines · Abhilash Kesavan
Changes since v4:
- Fixed comments from Tomasz Figa:
- Changed the namespace prefix from exynos to samsung
- Defined bindings to take all input clocks
- Sorted the Kconfig entries alphabetically in clock Makefile
- Used consistent 1 tab line breaks across the clock file
- Statically initialized the samsung_cmu_info struct
- Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment.
- Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed tags.

Quoted 5 lines

The clock patches look good to me, but since they are doing quite a lot of code moving I'd prefer to take them through clk tree. Based on the fact that there are no code dependencies between clock patches and remaining ones and Exynos7 is a new material for 3.18, I'm inclined to apply them to my tree if nobody minds.

Will you be picking up the clock changes soon ?

Regards,
Abhilash

Quoted 3 lines

Best regards,
Tomasz

Tomasz Figa

2014-09-30 15:56 UTC #13 lore raw

v5 cover arch: arm64: Enable support for Samsung Exynos7 SoC

Quoted 17 lines · Abhilash Kesavan

Hi Tomasz,
Quoted 14 lines · Tomasz Figa
Hi Abhilash,
Quoted 10 lines · Abhilash Kesavan
Changes since v4:
- Fixed comments from Tomasz Figa:
- Changed the namespace prefix from exynos to samsung
- Defined bindings to take all input clocks
- Sorted the Kconfig entries alphabetically in clock Makefile
- Used consistent 1 tab line breaks across the clock file
- Statically initialized the samsung_cmu_info struct
- Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment.
- Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed tags.

Quoted 7 lines

Quoted 5 lines
The clock patches look good to me, but since they are doing quite a lot of code moving I'd prefer to take them through clk tree. Based on the fact that there are no code dependencies between clock patches and remaining ones and Exynos7 is a new material for 3.18, I'm inclined to apply them to my tree if nobody minds.
Will you be picking up the clock changes soon ?

I'd like to do so. Kukjin, since clock changes are a part of this series, might I have your Ack for them to be applied separately?

Best regards,
Tomasz

Kukjin Kim

2014-10-07 04:16 UTC #14 lore raw

v5 cover arch: arm64: Enable support for Samsung Exynos7 SoC

Quoted 25 lines · Tomasz Figa

Quoted 23 lines · Abhilash Kesavan
Hi Tomasz,
Quoted 19 lines · Tomasz Figa
Hi Abhilash,
Quoted 10 lines · Abhilash Kesavan
Changes since v4:
- Fixed comments from Tomasz Figa:
- Changed the namespace prefix from exynos to samsung
- Defined bindings to take all input clocks
- Sorted the Kconfig entries alphabetically in clock Makefile
- Used consistent 1 tab line breaks across the clock file
- Statically initialized the samsung_cmu_info struct
- Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment.
- Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed tags.
The clock patches look good to me, but since they are doing quite a lot of code moving I'd prefer to take them through clk tree. Based on the fact that there are no code dependencies between clock patches and remaining ones and Exynos7 is a new material for 3.18, I'm inclined to apply them to my tree if nobody minds.

Quoted 5 lines

Quoted 1 line
Will you be picking up the clock changes soon ?
I'd like to do so. Kukjin, since clock changes are a part of this series, might I have your Ack for them to be applied separately?

Sure, I'm fine so please go ahead with my ack on the changes.

Acked-by Kukjin Kim <[email protected]>

Thanks for your asking.

- Kukjin

Abhilash Kesavan

2014-10-08 05:48 UTC #15 lore raw

v5 cover arch: arm64: Enable support for Samsung Exynos7 SoC

Hi Tomasz,

Quoted 28 lines · Kukjin Kim

Quoted 27 lines · Tomasz Figa
Quoted 24 lines · Abhilash Kesavan
Hi Tomasz,
Quoted 14 lines · Tomasz Figa
Hi Abhilash,
Quoted 10 lines · Abhilash Kesavan
Changes since v4:
- Fixed comments from Tomasz Figa:
- Changed the namespace prefix from exynos to samsung
- Defined bindings to take all input clocks
- Sorted the Kconfig entries alphabetically in clock Makefile
- Used consistent 1 tab line breaks across the clock file
- Statically initialized the samsung_cmu_info struct
- Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment.
- Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed tags.
Quoted 5 lines
The clock patches look good to me, but since they are doing quite a lot of code moving I'd prefer to take them through clk tree. Based on the fact that there are no code dependencies between clock patches and remaining ones and Exynos7 is a new material for 3.18, I'm inclined to apply them to my tree if nobody minds.
Will you be picking up the clock changes soon ?

Quoted 8 lines

Quoted 3 lines
I'd like to do so. Kukjin, since clock changes are a part of this series, might I have your Ack for them to be applied separately?
Sure, I'm fine so please go ahead with my ack on the changes.
Acked-by Kukjin Kim <[email protected]>
Thanks for your asking.

Can you please pick up the clock changes now that Kukjin has ack'ed it.

Thanks,
Abhilash

Quoted 3 lines

- Kukjin

Abhilash Kesavan

2014-10-24 14:32 UTC #16 lore raw

v5 cover arch: arm64: Enable support for Samsung Exynos7 SoC

+Sylwester

Quoted 34 lines · Abhilash Kesavan

Hi Tomasz,
Quoted 31 lines · Kukjin Kim
Quoted 30 lines · Tomasz Figa
Quoted 17 lines · Abhilash Kesavan
Hi Tomasz,
Quoted 14 lines · Tomasz Figa
Hi Abhilash,
Quoted 10 lines · Abhilash Kesavan
Changes since v4:
- Fixed comments from Tomasz Figa:
- Changed the namespace prefix from exynos to samsung
- Defined bindings to take all input clocks
- Sorted the Kconfig entries alphabetically in clock Makefile
- Used consistent 1 tab line breaks across the clock file
- Statically initialized the samsung_cmu_info struct
- Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' comment.
- Added Kukjin Kim's ack along with Thomas Abraham's tested and reviewed tags.
Quoted 7 lines
Quoted 5 lines
The clock patches look good to me, but since they are doing quite a lot of code moving I'd prefer to take them through clk tree. Based on the fact that there are no code dependencies between clock patches and remaining ones and Exynos7 is a new material for 3.18, I'm inclined to apply them to my tree if nobody minds.
Will you be picking up the clock changes soon ?
I'd like to do so. Kukjin, since clock changes are a part of this series, might I have your Ack for them to be applied separately?

Quoted 7 lines

Quoted 5 lines
Sure, I'm fine so please go ahead with my ack on the changes.
Acked-by Kukjin Kim <[email protected]>
Thanks for your asking.
Can you please pick up the clock changes now that Kukjin has ack'ed it.

Sylwester, you mentioned in another thread that Tomasz might not be available for the next few days. Could you please consider applying the clock changes in this series to samsung clk-next if they look OK ?

Please take a look at clock changes at
http://www.spinics.net/lists/arm-kernel/msg370673.html too.

Regards,
Abhilash

Sylwester Nawrocki

maintainer

2014-10-27 16:47 UTC #17 lore raw

v5 cover arch: arm64: Enable support for Samsung Exynos7 SoC

Hi Abhilash,

Quoted 24 lines · Abhilash Kesavan

Quoted 22 lines · Abhilash Kesavan
Quoted 20 lines · Kukjin Kim
Quoted 9 lines · Tomasz Figa
Quoted 8 lines · Abhilash Kesavan
Quoted 6 lines · Tomasz Figa
The clock patches look good to me, but since they are doing quite a lot of code moving I'd prefer to take them through clk tree. Based on the fact that there are no code dependencies between clock patches and remaining ones and Exynos7 is a new material for 3.18, I'm inclined to apply them to my tree if nobody minds.
Quoted 5 lines
Quoted 1 line
Will you be picking up the clock changes soon ?
I'd like to do so. Kukjin, since clock changes are a part of this series, might I have your Ack for them to be applied separately?
Sure, I'm fine so please go ahead with my ack on the changes.
Acked-by Kukjin Kim <[email protected]>
Thanks for your asking.

Quoted 8 lines

Quoted 1 line
Can you please pick up the clock changes now that Kukjin has ack'ed it.
Sylwester, you mentioned in another thread that Tomasz might not be available for the next few days. Could you please consider applying the clock changes in this series to samsung clk-next if they look OK ?
Please take a look at clock changes at
http://www.spinics.net/lists/arm-kernel/msg370673.html too.

I've picked up patches from the $subject series. But please see my comment the the second series you've pointed out with the link above. If you decide to rearrange changes to exynos7-clk.h header file among those two series I will drop that 4 patches. Perhaps you could gather all pending exynos7 clk patches, fix any issues and send to me in one series ?
I'd like to avoid modifying indices assigned to specific clocks in subsequent patches, DT binding should be defined in advance and ideally be specifying exact indices for each possible clock.

--
Thanks,
Sylwester

Chanho Park

2014-09-23 07:50 UTC #18 lore raw

v5 cover arch: arm64: Enable support for Samsung Exynos7 SoC