virtual clock nodes for VDD1 and VDD2

Index: linux-omap-2.6/arch/arm/mach-omap2/clock34xx.h
===================================================================
@@ -35,6 +35,13 @@ static u32 omap3_dpll_autoidle_read(stru
 static int omap3_noncore_dpll_enable(struct clk *clk);
 static void omap3_noncore_dpll_disable(struct clk *clk);
 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+static void omap3_table_recalc(struct clk *clk);
+static long omap3_round_to_table_rate(struct clk *clk, unsigned long rate);
+static int omap3_select_table_rate(struct clk *clk, unsigned long rate);
+
+extern struct vdd_prcm_config vdd1_rate_table[];
+extern struct vdd_prcm_config vdd2_rate_table[];
+extern struct vdd_prcm_config iva2_rate_table[];
 
 /* Maximum DPLL multiplier, divider values for OMAP3 */
 #define OMAP3_MAX_DPLL_MULT		2048

@@ -3046,6 +3053,24 @@ static struct clk wdt1_fck = {
 	.recalc		= &followparent_recalc,
 };
 
+static struct clk virt_vdd1_prcm_set = {
+	.name = "virt_vdd1_prcm_set",
+	.flags = CLOCK_IN_OMAP343X | VIRTUAL_CLOCK | ALWAYS_ENABLED,
+	.parent = &mpu_ck, /* Indexed by mpu speed, no parent */
+	.recalc = &omap3_table_recalc, /*sets are keyed on mpu rate */
+	.set_rate = &omap3_select_table_rate,
+	.round_rate = &omap3_round_to_table_rate,
+};
+
+static struct clk virt_vdd2_prcm_set = {
+	.name = "virt_vdd2_prcm_set",
+	.flags = CLOCK_IN_OMAP343X | VIRTUAL_CLOCK | ALWAYS_ENABLED,
+	.parent = &core_ck,
+	.recalc = &omap3_table_recalc,
+	.set_rate = &omap3_select_table_rate,
+	.round_rate = &omap3_round_to_table_rate,
+};
+
 static struct clk *onchip_34xx_clks[] __initdata = {
 	&omap_32k_fck,
 	&virt_12m_ck,

@@ -3258,6 +3283,9 @@ static struct clk *onchip_34xx_clks[] __
 	&secure_32k_fck,
 	&gpt12_fck,
 	&wdt1_fck,
+	/* virtual group clock */
+	&virt_vdd1_prcm_set,
+	&virt_vdd2_prcm_set,
 };
 
 #endif

245 lines not on this page · raw message

Index: linux-omap-2.6/include/asm-arm/arch-omap/clock.h
===================================================================
@@ -109,6 +109,14 @@ struct clk_functions {
 #endif
 };
 
+#ifdef CONFIG_ARCH_OMAP3
+struct vdd_prcm_config {
+	unsigned long speed;
+	unsigned long opp;
+	unsigned long flags;
+};
+#endif
+
 extern unsigned int mpurate;
 
 extern int clk_init(struct clk_functions *custom_clocks);

Index: linux-omap-2.6/arch/arm/mach-omap2/board-3430sdp.c
===================================================================
@@ -40,6 +40,7 @@
 #include <asm/arch/keypad.h>
 #include <asm/arch/dma.h>
 #include <asm/arch/gpmc.h>
+#include <asm/arch/clock.h>
 
 #include <asm/io.h>
 #include <asm/delay.h>

@@ -49,6 +50,43 @@
 #define ENABLE_VAUX3_DEDICATED	0x03
 #define ENABLE_VAUX3_DEV_GRP	0x20
 
+struct vdd_prcm_config vdd1_rate_table[] = {
+	{0, 0, 0},
+	/*OPP1*/
+	{S125M, VDD1_OPP1, 0},
+	/*OPP2*/
+	{S250M, VDD1_OPP2, 0},
+	/*OPP3*/
+	{S500M, VDD1_OPP3, 0},
+	/*OPP4*/
+	{S550M, VDD1_OPP4, 0},
+	/*OPP5*/
+	{S600M, VDD1_OPP5, 0},
+};
+
+struct vdd_prcm_config vdd2_rate_table[] = {
+	{0, 0, 0},
+	/*OPP1*/
+	{0, VDD2_OPP1, 0},
+	/*OPP2*/
+	{S83M, VDD2_OPP2, 0},
+	/*OPP3*/
+	{S166M, VDD2_OPP3, 0},
+};
+
+struct vdd_prcm_config iva2_rate_table[] = {
+	{0, 0, 0},
+	/*OPP1*/
+	{S90M, VDD1_OPP1, 0},
+	/*OPP2*/
+	{S180M, VDD1_OPP2, 0},
+	/*OPP3*/
+	{S360M, VDD1_OPP3, 0},
+	/*OPP4*/
+	{S400M, VDD1_OPP4, 0},
+	/*OPP5*/
+	{S430M, VDD1_OPP5, 0},
+};
 
 static struct resource sdp3430_smc91x_resources[] = {
 	[0] = {

Index: linux-omap-2.6/include/asm-arm/arch-omap/board-3430sdp.h
===================================================================
@@ -67,5 +67,40 @@ extern void sdp3430_flash_init(void);
 #define FLASH_SIZE_SDPV1	SZ_64M
 #define FLASH_SIZE_SDPV2	SZ_128M
 
+/* MPU speeds */
+#define S600M   600000000
+#define S550M   550000000
+#define S500M   500000000
+#define S250M   250000000
+#define S125M   125000000
+
+/* IVA speeds */
+#define S430M   430000000
+#define S400M   400000000
+#define S360M   360000000
+#define S180M   180000000
+#define S90M    90000000
+
+/* L3 speeds */
+#define S83M    83000000
+#define S166M   166000000
+
+/* VDD1 OPPS */
+#define VDD1_OPP1       0x1
+#define VDD1_OPP2       0x2
+#define VDD1_OPP3       0x3
+#define VDD1_OPP4       0x4
+#define VDD1_OPP5       0x5
+
+/* VDD2 OPPS */
+#define VDD2_OPP1       0x1
+#define VDD2_OPP2       0x2
+#define VDD2_OPP3       0x3
+
+#define MIN_VDD1_OPP    VDD1_OPP1
+#define MAX_VDD1_OPP    VDD1_OPP5
+#define MIN_VDD2_OPP    VDD2_OPP1
+#define MAX_VDD2_OPP    VDD2_OPP3
+
 #endif /* __ASM_ARCH_OMAP_3430SDP_H */