1/7 Nios: bugfixes

diff -purN -x CVS u-boot-20040130cvs/board/altera/common/flash.c u-boot-20040130cvs-nios_bugfixes/board/altera/common/flash.c
@@ -71,7 +71,6 @@ int flash_erase (flash_info_t * info, in
 	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
 	volatile CFG_FLASH_WORD_SIZE *addr2;
 	int prot, sect;
-	int any = 0;
 	unsigned oldpri;
 	ulong start;
 

@@ -94,6 +93,12 @@ int flash_erase (flash_info_t * info, in
 		printf ("\n");
 	}
 
+#ifdef DEBUG
+	for (sect = s_first; sect <= s_last; sect++) {
+		printf("- Erase: Sect: %i @ 0x%08x\n", sect,  info->start[sect]);
+	}
+#endif
+
 	/* NOTE: disabling interrupts on Nios can be very bad since it
 	 * also disables the LO_LIMIT exception. It's better here to
 	 * set the interrupt priority to 3 & restore it when we're done.

@@ -114,27 +119,26 @@ int flash_erase (flash_info_t * info, in
 			*addr = 0xaa;
 			*addr = 0x55;
 			*addr2 = 0x30;
-			any = 1;
-		}
-	}
-
-	/* Now just wait for 0xff & provide some user feedback while
-	 * we wait.
-	 */
-	if (any) {
-		addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
-		start = get_timer (0);
-		while (*addr2 != 0xff) {
-			udelay (1000 * 1000);
-			putc ('.');
-			if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
-				printf ("timeout\n");
-				return 1;
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait. Here we have to grant
+			 * timer interrupts. Otherwise get_timer() can't
+			 * work right. */
+			ipri(oldpri);
+			start = get_timer (0);
+			while (*addr2 != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
 			}
+			oldpri = ipri (3); /* disallow non important irqs again */
 		}
-		printf ("\n");
 	}
 
+	printf ("\n");
+
 	/* Restore interrupt priority */
 	ipri (oldpri);
 

diff -purN -x CVS u-boot-20040130cvs/board/altera/common/sevenseg.c u-boot-20040130cvs-nios_bugfixes/board/altera/common/sevenseg.c
@@ -44,7 +44,7 @@ static int sevenseg_init_done = 0;
 
 static inline void __sevenseg_set_masked (unsigned int mask, int value)
 {
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
 
 #ifdef	SEVENSEG_WRONLY	/* emulate read access */
 

@@ -97,7 +97,7 @@ static inline void __sevenseg_toggle_mas
 
 static inline void __sevenseg_set (unsigned int value)
 {
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
 
 #ifdef	SEVENSEG_WRONLY	/* emulate read access */
 

@@ -126,7 +126,7 @@ static inline void __sevenseg_set (unsig
 
 static inline void __sevenseg_init (void)
 {
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
 
 	__sevenseg_set(0);
 

diff -purN -x CVS u-boot-20040130cvs/board/altera/dk1c20/dk1c20.c u-boot-20040130cvs-nios_bugfixes/board/altera/dk1c20/dk1c20.c
@@ -33,8 +33,10 @@ void _default_hdlr (void)
 
 int board_early_init_f (void)
 {
+#if	defined(CONFIG_SEVENSEG)
 	/* init seven segment led display and switch off */
 	sevenseg_set(SEVENSEG_OFF);
+#endif
 	return 0;
 }
 

diff -purN -x CVS u-boot-20040130cvs/board/altera/dk1s10/dk1s10.c u-boot-20040130cvs-nios_bugfixes/board/altera/dk1s10/dk1s10.c
@@ -33,8 +33,10 @@ void _default_hdlr (void)
 
 int board_early_init_f (void)
 {
+#if	defined(CONFIG_SEVENSEG)
 	/* init seven segment led display and switch off */
 	sevenseg_set(SEVENSEG_OFF);
+#endif
 	return 0;
 }
 

diff -purN -x CVS u-boot-20040130cvs/include/configs/DK1C20.h u-boot-20040130cvs-nios_bugfixes/include/configs/DK1C20.h
@@ -647,8 +647,8 @@
  * ASMI is for Cyclone devices only and only works when the configuration
  * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details.
  *----------------------------------------------------------------------*/
-#define CONFIG_NIOS_ASMI			/* Enable ASMI		*/
-#define CFG_NIOS_ASMIBASE	0x00920b00	/* ASMI base address	*/
+#define CONFIG_NIOS_ASMI			   /* Enable ASMI	*/
+#define CFG_NIOS_ASMIBASE	CFG_NIOS_CPU_ASMI0 /* ASMI base address	*/
 
 /*------------------------------------------------------------------------
  * COMMANDS

diff -purN -x CVS u-boot-20040130cvs/include/configs/DK1S10.h u-boot-20040130cvs-nios_bugfixes/include/configs/DK1S10.h
@@ -243,11 +243,6 @@
 #define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
 #define	CFG_NIOS_CPU_IDE0	0x00920a00	/* IDE0		addr	*/
 
-/* active serial memory i/f */
-#define	CFG_NIOS_CPU_ASMI_NUMS	1		/* number of ASMI	*/
-#define	CFG_NIOS_CPU_ASMI0	0x00920b00	/* ASMI0	addr	*/
-#define	CFG_NIOS_CPU_ASMI0_IRQ	45		/*		IRQ	*/
-
 /* memory accessibility */
 #define	CFG_NIOS_CPU_SRAM_BASE	0x00800000	/* board SRAM	addr	*/
 #define	CFG_NIOS_CPU_SRAM_SIZE	(1024 * 1024)	/*  1 MB	size	*/