clk: tegra: Capitalization fixes

PATCH In review Thierry Reding 4 participants 6 messages Jun 3, 2020 – Jun 23, 2020

Subsystems (3)

Common clk Tegra architecture support Tegra clock driver

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Thierry Reding

author

2020-06-03 11:19 UTC #0 lore raw

PATCH 1/2 clk: tegra: Capitalization fixes

From: Thierry Reding <[email protected]>

HW, XUSB and PLL are abbreviations and should be all-uppercase.

Signed-off-by Thierry Reding <[email protected]>

---
 drivers/clk/tegra/clk-pll.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/clk/tegra/clk-pll.c +2 -2

index 0b212cf2e794..583d2ac61e9e 100644
@@ -1663,7 +1663,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
 	pll_writel(val, PLLE_SS_CTRL, pll);
 	udelay(1);
 
-	/* Enable hw control of xusb brick pll */
+	/* Enable HW control of XUSB brick PLL */
 	val = pll_readl_misc(pll);
 	val &= ~PLLE_MISC_IDDQ_SW_CTRL;
 	pll_writel_misc(val, pll);

@@ -1686,7 +1686,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
 	val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
 	pll_writel(val, XUSBIO_PLL_CFG0, pll);
 
-	/* Enable hw control of SATA pll */
+	/* Enable HW control of SATA PLL */
 	val = pll_readl(SATA_PLL_CFG0, pll);
 	val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
 	val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;

Signature · 1 line

2.24.1

Thierry Reding

author

2020-06-03 11:19 UTC #1 lore raw

PATCH 2/2 clk: tegra: Always program PLL_E when enabled

From: Thierry Reding <[email protected]>

Commit bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs") added checks to avoid enabling PLLs that have already been enabled by the bootloader. However, the PLL_E configuration inherited from the bootloader isn't necessarily the one that is needed for the kernel.

This can cause SATA to fail like this:

    [    5.310270] phy phy-sata.6: phy poweron failed --> -110
    [    5.315604] tegra-ahci 70027000.sata: failed to power on AHCI controller: -110
    [    5.323022] tegra-ahci: probe of 70027000.sata failed with error -110

Fix this by always programming the PLL_E. This ensures that any mis- configuration by the bootloader will be overwritten by the kernel.

Fixes bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs")

Reported-by LABBE Corentin <clabbe-rdvid1DuHRBWk0Htik3J/[email protected]>

Signed-off-by Thierry Reding <[email protected]>

---
 drivers/clk/tegra/clk-pll.c | 3 ---
 1 file changed, 3 deletions(-)

drivers/clk/tegra/clk-pll.c +0 -3

index 583d2ac61e9e..b2d39a66f0fa 100644
@@ -1601,9 +1601,6 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
 	unsigned long flags = 0;
 	unsigned long input_rate;
 
-	if (clk_pll_is_enabled(hw))
-		return 0;
-
 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 
 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))

Signature · 1 line

2.24.1

LABBE Corentin

Tested-by on v1 2/2

2020-06-03 13:13 UTC #2 lore raw

Re: [PATCH 2/2] clk: tegra: Always program PLL_E when enabled

Quoted 40 lines · Thierry Reding

From: Thierry Reding <[email protected]>
Commit bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs") added checks to avoid enabling PLLs that have already been enabled by the bootloader. However, the PLL_E configuration inherited from the bootloader isn't necessarily the one that is needed for the kernel.
This can cause SATA to fail like this:
    [    5.310270] phy phy-sata.6: phy poweron failed --> -110
    [    5.315604] tegra-ahci 70027000.sata: failed to power on AHCI controller: -110
    [    5.323022] tegra-ahci: probe of 70027000.sata failed with error -110
Fix this by always programming the PLL_E. This ensures that any mis- configuration by the bootloader will be overwritten by the kernel.
Fixes bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs")
Reported-by LABBE Corentin <[email protected]>
Signed-off-by Thierry Reding <[email protected]>
---
 drivers/clk/tegra/clk-pll.c | 3 ---
 1 file changed, 3 deletions(-)
drivers/clk/tegra/clk-pll.c +0 -3
index 583d2ac61e9e..b2d39a66f0fa 100644
@@ -1601,9 +1601,6 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
 	unsigned long flags = 0;
 	unsigned long input_rate;
 
-	if (clk_pll_is_enabled(hw))
-		return 0;
-
 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 
 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
Signature · 1 line
2.24.1

Tested-by Corentin Labbe <[email protected]>

Thanks

Dmitry Osipenko

Reviewed-by on v1 2/2

2020-06-03 14:04 UTC #3 lore raw

Re: [PATCH 2/2] clk: tegra: Always program PLL_E when enabled

In reply to Thierry Reding

03.06.2020 14:19, Thierry Reding пишет:

Quoted 29 lines

From: Thierry Reding <[email protected]>
Commit bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs") added checks to avoid enabling PLLs that have already been enabled by the bootloader. However, the PLL_E configuration inherited from the bootloader isn't necessarily the one that is needed for the kernel.
This can cause SATA to fail like this:
    [    5.310270] phy phy-sata.6: phy poweron failed --> -110
    [    5.315604] tegra-ahci 70027000.sata: failed to power on AHCI controller: -110
    [    5.323022] tegra-ahci: probe of 70027000.sata failed with error -110
Fix this by always programming the PLL_E. This ensures that any mis- configuration by the bootloader will be overwritten by the kernel.
Fixes bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs")
Reported-by LABBE Corentin <clabbe-rdvid1DuHRBWk0Htik3J/[email protected]>
Signed-off-by Thierry Reding <[email protected]>
---
 drivers/clk/tegra/clk-pll.c | 3 ---
 1 file changed, 3 deletions(-)
drivers/clk/tegra/clk-pll.c +0 -0
index 583d2ac61e9e..b2d39a66f0fa 100644

drivers/clk/tegra/clk-pll.c static int clk_plle_tegra114_enable(struct clk_hw *hw) · line 1606

Quoted 9 lines

drivers/clk/tegra/clk-pll.c +0 -3

@@ -1601,9 +1601,6 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
 	unsigned long flags = 0;
 	unsigned long input_rate;
 
-	if (clk_pll_is_enabled(hw))
-		return 0;
-
 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 
 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))

Reviewed-by Dmitry Osipenko <[email protected]>

Stephen Boyd

maintainer Acked-by on v1 2/2

2020-06-23 02:07 UTC #4 lore raw

Re: [PATCH 2/2] clk: tegra: Always program PLL_E when enabled

In reply to Thierry Reding

Quoting Thierry Reding (2020-06-03 04:19:23)

Quoted 13 lines

From: Thierry Reding <[email protected]>
Commit bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs") added checks to avoid enabling PLLs that have already been enabled by the bootloader. However, the PLL_E configuration inherited from the bootloader isn't necessarily the one that is needed for the kernel.
This can cause SATA to fail like this:
    [    5.310270] phy phy-sata.6: phy poweron failed --> -110
    [    5.315604] tegra-ahci 70027000.sata: failed to power on AHCI controller: -110
    [    5.323022] tegra-ahci: probe of 70027000.sata failed with error -110

Quoted 7 lines

Fix this by always programming the PLL_E. This ensures that any mis- configuration by the bootloader will be overwritten by the kernel.
Fixes bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs")
Reported-by LABBE Corentin <clabbe-rdvid1DuHRBWk0Htik3J/[email protected]>
Signed-off-by Thierry Reding <[email protected]>
---

Acked-by Stephen Boyd <[email protected]>

Stephen Boyd

maintainer Acked-by on v1 1/2

2020-06-23 02:07 UTC #5 lore raw

In reply to Thierry Reding

Quoting Thierry Reding (2020-06-03 04:19:22)

Quoted 6 lines

From: Thierry Reding <[email protected]>
HW, XUSB and PLL are abbreviations and should be all-uppercase.
Signed-off-by Thierry Reding <[email protected]>
---

Acked-by Stephen Boyd <[email protected]>