ARM:exynos5:power-domain: Save and restore CLK_TOP_SRC3 via clock framework.

Power domain clks are added to Gscaler and MFC pd nodes. These clocks are saved during power off.

Signed-off-by Prasanna Kumar <[email protected]>

---
 arch/arm/boot/dts/exynos5250.dtsi |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

arch/arm/boot/dts/exynos5250.dtsi +0 -0

index 6d0e87c..8043be3 100644

arch/arm/boot/dts/exynos5250.dtsi +0 -1

        };
 
        gsc_0:  gsc at 0x13e00000 {
--

1.7.5.4

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After Suspend-Resume operation, it is observed that CLK_TOP_SRC3 register gets modified if the G-Scaler/MFC devices are power gated.

The clock for G-Scaler gets set to XXTI which results in the device running very slow.This issue also seen for MFC.

To solve above issue, the existing clock framework of exynos5 is used to save and restore clocks while power gating instead of accessing CLK_SRC_TOP3 register directly.The clock names are read from DT file.

Please refer below URL to know the background of this issue.
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg14347.html.

Signed-off-by Prasanna Kumar <[email protected]>

---
 arch/arm/mach-exynos/pm_domains.c |  125 +++++++++++++++++++++++++++++++++++++
 1 files changed, 125 insertions(+), 0 deletions(-)

arch/arm/mach-exynos/pm_domains.c +5 -0

index 9f1351d..2f49de9 100644
@@ -21,9 +21,14 @@
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/sched.h>
+#include <linux/clk.h>
+#include <linux/list.h>
 
 #include <mach/regs-pmu.h>
 #include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/clock-clksrc.h>
+
 
 /*
  * Exynos specific wrapper around the generic power domain

@@ -33,7 +38,69 @@ struct exynos_pm_domain {
 	char const *name;
 	bool is_off;

arch/arm/mach-exynos/pm_domains.c +6 -0

+static int exynos_pdclk_save(struct exynos_pm_domain *epd)
+{
+	struct exynos_pd_clk *pdclk;
+	struct exynos_pd_clk *saved_pdclk;
+
+	list_for_each_entry(pdclk, &epd->list_pdclks, node) {

arch/arm/mach-exynos/pm_domains.c +23 -0

+			}
+			list_add_tail(&saved_pdclk->node,
+						&epd->saved_list_pdclks);
+		}
+	}
+	return 0;
+}
+
+static void exynos_pdclk_restore(struct exynos_pm_domain *epd)
+{
+	struct exynos_pd_clk *pdclk;
+	struct exynos_pd_clk *saved_pdclk;
+	struct list_head *p_clk;
+	struct list_head *p_saved_clk;
+	int ret;
+
+	p_saved_clk = epd->saved_list_pdclks.next;
+	p_clk = epd->list_pdclks.next;
+
+	for ( ; p_saved_clk != &epd->saved_list_pdclks &&
+		p_clk != &epd->list_pdclks;
+		p_clk = p_clk->next, p_saved_clk = p_saved_clk->next) {
+

arch/arm/mach-exynos/pm_domains.c +2 -0

+	}
+
 	pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
 	__raw_writel(pwr, base);
 

arch/arm/mach-exynos/pm_domains.c +15 -0

 	return 0;
 }
 

@@ -157,10 +236,48 @@ static struct notifier_block platform_nb = {
 	.notifier_call = exynos_pm_notifier_call,
 };
 
+static int exynos_read_pdclk_from_dt(struct device_node *dev_node,
+						struct exynos_pm_domain *pd)
+{
+	int i = 0;
+	const char *clk_name;
+	struct exynos_pd_clk *pd_clk;
+	int err = 0;
+
+	INIT_LIST_HEAD(&pd->list_pdclks);
+	INIT_LIST_HEAD(&pd->saved_list_pdclks);
+
+	for (i = 0; i < pd->pd_clks; i++) {
+		pd_clk = kzalloc(sizeof(struct exynos_pd_clk),
+							GFP_KERNEL);
+		if (!pd_clk) {

arch/arm/mach-exynos/pm_domains.c +16 -0

+			return PTR_ERR(pd_clk->clk);
+		}
+		list_add(&pd_clk->node, &pd->list_pdclks);
+	}
+	return 0;
+}
+
 static __init int exynos_pm_dt_parse_domains(void)
 {
 	struct platform_device *pdev;
 	struct device_node *np;
+	int err = 0;
 
 	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
 		struct exynos_pm_domain *pd;

@@ -182,6 +299,14 @@ static __init int exynos_pm_dt_parse_domains(void)
 		pd->pd.power_on = exynos_pd_power_on;
 		pd->pd.of_node = np;
 
+		pd->pd_clks = of_property_count_strings(np,
+						"samsung,exynos-pd-clks");
+		if (pd->pd_clks > 0) {
+			err = exynos_read_pdclk_from_dt(np, pd);
+			if (err)
+				return err;
+		}
+
 		platform_set_drvdata(pdev, pd);
 
 		on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;

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1.7.5.4


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After Suspend-Resume operation of exynos5, CLK_TOP_SRC3 register modified
while power gating G-scaler and MFC power domains.This is seen only after suspend and resume.

The solution to this problem is to save CLK_SRC_TOP3 register and restore it while powergating. But CLK_SRC_TOP3 register cannot accessed directly by power domain code.
Please refer below URL to know the background of this issue.
http://www.mail-archive.com/linux-samsung-
soc at vger.kernel.org/msg14347.html.

This patch set adds clock framework support for save and restore clock register (CLK_SRC_TOP3) for G-scaler and MFC power domains.

This patch set depends on
http://www.mail-archive.com/linux-samsung-
soc at vger.kernel.org/msg14648.html

Prasanna Kumar (3):
ARM: dts: exynos5: Add power domain clocks to pd node of Gscaler and
MFC
ARM:exynos5:dts: Bindings for clock definitions are added.
ARM: exynos5: Add clock save and restore operation(CLK_SRC_TOP3) using
clock framework.

 .../bindings/arm/exynos/power_domain.txt           |   14 ++
 arch/arm/boot/dts/exynos5250.dtsi                  |    2 +
 arch/arm/mach-exynos/pm_domains.c                  |  125
++++++++++++++++++++
 3 files changed, 141 insertions(+), 0 deletions(-)

--
1.7.5.4