PCI/PCIe cleanups and fixups for 8641
Subsystems (5)
cover PCI/PCIe cleanups and fixups for 8641
This is a set of patches queued for 2.6.23 that cleanup some of the PCI code for ppc32 and get PCIe working on 8641. Most of these patches have been seen in one form or another before on the list.
Also available at:
master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git for_paulus
- k
PATCH 1/15 Remove set_cfg_type for PCI indirect users that don't need it
The Freescale and Marvell PCI controllers dont require explicit setting for type 1 config cycles. They handle producing them by implicitly looking at the bus, devfn.
The TSI108 and 52xx don't use the generic PCI indirect code and thus don't bother with set_cfg_type.
--- arch/powerpc/platforms/52xx/mpc52xx_pci.c | 1 - arch/powerpc/platforms/82xx/mpc82xx_ads.c | 3 --- arch/powerpc/platforms/83xx/pci.c | 1 - arch/powerpc/platforms/85xx/pci.c | 1 - arch/powerpc/platforms/86xx/pci.c | 1 - arch/powerpc/sysdev/mv64x60_pci.c | 1 - arch/powerpc/sysdev/tsi108_pci.c | 1 - 7 files changed, 0 insertions(+), 9 deletions(-)
arch/powerpc/platforms/52xx/mpc52xx_pci.c +0 -1
@@ -390,7 +390,6 @@ mpc52xx_add_bridge(struct device_node *node)return -ENOMEM ; hose->arch_data = node; - hose->set_cfg_type =1 ; hose->first_busno = bus_range ? bus_range[0 ] :0 ; hose->last_busno = bus_range ? bus_range[1 ] :0xff ;
arch/powerpc/platforms/82xx/mpc82xx_ads.c +0 -3
@@ -548,14 +548,11 @@ static void __init mpc82xx_add_bridge(struct device_node *np)return ; hose->arch_data = np; - hose->set_cfg_type =1 ; hose->first_busno = bus_range ? bus_range[0 ] :0 ; hose->last_busno = bus_range ? bus_range[1 ] :0xff ; hose->bus_offset =0 ; - hose->set_cfg_type =1 ; -setup_indirect_pci (hose, r.start + offsetof(pci_cpm2_t , pci_cfg_addr), r.start + offsetof(pci_cpm2_t , pci_cfg_data));
arch/powerpc/platforms/83xx/pci.c +0 -1
@@ -70,7 +70,6 @@ int __init mpc83xx_add_bridge(struct device_node *dev)if (!hose)return -ENOMEM ; hose->arch_data = dev; - hose->set_cfg_type =1 ; hose->first_busno = bus_range ? bus_range[0 ] :0 ; hose->last_busno = bus_range ? bus_range[1 ] :0xff ;
arch/powerpc/platforms/85xx/pci.c +0 -1
@@ -61,7 +61,6 @@ int __init mpc85xx_add_bridge(struct device_node *dev)if (!hose)return -ENOMEM ; hose->arch_data = dev; - hose->set_cfg_type =1 ; hose->first_busno = bus_range ? bus_range[0 ] :0 ; hose->last_busno = bus_range ? bus_range[1 ] :0xff ;
arch/powerpc/platforms/86xx/pci.c +0 -1
@@ -172,7 +172,6 @@ int __init mpc86xx_add_bridge(struct device_node *dev)if (!hose)return -ENOMEM ; hose->arch_data = dev; - hose->set_cfg_type =1 ;/* last_busno = 0xfe cause by MPC8641 PCIE bug */ hose->first_busno = bus_range ? bus_range[0 ] :0x0 ;
arch/powerpc/sysdev/mv64x60_pci.c +0 -1
@@ -142,7 +142,6 @@ static int __init mv64x60_add_bridge(struct device_node *dev)return -ENOMEM ; hose->arch_data = dev; - hose->set_cfg_type =1 ; hose->first_busno = bus_range ? bus_range[0 ] :0 ; hose->last_busno = bus_range ? bus_range[1 ] :0xff ;
arch/powerpc/sysdev/tsi108_pci.c +0 -1
@@ -226,7 +226,6 @@ int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)return -ENOMEM ; } hose->arch_data = dev; - hose->set_cfg_type =1 ; hose->first_busno = bus_range ? bus_range[0 ] :0 ; hose->last_busno = bus_range ? bus_range[1 ] :0xff ;
Signature · 1 line
1.5.2.1
PATCH 2/15 52xx: Remove support for PCI bus_offset
The hose->bus_offset is only used for PCI config cycles and the 52xx PCI config code doesn't actually ever set bus_offset to a non-zero value.
--- arch/powerpc/platforms/52xx/mpc52xx_pci.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-)
arch/powerpc/platforms/52xx/mpc52xx_pci.c +4 -5
@@ -117,13 +117,13 @@ mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,out_be32 (hose->cfg_addr, (1 <<31 ) | - ((bus->number - hose->bus_offset) <<16 ) | + (bus->number <<16 ) | (devfn <<8 ) | (offset &0xfc ));mb ();#if defined(CONFIG_PPC_MPC5200_BUGFIX ) -if (bus->number != hose->bus_offset) { +if (bus->number) {/* workaround for the bug 435 of the MPC5200 (L25R); * Don't do 32 bits config access during type-1 cycles */ switch (len) {
@@ -174,13 +174,13 @@ mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,out_be32 (hose->cfg_addr, (1 <<31 ) | - ((bus->number - hose->bus_offset) <<16 ) | + (bus->number <<16 ) | (devfn <<8 ) | (offset &0xfc ));mb ();#if defined(CONFIG_PPC_MPC5200_BUGFIX ) -if (bus->number != hose->bus_offset) { +if (bus->number) {/* workaround for the bug 435 of the MPC5200 (L25R); * Don't do 32 bits config access during type-1 cycles */ switch (len) {
@@ -394,7 +394,6 @@ mpc52xx_add_bridge(struct device_node *node) hose->first_busno = bus_range ? bus_range[0 ] :0 ; hose->last_busno = bus_range ? bus_range[1 ] :0xff ; - hose->bus_offset =0 ; hose->ops = &mpc52xx_pci_ops; pci_regs =ioremap (rsrc.start, rsrc.end - rsrc.start +1 );
Signature · 1 line
1.5.2.1
PATCH 3/15 Pass the pci_controller into pci_exclude_device
There are times that we need to know which controller we are on to decide how to exclude devices properly. We now pass the pci_controller that we are going to use down to the pci_exclude_device function. This will greatly simplify being able to exclude the PHBs in multiple controller setups.
--- arch/powerpc/platforms/82xx/mpc82xx_ads.c | 3 +- arch/powerpc/platforms/83xx/mpc83xx.h | 4 +- arch/powerpc/platforms/83xx/pci.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_ads.c | 3 +- arch/powerpc/platforms/85xx/mpc85xx_cds.c | 3 +- arch/powerpc/platforms/86xx/mpc86xx.h | 3 +- arch/powerpc/platforms/86xx/pci.c | 2 +- arch/powerpc/platforms/embedded6xx/holly.c | 2 +- arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c | 3 +- arch/powerpc/sysdev/Makefile | 2 +- arch/powerpc/sysdev/fsl_pcie.c | 4 +- arch/powerpc/sysdev/indirect_pci.c | 8 +- arch/powerpc/sysdev/tsi108_pci.c | 6 +- arch/ppc/syslib/Makefile | 1 + arch/ppc/syslib/indirect_pci.c | 134 +++++++++++++++++++++ include/asm-powerpc/machdep.h | 2 +- 16 files changed, 163 insertions(+), 19 deletions(-) create mode 100644 arch/ppc/syslib/indirect_pci.c
arch/powerpc/platforms/82xx/mpc82xx_ads.c +2 -1
@@ -507,7 +507,8 @@ void m82xx_pci_init_irq(void)return ; } -static int m82xx_pci_exclude_device (u_char bus,u_char devfn) +static int m82xx_pci_exclude_device (struct pci_controller *hose, +u_char bus,u_char devfn) {if (bus ==0 &&PCI_SLOT (devfn) ==0 )return PCIBIOS_DEVICE_NOT_FOUND ;
arch/powerpc/platforms/83xx/mpc83xx.h +3 -1
@@ -3,6 +3,7 @@#include <linux/init.h> #include <linux/device.h> +#include <asm/pci-bridge.h> /* System Clock Control Register */ #define MPC83XX_SCCR_OFFS 0xA08
@@ -28,7 +29,8 @@*/ extern int mpc83xx_add_bridge (struct device_node *dev); -extern int mpc83xx_exclude_device (u_char bus,u_char devfn); +extern int mpc83xx_exclude_device (struct pci_controller *hose, +u_char bus,u_char devfn);extern void mpc83xx_restart (char *cmd);extern long mpc83xx_time_init (void );
arch/powerpc/platforms/83xx/pci.c +1 -1
@@ -35,7 +35,7 @@int mpc83xx_pci2_busno; -int mpc83xx_exclude_device (u_char bus,u_char devfn) +int mpc83xx_exclude_device (struct pci_controller *hose,u_char bus,u_char devfn) {if (bus ==0 &&PCI_SLOT (devfn) ==0 )return PCIBIOS_DEVICE_NOT_FOUND ;
arch/powerpc/platforms/85xx/mpc85xx_ads.c +2 -1
@@ -39,7 +39,8 @@#endif #ifdef CONFIG_PCI -static int mpc85xx_exclude_device (u_char bus,u_char devfn) +static int mpc85xx_exclude_device (struct pci_controller *hose, +u_char bus,u_char devfn) {if (bus ==0 &&PCI_SLOT (devfn) ==0 )return PCIBIOS_DEVICE_NOT_FOUND ;
arch/powerpc/platforms/85xx/mpc85xx_cds.c +2 -1
@@ -57,7 +57,8 @@ static volatile u8 *cadmus;extern int mpc85xx_pci2_busno; -static int mpc85xx_exclude_device (u_char bus,u_char devfn) +static int mpc85xx_exclude_device (struct pci_controller *hose, +u_char bus,u_char devfn) {if (bus ==0 &&PCI_SLOT (devfn) ==0 )return PCIBIOS_DEVICE_NOT_FOUND ;
arch/powerpc/platforms/86xx/mpc86xx.h +2 -1
@@ -17,7 +17,8 @@extern int mpc86xx_add_bridge (struct device_node *dev); -extern int mpc86xx_exclude_device (u_char bus,u_char devfn); +extern int mpc86xx_exclude_device (struct pci_controller *hose, +u_char bus,u_char devfn);extern void setup_indirect_pcie (struct pci_controller *hose,u32 cfg_addr,u32 cfg_data);
arch/powerpc/platforms/86xx/pci.c +1 -1
@@ -140,7 +140,7 @@ mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)early_write_config_dword (hose,0 ,0 ,PCI_PRIMARY_BUS , temps); } -int mpc86xx_exclude_device (u_char bus,u_char devfn) +int mpc86xx_exclude_device (struct pci_controller *hose,u_char bus,u_char devfn) {if (bus ==0 &&PCI_SLOT (devfn) ==0 )return PCIBIOS_DEVICE_NOT_FOUND ;
arch/powerpc/platforms/embedded6xx/holly.c +1 -1
@@ -45,7 +45,7 @@#define HOLLY_PCI_CFG_PHYS 0x7c000000 -int holly_exclude_device (u_char bus,u_char devfn) +int holly_exclude_device (struct pci_controller *hose,u_char bus,u_char devfn) {if (bus ==0 &&PCI_SLOT (devfn) ==0 )return PCIBIOS_DEVICE_NOT_FOUND ;
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c +2 -1
@@ -56,7 +56,8 @@extern void _nmask_and_or_msr (unsigned long nmask,unsigned long or_val); -int mpc7448_hpc2_exclude_device (u_char bus,u_char devfn) +int mpc7448_hpc2_exclude_device (struct pci_controller *hose, +u_char bus,u_char devfn) {if (bus ==0 &&PCI_SLOT (devfn) ==0 )return PCIBIOS_DEVICE_NOT_FOUND ;
arch/powerpc/sysdev/Makefile +1 -1
@@ -5,7 +5,6 @@ endif mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) -obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o obj-$(CONFIG_PPC_MPC106) += grackle.o obj-$(CONFIG_PPC_DCR) += dcr.o obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o
@@ -23,6 +22,7 @@ obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o obj-$(CONFIG_PM) += timer.o ifeq ($(CONFIG_PPC_MERGE),y) +obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o obj-$(CONFIG_PPC_I8259) += i8259.o obj-$(CONFIG_PPC_83xx) += ipic.o obj-$(CONFIG_4xx) += uic.o
arch/powerpc/sysdev/fsl_pcie.c +2 -2
@@ -39,7 +39,7 @@ indirect_read_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,u32 temp;if (ppc_md.pci_exclude_device) -if (ppc_md.pci_exclude_device (bus->number, devfn)) +if (ppc_md.pci_exclude_device (hose, bus->number, devfn))return PCIBIOS_DEVICE_NOT_FOUND ;/* Possible artifact of CDCpp50937 needs further investigation */
@@ -90,7 +90,7 @@ indirect_write_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,u32 temp;if (ppc_md.pci_exclude_device) -if (ppc_md.pci_exclude_device (bus->number, devfn)) +if (ppc_md.pci_exclude_device (hose, bus->number, devfn))return PCIBIOS_DEVICE_NOT_FOUND ;/* Possible artifact of CDCpp50937 needs further investigation */
arch/powerpc/sysdev/indirect_pci.c +4 -4
@@ -35,14 +35,14 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,u8 cfg_type =0 ;if (ppc_md.pci_exclude_device) -if (ppc_md.pci_exclude_device (bus->number, devfn)) +if (ppc_md.pci_exclude_device (hose, bus->number, devfn))return PCIBIOS_DEVICE_NOT_FOUND ;if (hose->set_cfg_type)if (bus->number != hose->first_busno) cfg_type =1 ; -PCI_CFG_OUT (hose->cfg_addr, +PCI_CFG_OUT (hose->cfg_addr, (0x80000000 | ((bus->number - hose->bus_offset) <<16 ) | (devfn <<8 ) | ((offset &0xfc ) | cfg_type)));
@@ -74,14 +74,14 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,u8 cfg_type =0 ;if (ppc_md.pci_exclude_device) -if (ppc_md.pci_exclude_device (bus->number, devfn)) +if (ppc_md.pci_exclude_device (hose, bus->number, devfn))return PCIBIOS_DEVICE_NOT_FOUND ;if (hose->set_cfg_type)if (bus->number != hose->first_busno) cfg_type =1 ; -PCI_CFG_OUT (hose->cfg_addr, +PCI_CFG_OUT (hose->cfg_addr, (0x80000000 | ((bus->number - hose->bus_offset) <<16 ) | (devfn <<8 ) | ((offset &0xfc ) | cfg_type)));
arch/powerpc/sysdev/tsi108_pci.c +4 -2
@@ -64,9 +64,10 @@ tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc, int offset, int len, u32 val) { volatile unsigned char *cfg_addr; +struct pci_controller *hose = bus->sysdata;if (ppc_md.pci_exclude_device) -if (ppc_md.pci_exclude_device (bus->number, devfunc)) +if (ppc_md.pci_exclude_device (hose, bus->number, devfunc))return PCIBIOS_DEVICE_NOT_FOUND ; cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
@@ -149,10 +150,11 @@ tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 * val) {volatile unsigned char *cfg_addr; +struct pci_controller *hose = bus->sysdata;u32 temp;if (ppc_md.pci_exclude_device) -if (ppc_md.pci_exclude_device (bus->number, devfn)) +if (ppc_md.pci_exclude_device (hose, bus->number, devfn))return PCIBIOS_DEVICE_NOT_FOUND ; cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
arch/ppc/syslib/Makefile +1 -0
@@ -7,6 +7,7 @@ CFLAGS_btext.o += -fPIC wdt-mpc8xx-$(CONFIG_8xx_WDT) += m8xx_wdt.o +obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram.o obj-$(CONFIG_PPC_OCP) += ocp.o obj-$(CONFIG_IBM_OCP) += ibm_ocp.o
arch/ppc/syslib/indirect_pci.c new file +134 -0
134 lines not on this page · raw message
include/asm-powerpc/machdep.h +1 -1
@@ -218,7 +218,7 @@ struct machdep_calls {int (*pcibios_enable_device_hook)(struct pci_dev *,int initial);/* Called in indirect_* to avoid touching devices */ -int (*pci_exclude_device)(unsigned char ,unsigned char ); +int (*pci_exclude_device)(struct pci_controller *,unsigned char ,unsigned char );/* Called at then very end of pcibios_init() */ void (*pcibios_after_init)(void );
Signature · 1 line
1.5.2.1
PATCH 4/15 Remove hack to determine the 2nd PHBs bus number
Now that we have the pci_controller in the exclude function we can easy figure out if the bus number is the PHB or not. The old style of using a variable setup at init time was actually broken and would only work in specific cases.
--- arch/powerpc/platforms/83xx/pci.c | 8 +------- arch/powerpc/platforms/85xx/mpc85xx_cds.c | 7 +------ arch/powerpc/platforms/85xx/pci.c | 3 --- 3 files changed, 2 insertions(+), 16 deletions(-)
arch/powerpc/platforms/83xx/pci.c +1 -7
@@ -33,15 +33,10 @@ #define DBG(x...)#endif -int mpc83xx_pci2_busno; -int mpc83xx_exclude_device (struct pci_controller *hose,u_char bus,u_char devfn) { -if (bus ==0 &&PCI_SLOT (devfn) ==0 ) +if ((bus == hose->first_busno) &&PCI_SLOT (devfn) ==0 )return PCIBIOS_DEVICE_NOT_FOUND ; -if (mpc83xx_pci2_busno) -if (bus == (mpc83xx_pci2_busno ) &&PCI_SLOT (devfn) ==0 ) -return PCIBIOS_DEVICE_NOT_FOUND ;return PCIBIOS_SUCCESSFUL ; }
@@ -86,7 +81,6 @@ int __init mpc83xx_add_bridge(struct device_node *dev)setup_indirect_pci (hose, immr +0x8380 , immr +0x8384 ); primary =0 ; hose->bus_offset = hose->first_busno; - mpc83xx_pci2_busno = hose->first_busno; } printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. "
arch/powerpc/platforms/85xx/mpc85xx_cds.c +1 -6
@@ -55,16 +55,11 @@ static volatile u8 *cadmus;#define ARCADIA_HOST_BRIDGE_IDSEL 17#define ARCADIA_2ND_BRIDGE_IDSEL 3 -extern int mpc85xx_pci2_busno; -static int mpc85xx_exclude_device (struct pci_controller *hose,u_char bus,u_char devfn) { -if (bus ==0 &&PCI_SLOT (devfn) ==0 ) +if ((bus == hose->first_busno) &&PCI_SLOT (devfn) ==0 )return PCIBIOS_DEVICE_NOT_FOUND ; -if (mpc85xx_pci2_busno) -if (bus == (mpc85xx_pci2_busno ) &&PCI_SLOT (devfn) ==0 ) -return PCIBIOS_DEVICE_NOT_FOUND ;/* We explicitly do not go past the Tundra 320 Bridge */ if ((bus ==1 ) && (PCI_SLOT (devfn) ==ARCADIA_2ND_BRIDGE_IDSEL ))return PCIBIOS_DEVICE_NOT_FOUND ;
arch/powerpc/platforms/85xx/pci.c +0 -3
@@ -33,8 +33,6 @@ #define DBG(x...)#endif -int mpc85xx_pci2_busno =0 ; -#ifdef CONFIG_PCI int __init mpc85xx_add_bridge (struct device_node *dev) {
@@ -74,7 +72,6 @@ int __init mpc85xx_add_bridge(struct device_node *dev)setup_indirect_pci (hose, immr +0x9000 , immr +0x9004 ); primary =0 ; hose->bus_offset = hose->first_busno; - mpc85xx_pci2_busno = hose->first_busno; } printk(KERN_INFO "Found MPC85xx PCI host bridge at 0x%016llx. "
Signature · 1 line
1.5.2.1
PATCH 5/15 Remove bus_offset in places its not really used
The user of the fsl_pcie code doesn't set bus_offset and 82xx doesn't require it either. Remove the places in the code that reference it so we can remove it all together.
--- arch/powerpc/platforms/82xx/mpc82xx_ads.c | 1 - arch/powerpc/sysdev/fsl_pcie.c | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-)
arch/powerpc/platforms/82xx/mpc82xx_ads.c +0 -1
@@ -552,7 +552,6 @@ static void __init mpc82xx_add_bridge(struct device_node *np) hose->first_busno = bus_range ? bus_range[0 ] :0 ; hose->last_busno = bus_range ? bus_range[1 ] :0xff ; - hose->bus_offset =0 ; setup_indirect_pci(hose, r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
arch/powerpc/sysdev/fsl_pcie.c +4 -4
@@ -50,12 +50,12 @@ indirect_read_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,if (bus->number ==0xff ) {PCI_CFG_OUT (hose->cfg_addr, (0x80000000 | ((offset &0xf00 ) <<16 ) | - ((bus->number - hose->bus_offset) <<16 ) + (bus->number<<16 ) | (devfn <<8 ) | ((offset &0xfc ) ))); }else {PCI_CFG_OUT (hose->cfg_addr, (0x80000001 | ((offset &0xf00 ) <<16 ) | - ((bus->number - hose->bus_offset) <<16 ) + (bus->number<<16 ) | (devfn <<8 ) | ((offset &0xfc ) ))); }
@@ -101,12 +101,12 @@ indirect_write_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,if (bus->number ==0xff ) {PCI_CFG_OUT (hose->cfg_addr, (0x80000000 | ((offset &0xf00 ) <<16 ) | - ((bus->number - hose->bus_offset) <<16 ) + (bus->number <<16 ) | (devfn <<8 ) | ((offset &0xfc ) ))); }else {PCI_CFG_OUT (hose->cfg_addr, (0x80000001 | ((offset &0xf00 ) <<16 ) | - ((bus->number - hose->bus_offset) <<16 ) + (bus->number <<16 ) | (devfn <<8 ) | ((offset &0xfc ) ))); }
Signature · 1 line
1.5.2.1
PATCH 6/15 Added self_busno to indicate which bus number the PHB is
Added self_busno to pci_controller and indirect PCI ops to be set by board code to indicate which bus number to use when talking to the PHB. By default we use zero since the majority of controllers that have implicit mechanisms to talk to the PHBs use a bus number of zero.
--- arch/powerpc/sysdev/indirect_pci.c | 12 ++++++++++-- include/asm-ppc/pci-bridge.h | 1 + 2 files changed, 11 insertions(+), 2 deletions(-)
arch/powerpc/sysdev/indirect_pci.c +10 -2
@@ -33,6 +33,7 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,struct pci_controller *hose = bus->sysdata;volatile void __iomem *cfg_data;u8 cfg_type =0 ; +u32 bus_no;if (ppc_md.pci_exclude_device)if (ppc_md.pci_exclude_device (hose, bus->number, devfn))
@@ -42,8 +43,11 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,if (bus->number != hose->first_busno) cfg_type =1 ; + bus_no = (bus->number == hose->first_busno) ? + hose->self_busno : bus->number - hose->bus_offset; +PCI_CFG_OUT (hose->cfg_addr, - (0x80000000 | ((bus->number - hose->bus_offset) <<16 ) + (0x80000000 | (bus_no <<16 ) | (devfn <<8 ) | ((offset &0xfc ) | cfg_type)));/*
@@ -72,6 +76,7 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,struct pci_controller *hose = bus->sysdata;volatile void __iomem *cfg_data;u8 cfg_type =0 ; +u32 bus_no;if (ppc_md.pci_exclude_device)if (ppc_md.pci_exclude_device (hose, bus->number, devfn))
@@ -81,8 +86,11 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,if (bus->number != hose->first_busno) cfg_type =1 ; + bus_no = (bus->number == hose->first_busno) ? + hose->self_busno : bus->number - hose->bus_offset; +PCI_CFG_OUT (hose->cfg_addr, - (0x80000000 | ((bus->number - hose->bus_offset) <<16 ) + (0x80000000 | (bus_no <<16 ) | (devfn <<8 ) | ((offset &0xfc ) | cfg_type)));/*
include/asm-ppc/pci-bridge.h +1 -0
@@ -47,6 +47,7 @@ struct pci_controller {int first_busno;int last_busno; +int self_busno;int bus_offset;void __iomem *io_base_virt;
Signature · 1 line
1.5.2.1
PATCH 7/15 Removed remnants of bus_offset
Removed the remants of bus_offset and use self_busno in the mv64x60 case and use pci_assign_all_buses on 83xx/85xx.
83xx/85xx have multiple PHBs and the firmwares on these devices tend not to handle topologies with P2P bridges well so we let Linux just reassign the bus numbers to match.
--- arch/powerpc/platforms/83xx/pci.c | 2 +- arch/powerpc/platforms/85xx/pci.c | 2 +- arch/powerpc/sysdev/indirect_pci.c | 4 ++-- arch/powerpc/sysdev/mv64x60_pci.c | 2 +- include/asm-ppc/pci-bridge.h | 1 + 5 files changed, 6 insertions(+), 5 deletions(-)
arch/powerpc/platforms/83xx/pci.c +1 -1
@@ -61,6 +61,7 @@ int __init mpc83xx_add_bridge(struct device_node *dev) " bus 0\n", dev->full_name); } + pci_assign_all_buses =1 ; hose =pcibios_alloc_controller ();if (!hose)return -ENOMEM ;
@@ -80,7 +81,6 @@ int __init mpc83xx_add_bridge(struct device_node *dev)if ((rsrc.start &0xfffff ) ==0x8600 ) {setup_indirect_pci (hose, immr +0x8380 , immr +0x8384 ); primary =0 ; - hose->bus_offset = hose->first_busno; } printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. "
arch/powerpc/platforms/85xx/pci.c +1 -1
@@ -55,6 +55,7 @@ int __init mpc85xx_add_bridge(struct device_node *dev) " bus 0\n", dev->full_name); } + pci_assign_all_buses =1 ; hose =pcibios_alloc_controller ();if (!hose)return -ENOMEM ;
@@ -71,7 +72,6 @@ int __init mpc85xx_add_bridge(struct device_node *dev)if ((rsrc.start &0xfffff ) ==0x9000 ) {setup_indirect_pci (hose, immr +0x9000 , immr +0x9004 ); primary =0 ; - hose->bus_offset = hose->first_busno; } printk(KERN_INFO "Found MPC85xx PCI host bridge at 0x%016llx. "
arch/powerpc/sysdev/indirect_pci.c +2 -2
@@ -44,7 +44,7 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, cfg_type =1 ; bus_no = (bus->number == hose->first_busno) ? - hose->self_busno : bus->number - hose->bus_offset; + hose->self_busno : bus->number; PCI_CFG_OUT(hose->cfg_addr, (0x80000000 | (bus_no << 16)
@@ -87,7 +87,7 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, cfg_type =1 ; bus_no = (bus->number == hose->first_busno) ? - hose->self_busno : bus->number - hose->bus_offset; + hose->self_busno : bus->number; PCI_CFG_OUT(hose->cfg_addr, (0x80000000 | (bus_no << 16)
arch/powerpc/sysdev/mv64x60_pci.c +1 -1
@@ -147,7 +147,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev) hose->last_busno = bus_range ? bus_range[1 ] :0xff ;setup_indirect_pci (hose, rsrc.start, rsrc.start +4 ); - hose->bus_offset = hose->first_busno; + hose->self_busno = hose->first_busno; printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. " "Firmware bus number: %d->%d\n",
include/asm-ppc/pci-bridge.h +1 -0
@@ -48,6 +48,7 @@ struct pci_controller {int first_busno;int last_busno;int self_busno; +/* bus_offset is only used by ARCH=ppc */ int bus_offset;void __iomem *io_base_virt;
Signature · 1 line
1.5.2.1
PATCH 8/15 Remove PCI-e errata for MPC8641 silicon ver 1.0
From: Zhang Wei <[email protected]>
Remove errata for PCI-e support of Rev 1.0 of MPC8641 since its considered obselete and is not production level silicon from Freescale.
--- arch/powerpc/Kconfig | 4 - arch/powerpc/boot/dts/mpc8641_hpcn.dts | 2 +- arch/powerpc/platforms/86xx/mpc86xx.h | 6 - arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 2 - arch/powerpc/platforms/86xx/pci.c | 18 +--- arch/powerpc/platforms/Kconfig | 1 - arch/powerpc/sysdev/Makefile | 1 - arch/powerpc/sysdev/fsl_pcie.c | 171 ---------------------------- 8 files changed, 3 insertions(+), 202 deletions(-) delete mode 100644 arch/powerpc/sysdev/fsl_pcie.c
arch/powerpc/Kconfig +0 -4
@@ -424,10 +424,6 @@ config SBUS config FSL_SOC bool -config FSL_PCIE - bool - depends on PPC_86xx - # Yes MCA RS/6000s exist but Linux-PPC does not currently support any config MCA bool
arch/powerpc/boot/dts/mpc8641_hpcn.dts +1 -1
@@ -186,7 +186,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8000 1000>; - bus-range = <0 fe>; + bus-range = <0 ff>; ranges = <02000000 0 80000000 80000000 0 20000000 01000000 0 00000000 e2000000 0 00100000>; clock-frequency = <1fca055>;
arch/powerpc/platforms/86xx/mpc86xx.h +0 -6
@@ -20,12 +20,6 @@ extern int mpc86xx_add_bridge(struct device_node *dev);extern int mpc86xx_exclude_device (struct pci_controller *hose,u_char bus,u_char devfn); -extern void setup_indirect_pcie (struct pci_controller *hose, -u32 cfg_addr,u32 cfg_data); -extern void setup_indirect_pcie_nomap (struct pci_controller *hose, -void __iomem *cfg_addr, -void __iomem *cfg_data); -extern void __init mpc86xx_smp_init (void );#endif /* __MPC86XX_H__ */
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c +0 -2
@@ -358,8 +358,6 @@ mpc86xx_hpcn_setup_arch(void)#ifdef CONFIG_PCI for (np =NULL ; (np =of_find_node_by_type (np,"pci" )) !=NULL ;)mpc86xx_add_bridge (np); - - ppc_md.pci_exclude_device = mpc86xx_exclude_device;#endif printk ("MPC86xx HPCN board from Freescale Semiconductor\n" );
arch/powerpc/platforms/86xx/pci.c +2 -16
@@ -133,19 +133,6 @@ mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)early_write_config_word (hose,0 ,0 ,PCI_COMMAND , cmd);early_write_config_byte (hose,0 ,0 ,PCI_LATENCY_TIMER ,0x80 ); - -/* PCIE Bus, Fix the MPC8641D host bridge's location to bus 0xFF. */ -early_read_config_dword (hose,0 ,0 ,PCI_PRIMARY_BUS , &temps); - temps = (temps &0xff000000 ) | (0xff ) | (0x0 <<8 ) | (0xfe <<16 ); -early_write_config_dword (hose,0 ,0 ,PCI_PRIMARY_BUS , temps); -} - -int mpc86xx_exclude_device (struct pci_controller *hose,u_char bus,u_char devfn) -{ -if (bus ==0 &&PCI_SLOT (devfn) ==0 ) -return PCIBIOS_DEVICE_NOT_FOUND ; - -return PCIBIOS_SUCCESSFUL ; }int __init mpc86xx_add_bridge (struct device_node *dev)
@@ -173,11 +160,10 @@ int __init mpc86xx_add_bridge(struct device_node *dev)return -ENOMEM ; hose->arch_data = dev; -/* last_busno = 0xfe cause by MPC8641 PCIE bug */ hose->first_busno = bus_range ? bus_range[0 ] :0x0 ; - hose->last_busno = bus_range ? bus_range[1 ] :0xfe ; + hose->last_busno = bus_range ? bus_range[1 ] :0xff ; -setup_indirect_pcie (hose, rsrc.start, rsrc.start +0x4 ); +setup_indirect_pci (hose, rsrc.start, rsrc.start +0x4 );/* Setup the PCIE host controller. */ mpc86xx_setup_pcie (hose, rsrc.start, rsrc.end - rsrc.start +1 );
arch/powerpc/platforms/Kconfig +0 -1
@@ -31,7 +31,6 @@ config PPC_86xx bool "Freescale 86xx" depends on 6xx select FSL_SOC - select FSL_PCIE select ALTIVEC help The Freescale E600 SoCs have 74xx cores.
arch/powerpc/sysdev/Makefile +0 -1
@@ -12,7 +12,6 @@ obj-$(CONFIG_PPC_PMI) += pmi.o obj-$(CONFIG_U3_DART) += dart_iommu.o obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o obj-$(CONFIG_FSL_SOC) += fsl_soc.o -obj-$(CONFIG_FSL_PCIE) += fsl_pcie.o obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
arch/powerpc/sysdev/fsl_pcie.c deleted +0 -171
171 lines not on this page · raw message
Signature · 1 line
1.5.2.1
PATCH 9/15 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
From: Wade Farnsworth <[email protected]>
This adds device nodes for the PCI bridges as well as the ISA devices on the newer revision MPC8641HPCN. It also adds the PCI ranges to the soc node so that address translation for the ISA devices works properly.
--- arch/powerpc/boot/dts/mpc8641_hpcn.dts | 97 +++++++++++++++++++++++++++---- 1 files changed, 84 insertions(+), 13 deletions(-)
arch/powerpc/boot/dts/mpc8641_hpcn.dts +84 -13
@@ -56,8 +56,12 @@ #size-cells = <1>; #interrupt-cells = <2>; device_type = "soc"; - ranges = <0 f8000000 00100000>; - reg = <f8000000 00100000>; // CCSRBAR 1M + ranges = <00001000 f8001000 000ff000 + 80000000 80000000 20000000 + e2000000 e2000000 00100000 + a0000000 a0000000 20000000 + e3000000 e3000000 00100000>; + reg = <f8000000 00001000>; // CCSRBAR bus-frequency = <0>; i2c@3000 {
@@ -285,17 +289,84 @@ f800 0 0 3 &i8259 0 0 f800 0 0 4 &i8259 0 0 >; - i8259: i8259@4d0 { - clock-frequency = <0>; - interrupt-controller; - device_type = "interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - big-endian; - interrupts = <49 2>; - interrupt-parent = <&mpic>; + uli1575@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + + pci_bridge@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + + isa@1e { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = <f000 0 0 0 0>; + ranges = <1 0 01000000 0 0 + 00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + reg = <1 20 2 + 1 a0 2 + 1 4d0 2>; + clock-frequency = <0>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + built-in; + compatible = "chrp,iic"; + interrupts = <49 2>; + interrupt-parent = + <&mpic>; + }; + + i8042@60 { + #size-cells = <0>; + #address-cells = <1>; + reg = <1 60 1 1 64 1>; + interrupts = <1 3 c 3>; + interrupt-parent = + <&i8259>; + + keyboard@0 { + reg = <0>; + compatible = "pnpPNP,303"; + }; + + mouse@1 { + reg = <1>; + compatible = "pnpPNP,f03"; + }; + }; + + rtc@70 { + compatible = + "pnpPNP,b00"; + reg = <1 70 2>; + }; + + gpio@400 { + reg = <1 400 80>; + }; + }; + }; }; };
Signature · 1 line
1.5.2.1
PATCH 10/15 Added indirect_type to handle variants of PCI ops
The generic PCI config ops indirect support for ppc32 covers only two cases (implicit vs explicit) type 0/1 config cycles via set_cfg_type. Added a indirect_type bit mask to handle other variants.
Added support for PCI-e extended registers and moved the cfg_type handling into the bit mask for ARCH=powerpc. We can also use this to handle indirect quirks.
--- arch/powerpc/sysdev/indirect_pci.c | 22 ++++++++++++++++------ include/asm-ppc/pci-bridge.h | 10 ++++++++++ 2 files changed, 26 insertions(+), 6 deletions(-)
arch/powerpc/sysdev/indirect_pci.c +16 -6
@@ -33,22 +33,27 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,struct pci_controller *hose = bus->sysdata;volatile void __iomem *cfg_data;u8 cfg_type =0 ; -u32 bus_no; +u32 bus_no, reg;if (ppc_md.pci_exclude_device)if (ppc_md.pci_exclude_device (hose, bus->number, devfn))return PCIBIOS_DEVICE_NOT_FOUND ; -if (hose->set_cfg_type) +if (hose->indirect_type &PPC_INDIRECT_TYPE_SET_CFG_TYPE )if (bus->number != hose->first_busno) cfg_type =1 ; bus_no = (bus->number == hose->first_busno) ? hose->self_busno : bus->number; +if (hose->indirect_type &PPC_INDIRECT_TYPE_EXT_REG ) + reg = ((offset &0xf00 ) <<16 ) | (offset &0xfc ); +else + reg = offset &0xfc ; +PCI_CFG_OUT (hose->cfg_addr, (0x80000000 | (bus_no <<16 ) - | (devfn <<8 ) | ((offset &0xfc ) | cfg_type))); + | (devfn <<8 ) | reg | cfg_type));/* * Note: the caller has already checked that offset is
@@ -76,22 +81,27 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,struct pci_controller *hose = bus->sysdata;volatile void __iomem *cfg_data;u8 cfg_type =0 ; -u32 bus_no; +u32 bus_no, reg;if (ppc_md.pci_exclude_device)if (ppc_md.pci_exclude_device (hose, bus->number, devfn))return PCIBIOS_DEVICE_NOT_FOUND ; -if (hose->set_cfg_type) +if (hose->indirect_type &PPC_INDIRECT_TYPE_SET_CFG_TYPE )if (bus->number != hose->first_busno) cfg_type =1 ; bus_no = (bus->number == hose->first_busno) ? hose->self_busno : bus->number; +if (hose->indirect_type &PPC_INDIRECT_TYPE_EXT_REG ) + reg = ((offset &0xf00 ) <<16 ) | (offset &0xfc ); +else + reg = offset &0xfc ; +PCI_CFG_OUT (hose->cfg_addr, (0x80000000 | (bus_no <<16 ) - | (devfn <<8 ) | ((offset &0xfc ) | cfg_type))); + | (devfn <<8 ) | reg | cfg_type));/* * Note: the caller has already checked that offset is
include/asm-ppc/pci-bridge.h +10 -0
@@ -65,9 +65,19 @@ struct pci_controller {/* * If set, indirect method will set the cfg_type bit as * needed to generate type 1 configuration transactions. +* use only on ARCH=ppc */ int set_cfg_type; +/* +* Used for variants of PCI indirect handling and possible quirks: +* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 +* EXT_REG - provides access to PCI-e extended registers +*/ +#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) +#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) +u32 indirect_type; +/* Currently, we limit ourselves to 1 IO range and 3 mem * ranges since the common pci_bus structure can't handle more */
Signature · 1 line
1.5.2.1
PATCH 11/15 86xx: Avoid system halt if link training isn't at least L0.
From: Zhang Wei <[email protected]>
We check the Link Training and State Status register to make sure we are at least at the L0 state.
--- arch/powerpc/platforms/86xx/pci.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-)
arch/powerpc/platforms/86xx/pci.c +10 -1
@@ -122,7 +122,6 @@ static void __init mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size) { u16 cmd; -unsigned int temps;DBG ("PCIE host controller register offset 0x%08x, size 0x%08x.\n" , pcie_offset, pcie_size);
@@ -135,6 +134,9 @@ mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)early_write_config_byte (hose,0 ,0 ,PCI_LATENCY_TIMER ,0x80 ); } +#define PCIE_LTSSM 0x404/* PCIe Link Training and Status */ +#define PCIE_LTSSM_L0 0x16/* L0 state */ +int __init mpc86xx_add_bridge (struct device_node *dev) {int len;
@@ -143,6 +145,7 @@ int __init mpc86xx_add_bridge(struct device_node *dev)const int *bus_range;int has_address =0 ;int primary =0 ; +u16 val;DBG ("Adding PCIE host bridge %s\n" , dev->full_name);
@@ -159,12 +162,18 @@ int __init mpc86xx_add_bridge(struct device_node *dev)if (!hose)return -ENOMEM ; hose->arch_data = dev; + hose->indirect_type =PPC_INDIRECT_TYPE_EXT_REG ; hose->first_busno = bus_range ? bus_range[0 ] :0x0 ; hose->last_busno = bus_range ? bus_range[1 ] :0xff ;setup_indirect_pci (hose, rsrc.start, rsrc.start +0x4 ); +/* Probe the hose link training status */ +early_read_config_word (hose,0 ,0 ,PCIE_LTSSM , &val); +if (val <PCIE_LTSSM_L0 ) +return -ENXIO ; +/* Setup the PCIE host controller. */ mpc86xx_setup_pcie (hose, rsrc.start, rsrc.end - rsrc.start +1 );
Signature · 1 line
1.5.2.1
PATCH 12/15 86xx: Workaround PCI_PRIMARY_BUS usage
The Freescale PCI-e controllers have an issue in that they use the PCI_PRIMARY_BUS register in the virtual P2P bridge to determine which bus number to match on when generating a type 0 config cycle. The issue is if we are renumbering bus numbers to match Linux we will try setting the PCI_PRIMARY_BUS and will not know which bus number to use for generating type 0 config cycles. We surpress writing the register in the P2P bridge and always keep it at zero.
In the future when proper PCI domain support is working we should be able to remove this.
--- arch/powerpc/platforms/86xx/pci.c | 4 +++- arch/powerpc/sysdev/indirect_pci.c | 6 ++++++ include/asm-ppc/pci-bridge.h | 5 +++++ 3 files changed, 14 insertions(+), 1 deletions(-)
arch/powerpc/platforms/86xx/pci.c +3 -1
@@ -158,11 +158,13 @@ int __init mpc86xx_add_bridge(struct device_node *dev)printk (KERN_WARNING "Can't get bus-range for %s, assume" " bus 0\n" , dev->full_name); + pci_assign_all_buses =1 ; hose =pcibios_alloc_controller ();if (!hose)return -ENOMEM ; hose->arch_data = dev; - hose->indirect_type =PPC_INDIRECT_TYPE_EXT_REG ; + hose->indirect_type =PPC_INDIRECT_TYPE_EXT_REG | +PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS ; hose->first_busno = bus_range ? bus_range[0 ] :0x0 ; hose->last_busno = bus_range ? bus_range[1 ] :0xff ;
arch/powerpc/sysdev/indirect_pci.c +6 -0
@@ -103,6 +103,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, (0x80000000 | (bus_no <<16 ) | (devfn << 8) | reg | cfg_type)); +/* surpress setting of PCI_PRIMARY_BUS */ +if (hose->indirect_type &PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS ) +if ((offset ==PCI_PRIMARY_BUS ) && + (bus->number == hose->first_busno)) + val &=0xffffff00 ; +/* * Note: the caller has already checked that offset is * suitably aligned and that len is 1, 2 or 4.
include/asm-ppc/pci-bridge.h +5 -0
@@ -73,9 +73,14 @@ struct pci_controller {* Used for variants of PCI indirect handling and possible quirks: * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 * EXT_REG - provides access to PCI-e extended registers +* SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS +* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS +* to determine which bus number to match on when generating type0 +* config cycles */ #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) +#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)u32 indirect_type;/* Currently, we limit ourselves to 1 IO range and 3 mem
Signature · 1 line
1.5.2.1
PATCH 13/15 MPC8641HPCN: Set IDE in ULI1575 to not native mode.
From: Zhang Wei <[email protected]>
Set IDE in ULI1575 to not 100% native mode, which forces the IDE driver to probe the irq itself.
--- arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c +1 -0
@@ -312,6 +312,7 @@ static void __devinit quirk_uli5229(struct pci_dev *dev) {unsigned short temp;pci_write_config_word (dev,0x04 ,0x0405 ); + dev->class &= ~0x5 ;pci_read_config_word (dev,0x4a , &temp); temp |=0x1000 ;pci_write_config_word (dev,0x4a , temp);
Signature · 1 line
1.5.2.1
PATCH 14/15 Let subordinate transparent bridges be transparent.
From: York Sun <[email protected]>
In pcibios_fixup_bus(), bridges that are subordinate to transparent bridges were still relocating their IORESOURCE_IO and IO_RESOURCE_MEM start and end values.
Fix this by preventing the transparent bridge from relocating the start and end values, thus allowing the subordinate non-transparent bridge full molestation rights.
--- arch/powerpc/kernel/pci_32.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
arch/powerpc/kernel/pci_32.c +1 -1
@@ -1370,7 +1370,7 @@ void __init pcibios_fixup_bus(struct pci_bus *bus)for (i =0 ; i <4 ; ++i) {if ((res = bus->resource[i]) ==NULL )continue ; -if (!res->flags) +if (!res->flags || bus->self->transparent)continue ;if (io_offset && (res->flags &IORESOURCE_IO )) { res->start += io_offset;
Signature · 1 line
1.5.2.1
PATCH 15/15 86xx: Created quirk_fsl_pcie_transparent() to initialize bridge resources.
From: Zhang Wei <[email protected]>
The Freescale PCI-e RC poses as a transparent bridge, but does not implement the IO_BASE or IO_LIMIT registers in the config space. This means that the code which initializes the bridge resources ends up setting the IO resources erroneously. Add quick_fsl_pcie_transparent() to handle this.
This change sets RC of mpc8641 to be a transparent bridge for legacy I/O access and initializes the RC bridge resources from the device tree.
--- arch/powerpc/platforms/86xx/pci.c | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-)
arch/powerpc/platforms/86xx/pci.c +37 -0
@@ -134,6 +134,43 @@ mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)early_write_config_byte (hose,0 ,0 ,PCI_LATENCY_TIMER ,0x80 ); } +static void __devinit quirk_fsl_pcie_transparent (struct pci_dev *dev) +{ +struct resource *res; +int i, res_idx =PCI_BRIDGE_RESOURCES ; +struct pci_controller *hose; + +/* +* Make the bridge be transparent. +*/ + dev->transparent =1 ; + + hose =pci_bus_to_hose (dev->bus->number); +if (!hose) { +printk (KERN_ERR "Can't find hose for bus %d\n" , + dev->bus->number); +return ; + } + +if (hose->io_resource.flags) { + res = &dev->resource[res_idx++]; + res->start = hose->io_resource.start; + res->end = hose->io_resource.end; + res->flags = hose->io_resource.flags; + } + +for (i =0 ; i <3 ; i++) { + res = &dev->resource[res_idx + i]; + res->start = hose->mem_resources[i].start; + res->end = hose->mem_resources[i].end; + res->flags = hose->mem_resources[i].flags; + } +} + + +DECLARE_PCI_FIXUP_EARLY (0x1957 ,0x7010 , quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY (0x1957 ,0x7011 , quirk_fsl_pcie_transparent); +#define PCIE_LTSSM 0x404/* PCIe Link Training and Status */ #define PCIE_LTSSM_L0 0x16/* L0 state */
Signature · 1 line
1.5.2.1
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
In reply to Kumar GalaQuoted 10 lines · Kumar Gala
From: Wade Farnsworth <[email protected]>
This adds device nodes for the PCI bridges as well as the ISA devices on the newer revision MPC8641HPCN. It also adds the PCI ranges to the soc node so that address translation for the ISA devices works properly.
arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-2- ranges = <0 f8000000 00100000>; - reg = <f8000000 00100000>; // CCSRBAR 1M + ranges = <00001000 f8001000 000ff000
[...]
arch/powerpc/boot/dts/mpc8641_hpcn.dts line 64
Quoted 1 line
arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-0+ reg = <f8000000 00001000>; // CCSRBAR
This can't be right, and I suspect it will break any kernel access to the first 0x1000 bytes of the CCSR_BAR space. reg should actually describe the register space of the SOC. If ranges needs to specify that, too, they should be able to be redundant. But this looks like a big hack, to me. Am I missing something?
Andy
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
Quoted 11 lines
Quoted 3 lines
arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-2- ranges = <0 f8000000 00100000>; - reg = <f8000000 00100000>; // CCSRBAR 1M + ranges = <00001000 f8001000 000ff000[...]
arch/powerpc/boot/dts/mpc8641_hpcn.dts line 64
Quoted 1 line
arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-0+ reg = <f8000000 00001000>; // CCSRBARThis can't be right, and I suspect it will break any kernel access to the first
0x1000bytes of theCCSR_BARspace. reg should actually describe the register space of the SOC. If ranges needs to specify that, too, they should be able to be redundant. But this looks like a big hack, to me. Am I missing something?
"reg" and "ranges" can never overlap really.
Is this the special case where the PHB is visible in PCI configuration space?
Or, please explain what CCSR_BAR is...
Segher
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
Quoted 12 lines · Segher Boessenkool
Quoted 11 lines
Quoted 3 lines
arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-2- ranges = <0 f8000000 00100000>; - reg = <f8000000 00100000>; // CCSRBAR 1M + ranges = <00001000 f8001000 000ff000[...]
arch/powerpc/boot/dts/mpc8641_hpcn.dts line 64
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arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-0+ reg = <f8000000 00001000>; // CCSRBARThis can't be right, and I suspect it will break any kernel access to the first
0x1000bytes of theCCSR_BARspace. reg should actually describe the register space of the SOC. If ranges needs to specify that, too, they should be able to be redundant. But this looks like a big hack, to me. Am I missing something?
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"reg" and "ranges" can never overlap really.
Is this the special case where the PHB is visible in PCI configuration space?
Or, please explain what
CCSR_BARis...
Its a 1M MMIO register space on the SOC (all device registers on the SOC live there).
- k
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
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arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-2- ranges = <0 f8000000 00100000>; - reg = <f8000000 00100000>; // CCSRBAR 1M + ranges = <00001000 f8001000 000ff000[...]
arch/powerpc/boot/dts/mpc8641_hpcn.dts line 64
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arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-0+ reg = <f8000000 00001000>; // CCSRBARThis can't be right, and I suspect it will break any kernel access to the first
0x1000bytes of theCCSR_BARspace. reg should actually describe the register space of the SOC. If ranges needs to specify that, too, they should be able to be redundant. But this looks like a big hack, to me. Am I missing something?
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"reg" and "ranges" can never overlap really.
Is this the special case where the PHB is visible in PCI configuration space?
Or, please explain what
CCSR_BARis...Its a 1M MMIO register space on the SOC (all device registers on the SOC live there).
Okay, so it has nothing to do with PCI configuration space?
There is "BAR" in the name, so it is a movable range? Where is the base address set?
What is the relationship between (in the example) the address ranges x'f800_0000+1000 and x'f800_1000+ff000?
Segher
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
Quoted 14 lines · Segher Boessenkool
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arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-2- ranges = <0 f8000000 00100000>; - reg = <f8000000 00100000>; // CCSRBAR 1M + ranges = <00001000 f8001000 000ff000[...]
arch/powerpc/boot/dts/mpc8641_hpcn.dts line 64
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arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-0+ reg = <f8000000 00001000>; // CCSRBARThis can't be right, and I suspect it will break any kernel access to the first
0x1000bytes of theCCSR_BARspace. reg should actually describe the register space of the SOC. If ranges needs to specify that, too, they should be able to be redundant. But this looks like a big hack, to me. Am I missing something?"reg" and "ranges" can never overlap really.
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Is this the special case where the PHB is visible in PCI configuration space?
Or, please explain what
CCSR_BARis...Its a 1M MMIO register space on the SOC (all device registers on the SOC live there).
Okay, so it has nothing to do with PCI configuration space?
correct
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There is "BAR" in the name, so it is a movable range? Where is the base address set?
in a MMIO register in the space itself.
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What is the relationship between (in the example) the address ranges x'f800_0000+1000 and x'f800_1000+ff000?
uugh, not sure what that's all about.
- k
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
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arch/powerpc/boot/dts/mpc8641_hpcn.dts line 64
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arch/powerpc/boot/dts/mpc8641_hpcn.dts +2
-2- ranges = <0 f8000000 00100000>; - reg = <f8000000 00100000>; // CCSRBAR 1M + ranges = <00001000 f8001000 000ff000 + reg = <f8000000 00001000>; // CCSRBARThere is "BAR" in the name, so it is a movable range? Where is the base address set?
in a MMIO register in the space itself.
Oh, *great* design.</sarcasm>
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What is the relationship between (in the example) the address ranges x'f800_0000+1000 and x'f800_1000+ff000?
uugh, not sure what that's all about.
Reading back I see that the CCSR region is 1MB, and only the first 4kB are for this PHB. What is the rest of this range used for -- devices on this PCI bus, other SoC devices, ...?
Segher
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
Quoted 11 lines · Segher Boessenkool
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Review
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-2- ranges = <0 f8000000 00100000>; - reg = <f8000000 00100000>; // CCSRBAR 1M + ranges = <00001000 f8001000 000ff000 + reg = <f8000000 00001000>; // CCSRBARThere is "BAR" in the name, so it is a movable range? Where is the base address set?
in a MMIO register in the space itself.
Oh, *great* design.</sarcasm>
its not that bad ;)
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What is the relationship between (in the example) the address ranges x'f800_0000+1000 and x'f800_1000+ff000?
uugh, not sure what that's all about.
Reading back I see that the CCSR region is 1MB, and only the first 4kB are for this PHB. What is the rest of this range used for -- devices on this PCI bus, other SoC devices, ...?
No, the first 4kB are SOC/platform level config registers (high level window setup, CCSR location, etc).
The PHB registers are somewhere in the middle (0x8000, I think). All the children devices (enet, PHBs, etc) live in the 1M block.
I think my original idea was the reg property on the SOC node was for the first 4k block that held the SOC config registers. I think what Wade did is correct since the reg property on the SOC node isnt going to get translated through the ranges property and that they should be mutually exclusive.
- k
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
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-2- ranges = <0 f8000000 00100000>; - reg = <f8000000 00100000>; // CCSRBAR 1M + ranges = <00001000 f8001000 000ff000 + reg = <f8000000 00001000>; // CCSRBAR
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There is "BAR" in the name, so it is a movable range? Where is the base address set?
in a MMIO register in the space itself.
Oh, *great* design.</sarcasm>
its not that bad ;)
Well there's no way to configure it if the current configuration is screwed, or you just don't know what the current configuration is. Anyway, that's all beside the point here.
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What is the relationship between (in the example) the address ranges x'f800_0000+1000 and x'f800_1000+ff000?
uugh, not sure what that's all about.
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Reading back I see that the CCSR region is 1MB, and only the first 4kB are for this PHB. What is the rest of this range used for -- devices on this PCI bus, other SoC devices, ...?
No, the first 4kB are SOC/platform level config registers (high level window setup, CCSR location, etc).
The PHB registers are somewhere in the middle (
0x8000, I think). All the children devices (enet, PHBs, etc) live in the 1M block.
So:
-- CCSR doesn't sit on PCI at all
-- It is a SoC register space
-- And it is only needed for configuration, not for normal
operation? ( <-- I so much hope this one is true!)
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I think my original idea was the reg property on the SOC node was for the first 4k block that held the SOC config registers. I think what Wade did is correct since the reg property on the SOC node isnt going to get translated through the ranges property and that they should be mutually exclusive.
Yeah but I'm wondering about the other devices on CCSR now...
Segher
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
In reply to Kumar GalaQuoted 10 lines · Kumar Gala
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What is the relationship between (in the example) the address ranges x'f800_0000+1000 and x'f800_1000+ff000?
uugh, not sure what that's all about.
Reading back I see that the CCSR region is 1MB, and only the first 4kB are for this PHB. What is the rest of this range used for -- devices on this PCI bus, other SoC devices, ...?
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No, the first 4kB are SOC/platform level config registers (high level window setup, CCSR location, etc).
The PHB registers are somewhere in the middle (
0x8000, I think). All the children devices (enet, PHBs, etc) live in the 1M block.I think my original idea was the reg property on the SOC node was for the first 4k block that held the SOC config registers. I think what Wade did is correct since the reg property on the SOC node isnt going to get translated through the ranges property and that they should be mutually exclusive.
Ok, I'm thinking we don't need the reg property at all, or that it can be of size 0 or 4 (the CCSRBAR, itself). If we need to access registers in the first 4k, we can define reg properties for the submodules which are in the CCSR space.
My issue with the submitted option is that the first 4k don't really belong to an SOC "device", they are just the first 4k of registers. In this case, they are the Local Access Window registers. It sort of feels like we're arbitrarily deciding assigning the first 4k to the "SOC". If that's what we want to do, I'd like if we put it in booting-without-of.txt. Actually, it should go there, anyway.
Andy
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
In reply to Segher BoessenkoolQuoted 12 lines · Segher Boessenkool
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arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-2- ranges = <0 f8000000 00100000>; - reg = <f8000000 00100000>; // CCSRBAR 1M + ranges = <00001000 f8001000 000ff000[...]
arch/powerpc/boot/dts/mpc8641_hpcn.dts line 64
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arch/powerpc/boot/dts/mpc8641_hpcn.dts +1
-0+ reg = <f8000000 00001000>; // CCSRBARThis can't be right, and I suspect it will break any kernel access to the first
0x1000bytes of theCCSR_BARspace. reg should actually describe the register space of the SOC. If ranges needs to specify that, too, they should be able to be redundant. But this looks like a big hack, to me. Am I missing something?
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"reg" and "ranges" can never overlap really.
Is this really true, always?
What about something like a PReP PCI bridge, which has the registers for indirect config-space access in the same range as the ISA IO space?
Signature · 4 lines
David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
Re: [PATCH 09/15] [POWERPC] 86xx: Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
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This can't be right, and I suspect it will break any kernel access to the first
0x1000bytes of theCCSR_BARspace. reg should actually describe the register space of the SOC. If ranges needs to specify that, too, they should be able to be redundant. But this looks like a big hack, to me. Am I missing something?"reg" and "ranges" can never overlap really.
Is this really true, always?
Well think about it. "reg" is the addresses your bridge device's registers sit at. "ranges" is the addresses your bridge translates to its child bus.
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What about something like a PReP PCI bridge, which has the registers for indirect config-space access in the same range as the ISA IO space?
Yeah there are always nasty corner cases that are hard to express. Like a PHB that is visible as a device on its own PCI bus -- it would have to be its own child in the device tree! Such devices are best dealt with on a one-by-one basis.
Segher
Re: [PATCH 07/15] [POWERPC] Removed remnants of bus_offset
In reply to Kumar GalaQuoted 6 lines · Kumar Gala
Removed the remants of
bus_offsetand useself_busnoin the mv64x60 case and usepci_assign_all_buseson 83xx/85xx.83xx/85xx have multiple PHBs and the firmwares on these devices tend not to handle topologies with P2P bridges well so we let Linux just reassign the bus numbers to match.
[snip]
include/asm-ppc/pci-bridge.h struct pci_controller { · line 54
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include/asm-ppc/pci-bridge.h +1
-0@@ -48,6 +48,7 @@ struct pci_controller {int first_busno;int last_busno;int self_busno; +/* bus_offset is only used by ARCH=ppc */ int bus_offset;void __iomem *io_base_virt;
Might be a good time to copy asm-ppc/pci-bridge.h to asm-powerpc/pci-bridge-32.h, yeah?
Signature · 4 lines
David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
Re: [PATCH 07/15] [POWERPC] Removed remnants of bus_offset
Quoted 20 lines · David Gibson
Quoted 6 lines · Kumar Gala
Removed the remants of
bus_offsetand useself_busnoin the mv64x60 case and usepci_assign_all_buseson 83xx/85xx.83xx/85xx have multiple PHBs and the firmwares on these devices tend not to handle topologies with P2P bridges well so we let Linux just reassign the bus numbers to match.
[snip]
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include/asm-ppc/pci-bridge.h +1
-0@@ -48,6 +48,7 @@ struct pci_controller {int first_busno;int last_busno;int self_busno; +/* bus_offset is only used by ARCH=ppc */ int bus_offset;
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include/asm-ppc/pci-bridge.h struct pci_controller { · line 54
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include/asm-ppc/pci-bridge.h +0
-0void __iomem *io_base_virt;Might be a good time to copy
asm-ppc/pci-bridge.htoasm-powerpc/pci-bridge-32.h, yeah?
Yeah I'll look at something towards that, seeing as its one of the few headers we are including directly.
- k