SDM845 System Cache Driver
v6 cover SDM845 System Cache Driver
This series implements system cache or LLCC(Last Level Cache Controller) driver for SDM845 SOC. The purpose of the driver is to partition the system cache and program the settings such as priortiy, lines to probe while doing a look up in the system cache, low power related settings etc. The partitions are called cache slices. Each cache slice is associated with size and SCID(System Cache ID). The driver also provides API for clients to query the cache slice details,activate and deactivate them.
The driver can be broadly classified into:
* SOC specific driver: llcc-sdm845.c: Cache partitioning and cache slice properties for usecases on sdm845 that need to use system cache.
* API : llcc-slice.c: Exports APIs to clients to query cache slice details, activate and deactivate cache slices.
Changes since v5:
* Remove client information from DT and make driver data global.
* Check return value of llcc_update_act_ctrl function
* Change error returned from -EFAULT to -EINVAL
Changes since v4:
* Remove null pointer checks as per comments.
* Remove extra blank lines.
Changes since v3:
* Use the regmap_read_poll_timeout function
* Check for regmap read/write errors.
* Remove memory barrier after regmap write
* Derive memory bank offsets using stride macro variable
* Remove debug statements from code
* Remove the qcom_llcc_remove function
* Use if IS_ENABLED in place of ifdef for built-in module
* Change EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
* Remove unnecessary free functions
* Change the variable names as per review comments
Changes since v2:
* Corrected the Makefile to fix compilation.
Changes since v1:
* Added Makefile and Kconfig.
Changes since v0:
* Removed the syscon and simple-mfd approach
* Updated the device tree nodes to mention LLCC as a single HW block
* Moved llcc bank offsets from device tree and handled the offset in the driver.
ckadabi at codeaurora.org (2):
dt-bindings: Documentation for qcom, llcc
drivers: soc: Add LLCC driver
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 32 ++ drivers/soc/qcom/Kconfig | 17 ++ drivers/soc/qcom/Makefile | 2 + drivers/soc/qcom/llcc-sdm845.c | 106 +++++++ drivers/soc/qcom/llcc-slice.c | 335 +++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 162 ++++++++++ 6 files changed, 654 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt create mode 100644 drivers/soc/qcom/llcc-sdm845.c create mode 100644 drivers/soc/qcom/llcc-slice.c create mode 100644 include/linux/soc/qcom/llcc-qcom.h
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v6 1/2 dt-bindings: Documentation for qcom, llcc
Documentation for last level cache controller device tree bindings, client bindings usage examples.
--- .../devicetree/bindings/arm/msm/qcom,llcc.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +32 -0
@@ -0,0 +1,32 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, +that can be shared by multiple clients. Clients here are different cores in the +SOC, the idea is to minimize the local caches at the clients and migrate to +common pool of memory. Cache memory is divided into partitions called slices +which are assigned to clients. Clients can query the slice details, activate +and deactivate them. + +Properties: +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: <prop-encoded-array> + Definition: Start address and the range of the LLCC registers. + +- max-slices: + usage: required + Value Type: <u32> + Definition: Number of cache slices supported by hardware + +Example: + + llcc: qcom,llcc at 1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + max-slices = <32>; + };
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v6 1/2] dt-bindings: Documentation for qcom, llcc
Quoting Rishabh Bhatnagar (2018-05-08 13:22:00)
Quoted 15 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +9
-0@@ -0,0 +1,32 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, +that can be shared by multiple clients. Clients here are different cores in the +SOC, the idea is to minimize the local caches at the clients and migrate to +common pool of memory. Cache memory is divided into partitions called slices +which are assigned to clients. Clients can query the slice details, activate +and deactivate them. +
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt line 19
Quoted 10 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +10
-0+Properties: +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: <prop-encoded-array> + Definition: Start address and the range of the LLCC registers.
Start address and size?
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt line 28
Quoted 9 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +9
-0+ +- max-slices: + usage: required + Value Type: <u32> + Definition: Number of cache slices supported by hardware + +Example: + + llcc: qcom,llcc at 1100000 {
cache-controller at 1100000 ?
Quoted 5 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +4
-0+ compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + max-slices = <32>; + };
Re: [PATCH v6 1/2] dt-bindings: Documentation for qcom, llcc
Quoted 26 lines · Stephen Boyd
Quoting Rishabh Bhatnagar (2018-05-08 13:22:00)
Quoted 25 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +3
-0@@ -0,0 +1,32 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cachememory in SOC,
+that can be shared by multiple clients. Clients here are different cores in the
+SOC, the idea is to minimize the local caches at the clients and migrate to
+common pool of memory. Cache memory is divided into partitions called slices
+which are assigned to clients. Clients can query the slice details, activateDocumentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +6
-0+and deactivate them. + +Properties: +- compatible: + Usage: required + Value type: <string>
Quoted 9 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt line 19
Quoted 6 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +6
-0+ Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: <prop-encoded-array> + Definition: Start address and the range of the LLCC registers.Start address and size?
Yes i'll change it to Start address and size of the register region.
Quoted 12 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt line 28
Quoted 9 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +9
-0+ +- max-slices: + usage: required + Value Type: <u32> + Definition: Number of cache slices supported by hardware + +Example: + + llcc: qcom,llcc at 1100000 {cache-controller at 1100000 ?
We have tried to use consistent naming convention as in llcc_* everywhere.
Using cache-controller will mix and match the naming convention. Also in the documentation it is explained what llcc is and its full form.
Quoted 5 lines
Quoted 5 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +4
-1+ compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + max-slices = <32>; + }; --
Re: [PATCH v6 1/2] dt-bindings: Documentation for qcom, llcc
Quoting rishabhb at codeaurora.org (2018-05-16 10:33:14)
Quoted 15 lines · Stephen Boyd
Quoted 14 lines
Quoting Rishabh Bhatnagar (2018-05-08 13:22:00)
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt line 28
Quoted 9 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +9
-0+ +- max-slices: + usage: required + Value Type: <u32> + Definition: Number of cache slices supported by hardware + +Example: + + llcc: qcom,llcc at 1100000 {cache-controller at 1100000 ?
Quoted 5 lines
We have tried to use consistent naming convention as in llcc_* everywhere.
Using cache-controller will mix and match the naming convention. Also in the documentation it is explained what llcc is and its full form.
DT prefers standard node names as opposed to vendor specific node names. Isn't it a cache controller? I fail to see why this can't be done.
Re: [PATCH v6 1/2] dt-bindings: Documentation for qcom, llcc
Quoted 23 lines · Stephen Boyd
Quoting rishabhb at codeaurora.org (2018-05-16 10:33:14)
Quoted 15 lines · Stephen Boyd
Quoted 14 lines
Quoting Rishabh Bhatnagar (2018-05-08 13:22:00)
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt line 28
Quoted 9 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +9
-0+ +- max-slices: + usage: required + Value Type: <u32> + Definition: Number of cache slices supported by hardware + +Example: + + llcc: qcom,llcc at 1100000 {cache-controller at 1100000 ?
Quoted 6 lines
We have tried to use consistent naming convention as in llcc_* everywhere.
Using cache-controller will mix and match the naming convention. Also in
the documentation it is explained what llcc is and its full form.
Quoted 3 lines
DT prefers standard node names as opposed to vendor specific node names.
Isn't it a cache controller? I fail to see why this can't be done.
Hi Stephen,
The driver is vendor specific and also for uniformity purposes we preferred
to go with this name.
Rob Herring
maintainerRe: [PATCH v6 1/2] dt-bindings: Documentation for qcom, llcc
Quoted 24 lines · rishabhb at codeaurora.org
Quoted 23 lines · Stephen Boyd
Quoting rishabhb at codeaurora.org (2018-05-16 10:33:14)
Quoted 21 lines · Stephen Boyd
Quoted 14 lines
Quoting Rishabh Bhatnagar (2018-05-08 13:22:00)
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt line 28
Quoted 9 lines
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file +9
-0+ +- max-slices: + usage: required + Value Type: <u32> + Definition: Number of cache slices supported by hardware + +Example: + + llcc: qcom,llcc at 1100000 {cache-controller at 1100000 ?
We have tried to use consistent naming convention as in llcc_* everywhere.
Using cache-controller will mix and match the naming convention. Also in
the documentation it is explained what llcc is and its full form.
Quoted 5 lines
Quoted 2 lines
DT prefers standard node names as opposed to vendor specific node names. Isn't it a cache controller? I fail to see why this can't be done.
Hi Stephen,
The driver is vendor specific and also for uniformity purposes we preferred to go with this name.
Almost *every* node and driver is vendor specific. Please do as Stephen suggested.
Rob
PATCH v6 2/2 drivers: soc: Add LLCC driver
In reply to Rishabh BhatnagarLLCC (Last Level Cache Controller) provides additional cache memory in the system. LLCC is partitioned into multiple slices and each slice gets its own priority, size, ID and other config parameters. LLCC driver programs these parameters for each slice. Clients that are assigned to use LLCC need to get information such size & ID of the slice they get and activate or deactivate the slice as needed. LLCC driver provides API for the clients to perform these operations.
--- drivers/soc/qcom/Kconfig | 17 ++ drivers/soc/qcom/Makefile | 2 + drivers/soc/qcom/llcc-sdm845.c | 106 ++++++++++++ drivers/soc/qcom/llcc-slice.c | 335 +++++++++++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 162 ++++++++++++++++++ 5 files changed, 622 insertions(+) create mode 100644 drivers/soc/qcom/llcc-sdm845.c create mode 100644 drivers/soc/qcom/llcc-slice.c create mode 100644 include/linux/soc/qcom/llcc-qcom.h
drivers/soc/qcom/Kconfig +17 -0
@@ -21,6 +21,23 @@ config QCOM_GSBI functions for connecting the underlying serial UART, SPI, and I2C devices to the output pins. +config QCOM_LLCC + tristate "Qualcomm Technologies, Inc. LLCC driver" + depends on ARCH_QCOM + help + Qualcomm Technologies, Inc. platform specific + Last Level Cache Controller(LLCC) driver. This provides interfaces + to clients that use the LLCC. Say yes here to enable LLCC slice + driver. + +config QCOM_SDM845_LLCC + tristate "Qualcomm Technologies, Inc. SDM845 LLCC driver" + depends on QCOM_LLCC + help + Say yes here to enable the LLCC driver for SDM845. This provides + data required to configure LLCC so that clients can start using the + LLCC slices. + config QCOM_MDT_LOADER tristate select QCOM_SCM
drivers/soc/qcom/Makefile +2 -0
@@ -12,3 +12,5 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o obj-$(CONFIG_QCOM_SMP2P) += smp2p.o obj-$(CONFIG_QCOM_SMSM) += smsm.o obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o +obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o +obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o
drivers/soc/qcom/llcc-sdm845.c new file +106 -0
106 lines not on this page · raw message
drivers/soc/qcom/llcc-slice.c new file +335 -0
335 lines not on this page · raw message
include/linux/soc/qcom/llcc-qcom.h new file +162 -0
162 lines not on this page · raw message
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v6 2/2] drivers: soc: Add LLCC driver
Hi Rishabh,
Quoted 8 lines · Rishabh Bhatnagar
LLCC (Last Level Cache Controller) provides additional cache memory in the system. LLCC is partitioned into multiple slices and each slice gets its own priority, size, ID and other config parameters. LLCC driver programs these parameters for each slice. Clients that are assigned to use LLCC need to get information such size & ID of the slice they get and activate or deactivate the slice as needed. LLCC driver provides API for the clients to perform these operations.
Quoted 7 lines
Signed-off-by Channagoud Kadabi <[email protected]>Signed-off-by Rishabh Bhatnagar <[email protected]>--- drivers/soc/qcom/Kconfig | 17 ++ drivers/soc/qcom/Makefile | 2 + drivers/soc/qcom/llcc-sdm845.c | 106 ++++++++++++ drivers/soc/qcom/llcc-slice.c | 335
+++++++++++++++++++++++++++++++++++++
Quoted 5 lines
include/linux/soc/qcom/llcc-qcom.h | 162 ++++++++++++++++++ 5 files changed, 622 insertions(+)create mode 100644
drivers/soc/qcom/llcc-sdm845.ccreate mode 100644drivers/soc/qcom/llcc-slice.ccreate mode 100644include/linux/soc/qcom/llcc-qcom.h
...
Review
Quoted 1 line
(quoted diff) +0
-0
b/drivers/soc/qcom/llcc-sdm845.c
Quoted 13 lines
new file mode 100644
index 0000000..e5e792cdrivers/soc/qcom/llcc-sdm845.c new file +8
-0@@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +* +*/ + +#include <linux/kernel.h> +#include <linux/module.h>
drivers/soc/qcom/llcc-sdm845.c line 18
Quoted 10 lines
drivers/soc/qcom/llcc-sdm845.c new file +10
-0+#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/soc/qcom/llcc-qcom.h> + +/* +* SCT(System Cache Table) entry contains of the following members: +* usecase_id: Unique id for the client's use case +* slice_id: llcc slice id for each client +* max_cap: The maximum capacity of the cache slice provided in KB +* priority: Priority of the client used to select victim line for
replacement
drivers/soc/qcom/llcc-sdm845.c
Quoted 3 lines
drivers/soc/qcom/llcc-sdm845.c new file +3
-0+* fixed_size: Boolean indicating if the slice has a fixed capacity +* bonus_ways: Bonus ways are additional ways to be used for any slice, +* if client ends up using more than reserved cache ways.
Bonus
drivers/soc/qcom/llcc-sdm845.c
Quoted 5 lines
drivers/soc/qcom/llcc-sdm845.c new file +5
-0+* ways are allocated only if they are not reserved for some +* other client. +* res_ways: Reserved ways for the cache slice, the reserved ways cannot +* be used by any other client than the one its assigned to. +* cache_mode: Each slice operates as a cache, this controls the mode of
the
drivers/soc/qcom/llcc-sdm845.c
Quoted 3 lines
drivers/soc/qcom/llcc-sdm845.c new file +3
-0+* slice: normal or TCM(Tightly Coupled Memory) +* probe_target_ways: Determines what ways to probe for access hit. When +* configured to 1 only bonus and reserved ways are
probed.
drivers/soc/qcom/llcc-sdm845.c
Quoted 4 lines
drivers/soc/qcom/llcc-sdm845.c new file +4
-0+* When configured to 0 all ways in llcc are probed. +* dis_cap_alloc: Disable capacity based allocation for a client +* retain_on_pc: If this bit is set and client has maintained active vote +* then the ways assigned to this client are not flushed
on power
drivers/soc/qcom/llcc-sdm845.c line 35
Quoted 2 lines
drivers/soc/qcom/llcc-sdm845.c new file +2
-0+* collapse. +* activate_on_init: Activate the slice immediately after the SCT is
programmed
drivers/soc/qcom/llcc-sdm845.c line 37
Quoted 2 lines
drivers/soc/qcom/llcc-sdm845.c new file +2
-0+*/ +#define SCT_ENTRY(uid, sid, mc, p, fs, bway, rway, cmod, ptw, dca, rp,
a) \
Quoted 25 lines
drivers/soc/qcom/llcc-sdm845.c new file +25
-0+ { \ + .usecase_id = uid, \ + .slice_id = sid, \ + .max_cap = mc, \ + .priority = p, \ + .fixed_size = fs, \ + .bonus_ways = bway, \ + .res_ways = rway, \ + .cache_mode = cmod, \ + .probe_target_ways = ptw, \ + .dis_cap_alloc = dca, \ + .retain_on_pc = rp, \ + .activate_on_init = a, \ + } + +static struct llcc_slice_config sdm845_data[] = { +SCT_ENTRY (1 ,1 ,2816 ,1 ,0 ,0xffc ,0x2 ,0 ,0 ,1 ,1 ,1 ), +SCT_ENTRY (2 ,2 ,512 ,2 ,1 ,0x0 ,0x0f0 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (3 ,3 ,512 ,2 ,1 ,0x0 ,0x0f0 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (4 ,4 ,563 ,2 ,1 ,0x0 ,0x00e ,2 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (5 ,5 ,2816 ,1 ,0 ,0xffc ,0x2 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (6 ,6 ,2816 ,1 ,0 ,0xffc ,0x2 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (7 ,7 ,1024 ,2 ,0 ,0xfc ,0xf00 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (8 ,8 ,2816 ,1 ,0 ,0xffc ,0x2 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (10 ,10 ,2816 ,1 ,0 ,0xffc ,0x2 ,0 ,0 ,1 ,1 ,0 ),
drivers/soc/qcom/llcc-sdm845.c line 72
Quoted 10 lines
drivers/soc/qcom/llcc-sdm845.c new file +10
-0+SCT_ENTRY (11 ,11 ,512 ,1 ,1 ,0xc ,0x0 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (12 ,12 ,2304 ,1 ,0 ,0xff0 ,0x2 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (13 ,13 ,256 ,2 ,0 ,0x0 ,0x1 ,0 ,0 ,1 ,0 ,1 ), +SCT_ENTRY (15 ,15 ,2816 ,1 ,0 ,0xffc ,0x2 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (16 ,16 ,2816 ,1 ,0 ,0xffc ,0x2 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (17 ,17 ,2816 ,1 ,0 ,0xffc ,0x2 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (20 ,20 ,1024 ,2 ,1 ,0x0 ,0xf00 ,0 ,0 ,1 ,1 ,0 ), +SCT_ENTRY (21 ,21 ,1024 ,0 ,1 ,0x1e ,0x0 ,0 ,0 ,1 ,1 ,0 ), + SCT_ENTRY(22, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0), +};
Now that drivers are hardcoding IDs when calling llcc_slice_getd, should we add #defines in llcc-qcom.h for each of the usecase IDs? Then this would change the entries to look like:
SCT_ENTRY(QCOM_LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1,
1, 1),
and drivers using it would call llcc_slice_getd(QCOM_LLCC_CPUSS), rather than llcc_slice_getd(1).
Quoted 6 lines
drivers/soc/qcom/llcc-slice.c new file +0
-0@@ -0,0 +1,335 @@
...
Quoted 15 lines
drivers/soc/qcom/llcc-slice.c new file +15
-0+ +/** +* llcc_slice_activate - Activate the llcc slice +* @desc: Pointer to llcc slice descriptor +* +* A value of zero will be returned on success and a negative errno will +* be returned in error cases +*/ +int llcc_slice_activate (struct llcc_slice_desc *desc) +{ +int ret; +u32 act_ctrl_val; + +mutex_lock (&drv_data->lock); +if (test_bit (desc->slice_id, drv_data->bitmap)) {
drivers/soc/qcom/llcc-slice.c line 153
Quoted 10 lines
drivers/soc/qcom/llcc-slice.c new file +10
-0+mutex_unlock (&drv_data->lock); +return 0 ; + } + + act_ctrl_val =ACT_CTRL_OPCODE_ACTIVATE <<ACT_CTRL_OPCODE_SHIFT ; + + ret =llcc_update_act_ctrl (desc->slice_id, act_ctrl_val, +DEACTIVATE ); +if (ret) +return ret;
I had asked for this in the last revision, and thank you for putting that in so that the bitmap matches reality. Unfortunately this introduces another error, which is that you never unlock the mutex :(
Quoted 16 lines
drivers/soc/qcom/llcc-slice.c new file +16
-0+ +__set_bit (desc->slice_id, drv_data->bitmap); +mutex_unlock (&drv_data->lock); + +return ret; +} +EXPORT_SYMBOL_GPL (llcc_slice_activate); + +/** +* llcc_slice_deactivate - Deactivate the llcc slice +* @desc: Pointer to llcc slice descriptor +* +* A value of zero will be returned on success and a negative errno will +* be returned in error cases +*/ +int llcc_slice_deactivate (struct llcc_slice_desc *desc)
drivers/soc/qcom/llcc-slice.c
Quoted 10 lines
drivers/soc/qcom/llcc-slice.c new file +10
-0+{ +u32 act_ctrl_val; +int ret; + +mutex_lock (&drv_data->lock); +if (!test_bit (desc->slice_id, drv_data->bitmap)) { +mutex_unlock (&drv_data->lock); +return 0 ; + } + act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE <<
ACT_CTRL_OPCODE_SHIFT;
drivers/soc/qcom/llcc-slice.c line 184
Quoted 5 lines
drivers/soc/qcom/llcc-slice.c new file +5
-0+ + ret =llcc_update_act_ctrl (desc->slice_id, act_ctrl_val, +ACTIVATE ); +if (ret) +return ret;
Same here, mutex left locked.
Quoted 38 lines
drivers/soc/qcom/llcc-slice.c new file +38
-0+ +__clear_bit (desc->slice_id, drv_data->bitmap); +mutex_unlock (&drv_data->lock); + +return ret; +} +EXPORT_SYMBOL_GPL (llcc_slice_deactivate); + +/** +* llcc_get_slice_id - return the slice id +* @desc: Pointer to llcc slice descriptor +*/ +int llcc_get_slice_id (struct llcc_slice_desc *desc) +{ +return desc->slice_id; +} +EXPORT_SYMBOL_GPL (llcc_get_slice_id); + +/** +* llcc_get_slice_size - return the slice id +* @desc: Pointer to llcc slice descriptor +*/ +size_t llcc_get_slice_size (struct llcc_slice_desc *desc) +{ +return desc->slice_size; +} +EXPORT_SYMBOL_GPL (llcc_get_slice_size); + +static int qcom_llcc_cfg_program (struct platform_device *pdev) +{ +int i; +u32 attr1_cfg; +u32 attr0_cfg; +u32 attr1_val; +u32 attr0_val; +u32 max_cap_cacheline; +u32 sz; +int ret =0 ;
drivers/soc/qcom/llcc-slice.c line 235
Quoted 10 lines
drivers/soc/qcom/llcc-slice.c new file +10
-0+const struct llcc_slice_config *llcc_table; +struct llcc_slice_desc desc; +u32 bcast_off = drv_data->bcast_off; + + sz = drv_data->cfg_size; + llcc_table = drv_data->cfg; + +for (i =0 ; i < sz; i++) { + attr1_cfg = bcast_off + +
LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
drivers/soc/qcom/llcc-slice.c line 235
Quoted 2 lines
drivers/soc/qcom/llcc-slice.c new file +2
-0+ attr0_cfg = bcast_off + +
LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
drivers/soc/qcom/llcc-slice.c
Quoted 7 lines
drivers/soc/qcom/llcc-slice.c new file +7
-0+ + attr1_val = llcc_table[i].cache_mode; + attr1_val |= llcc_table[i].probe_target_ways << +ATTR1_PROBE_TARGET_WAYS_SHIFT ; + attr1_val |= llcc_table[i].fixed_size << +ATTR1_FIXED_SIZE_SHIFT ; + attr1_val |= llcc_table[i].priority <<
ATTR1_PRIORITY_SHIFT;
drivers/soc/qcom/llcc-slice.c
Quoted 2 lines
drivers/soc/qcom/llcc-slice.c new file +2
-0+ + max_cap_cacheline =
MAX_CAP_TO_BYTES(llcc_table[i].max_cap);
drivers/soc/qcom/llcc-slice.c
Quoted 3 lines
drivers/soc/qcom/llcc-slice.c new file +3
-0+ +/* LLCC instances can vary for each target. +* The SW writes to broadcast register which gets
propagated
drivers/soc/qcom/llcc-slice.c
Quoted 2 lines
drivers/soc/qcom/llcc-slice.c new file +2
-0+* to each llcc instace (llcc0,.. llccN). +* Since the size of the memory is divided equally
amongst the
Quoted 1 line
+ * llcc instances, we need to configure the max cap
accordingly.
drivers/soc/qcom/llcc-slice.c
Quoted 2 lines
drivers/soc/qcom/llcc-slice.c new file +2
-0+*/ + max_cap_cacheline = max_cap_cacheline /
drv_data->num_banks;
drivers/soc/qcom/llcc-slice.c
Quoted 5 lines
drivers/soc/qcom/llcc-slice.c new file +5
-0+ max_cap_cacheline >>=CACHE_LINE_SIZE_SHIFT ; + attr1_val |= max_cap_cacheline <<ATTR1_MAX_CAP_SHIFT ; + + attr0_val = llcc_table[i].res_ways &ATTR0_RES_WAYS_MASK ; + attr0_val |= llcc_table[i].bonus_ways <<
ATTR0_BONUS_WAYS_SHIFT;
drivers/soc/qcom/llcc-slice.c
Quoted 2 lines
drivers/soc/qcom/llcc-slice.c new file +2
-0+ + ret = regmap_write(drv_data->regmap, attr1_cfg,
attr1_val);
drivers/soc/qcom/llcc-slice.c
Quoted 3 lines
drivers/soc/qcom/llcc-slice.c new file +3
-0+if (ret) +return ret; + ret = regmap_write(drv_data->regmap, attr0_cfg,
attr0_val);
Quoted 39 lines
drivers/soc/qcom/llcc-slice.c new file +39
-0+if (ret) +return ret; +if (llcc_table[i].activate_on_init) { + desc.slice_id = llcc_table[i].slice_id; + ret =llcc_slice_activate (&desc); + } + } +return ret; +} + +int qcom_llcc_probe (struct platform_device *pdev, +const struct llcc_slice_config *llcc_cfg,u32 sz) +{ + +u32 num_banks =0 ; +struct device *dev = &pdev->dev; +struct resource *res; +void __iomem *base; +int ret =0 ; +int i; + + drv_data =devm_kzalloc (dev,sizeof (*drv_data),GFP_KERNEL ); +if (!drv_data) +return -ENOMEM ; + + res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); + base =devm_ioremap_resource (&pdev->dev, res); +if (IS_ERR (base)) +return PTR_ERR (base); + + drv_data->regmap =devm_regmap_init_mmio (dev, base, + &llcc_regmap_config); +if (IS_ERR (drv_data->regmap)) +return PTR_ERR (drv_data->regmap); + + ret =regmap_read (drv_data->regmap,LLCC_COMMON_STATUS0 , + &num_banks); +if (ret) +return ret;
drivers/soc/qcom/llcc-slice.c line 310
Quoted 10 lines
drivers/soc/qcom/llcc-slice.c new file +10
-0+ + num_banks &=LLCC_LB_CNT_MASK ; + num_banks >>=LLCC_LB_CNT_SHIFT ; + drv_data->num_banks = num_banks; + + ret =of_property_read_u32 (pdev->dev.of_node,"max-slices" , + &drv_data->max_slices); +if (ret) +return ret; +
The way this driver is written, there is only one sane value for max-slices, and it can be derived by finding the max slice_id in llcc_cfg. You only use "max-slices" to size the bitmap, but then use the slice_id everywhere when indexing into the bitmap, so as far as I can tell this DT property is not needed. Can we remove it from the binding and just derive the value by iterating over llcc_cfg to find the max slice_id?
-Evan