ARM: EXYNOS: cpuidle: Several fixes in exynos cpuidle/PM

Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform.

Cc Abhilash Kesavan <[email protected]>

Cc Thomas Abraham <[email protected]>

Signed-off-by Amit Daniel Kachhap <[email protected]>

---
Re-based against linux for-next branch.

 arch/arm/mach-exynos/cpuidle.c       |   35 ----------------------------
 drivers/clk/samsung/clk-exynos5250.c |   42 ++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 35 deletions(-)

arch/arm/mach-exynos/cpuidle.c +0 -35

index 17a18ff..4667907 100644
@@ -159,46 +159,11 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
                return exynos4_enter_core0_aftr(dev, drv, new_index);
 }
 
-static void __init exynos5_core_down_clk(void)
-{
-       unsigned int tmp;
-
-       /*
-        * Enable arm clock down (in idle) and set arm divider
-        * ratios in WFI/WFE state.
-        */
-       tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
-             PWR_CTRL1_CORE1_DOWN_RATIO | \
-             PWR_CTRL1_DIV2_DOWN_EN     | \
-             PWR_CTRL1_DIV1_DOWN_EN     | \
-             PWR_CTRL1_USE_CORE1_WFE    | \
-             PWR_CTRL1_USE_CORE0_WFE    | \
-             PWR_CTRL1_USE_CORE1_WFI    | \
-             PWR_CTRL1_USE_CORE0_WFI;
-       __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
-
-       /*
-        * Enable arm clock up (on exiting idle). Set arm divider
-        * ratios when not in idle along with the standby duration
-        * ratios.
-        */
-       tmp = PWR_CTRL2_DIV2_UP_EN       | \
-             PWR_CTRL2_DIV1_UP_EN       | \
-             PWR_CTRL2_DUR_STANDBY2_VAL | \
-             PWR_CTRL2_DUR_STANDBY1_VAL | \
-             PWR_CTRL2_CORE2_UP_RATIO   | \
-             PWR_CTRL2_CORE1_UP_RATIO;
-       __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
-}
-
 static int __init exynos4_init_cpuidle(void)
 {
        int cpu_id, ret;
        struct cpuidle_device *device;
 
-       if (soc_is_exynos5250())
-               exynos5_core_down_clk();
-
        ret = cpuidle_register_driver(&exynos4_idle_driver);
        if (ret) {
                printk(KERN_ERR "CPUidle failed to register driver\n");

drivers/clk/samsung/clk-exynos5250.c +42 -1

index 5c97e75..89f51e9 100644
@@ -21,6 +21,8 @@
 
 #define SRC_CPU                        0x200
 #define DIV_CPU0               0x500
+#define PWR_CTRL1              0x1020
+#define PWR_CTRL2              0x1024
 #define SRC_CORE1              0x4204
 #define SRC_TOP0               0x10210
 #define SRC_TOP2               0x10218

@@ -63,6 +65,23 @@
 #define PLL_DIV2_SEL           0x20a24
 #define GATE_IP_DISP1          0x10928
 
+/*Below definitions are used for PWR_CTRL settings*/
+#define PWR_CTRL1_CORE2_DOWN_RATIO             (7 << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO             (7 << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN                 (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN                 (1 << 8)
+#define PWR_CTRL1_USE_CORE1_WFE                        (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE                        (1 << 4)
+#define PWR_CTRL1_USE_CORE1_WFI                        (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI                        (1 << 0)
+
+#define PWR_CTRL2_DIV2_UP_EN                   (1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN                   (1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2_VAL             (1 << 16)
+#define PWR_CTRL2_DUR_STANDBY1_VAL             (1 << 8)
+#define PWR_CTRL2_CORE2_UP_RATIO               (1 << 4)
+#define PWR_CTRL2_CORE1_UP_RATIO               (1 << 0)
+
 /*
  * Let each supported clock get a unique id. This id is used to lookup the clock
  * for device tree based platforms. The clocks are categorized into three

@@ -110,6 +129,8 @@ enum exynos5250_clks {
 static __initdata unsigned long exynos5250_clk_regs[] = {
        SRC_CPU,
        DIV_CPU0,
+       PWR_CTRL1,
+       PWR_CTRL2,
        SRC_CORE1,
        SRC_TOP0,
        SRC_TOP2,

@@ -474,6 +495,7 @@ void __init exynos5250_clk_init(struct device_node *np)
 {
        void __iomem *reg_base;
        struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+       unsigned int tmp;
 
        if (np) {
                reg_base = of_iomap(np, 0);

@@ -516,6 +538,26 @@ void __init exynos5250_clk_init(struct device_node *np)
        samsung_clk_register_gate(exynos5250_gate_clks,
                        ARRAY_SIZE(exynos5250_gate_clks));
 
+       /*
+        * Enable arm clock down (in idle) and set arm divider
+        * ratios in WFI/WFE state.
+        */
+       tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
+               PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
+               PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
+               PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
+       __raw_writel(tmp, reg_base + PWR_CTRL1);
+
+       /*
+        * Enable arm clock up (on exiting idle). Set arm divider
+        * ratios when not in idle along with the standby duration
+        * ratios.
+        */
+       tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
+               PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
+               PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
+       __raw_writel(tmp, reg_base + PWR_CTRL2);
+
        pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
                        _get_rate("armclk"));
 }
--

1.7.1

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Hi Mike,

If possible please ack this patch or merge this via your tree.

Thanks,
Amit Daniel

Quoted 1 line · Amit Daniel Kachhap

Now with common clock support added for exynos5250 it is necessary to

move

Quoted 2 lines

this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale

platform.

Quoted 4 lines

Cc Abhilash Kesavan <[email protected]>

Cc Thomas Abraham <[email protected]>

Signed-off-by Amit Daniel Kachhap <[email protected]>

Quoted 4 lines

---
Re-based against linux for-next branch.

 arch/arm/mach-exynos/cpuidle.c       |   35

Quoted 1 line

 drivers/clk/samsung/clk-exynos5250.c |   42

++++++++++++++++++++++++++++++++++

arch/arm/mach-

Quoted 3 lines

 2 files changed, 42 insertions(+), 35 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-exynos/cpuidle.c +0 -0

exynos/cpuidle.c

arch/arm/mach-exynos/cpuidle.c static int exynos4_enter_lowpower(struct

Quoted 4 lines

index 17a18ff..4667907 100644

arch/arm/mach-exynos/cpuidle.c +0 -0

@@ -159,46 +159,11 @@ static int exynos4_enter_lowpower(struct

cpuidle_device *dev,

Review

Quoted 47 lines

arch/arm/mach-exynos/cpuidle.c +0 -35

                return exynos4_enter_core0_aftr(dev, drv, new_index);
 }
 
-static void __init exynos5_core_down_clk(void)
-{
-       unsigned int tmp;
-
-       /*
-        * Enable arm clock down (in idle) and set arm divider
-        * ratios in WFI/WFE state.
-        */
-       tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
-             PWR_CTRL1_CORE1_DOWN_RATIO | \
-             PWR_CTRL1_DIV2_DOWN_EN     | \
-             PWR_CTRL1_DIV1_DOWN_EN     | \
-             PWR_CTRL1_USE_CORE1_WFE    | \
-             PWR_CTRL1_USE_CORE0_WFE    | \
-             PWR_CTRL1_USE_CORE1_WFI    | \
-             PWR_CTRL1_USE_CORE0_WFI;
-       __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
-
-       /*
-        * Enable arm clock up (on exiting idle). Set arm divider
-        * ratios when not in idle along with the standby duration
-        * ratios.
-        */
-       tmp = PWR_CTRL2_DIV2_UP_EN       | \
-             PWR_CTRL2_DIV1_UP_EN       | \
-             PWR_CTRL2_DUR_STANDBY2_VAL | \
-             PWR_CTRL2_DUR_STANDBY1_VAL | \
-             PWR_CTRL2_CORE2_UP_RATIO   | \
-             PWR_CTRL2_CORE1_UP_RATIO;
-       __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
-}
-
 static int __init exynos4_init_cpuidle(void)
 {
        int cpu_id, ret;
        struct cpuidle_device *device;
 
-       if (soc_is_exynos5250())
-               exynos5_core_down_clk();
-
        ret = cpuidle_register_driver(&exynos4_idle_driver);
        if (ret) {
                printk(KERN_ERR "CPUidle failed to register driver\n");

(quoted diff) +0 -0

b/drivers/clk/samsung/clk-exynos5250.c

Quoted 25 lines

index 5c97e75..89f51e9 100644

drivers/clk/samsung/clk-exynos5250.c +11 -0

@@ -21,6 +21,8 @@
 
 #define SRC_CPU                        0x200
 #define DIV_CPU0               0x500
+#define PWR_CTRL1              0x1020
+#define PWR_CTRL2              0x1024
 #define SRC_CORE1              0x4204
 #define SRC_TOP0               0x10210
 #define SRC_TOP2               0x10218

@@ -63,6 +65,23 @@
 #define PLL_DIV2_SEL           0x20a24
 #define GATE_IP_DISP1          0x10928
 
+/*Below definitions are used for PWR_CTRL settings*/
+#define PWR_CTRL1_CORE2_DOWN_RATIO             (7 << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO             (7 << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN                 (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN                 (1 << 8)
+#define PWR_CTRL1_USE_CORE1_WFE                        (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE                        (1 << 4)
+#define PWR_CTRL1_USE_CORE1_WFI                        (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI                        (1 << 0)

drivers/clk/samsung/clk-exynos5250.c line 86

Quoted 10 lines

drivers/clk/samsung/clk-exynos5250.c +8 -0

+
+#define PWR_CTRL2_DIV2_UP_EN                   (1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN                   (1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2_VAL             (1 << 16)
+#define PWR_CTRL2_DUR_STANDBY1_VAL             (1 << 8)
+#define PWR_CTRL2_CORE2_UP_RATIO               (1 << 4)
+#define PWR_CTRL2_CORE1_UP_RATIO               (1 << 0)
+
 /*
  * Let each supported clock get a unique id. This id is used to lookup

the clock

drivers/clk/samsung/clk-exynos5250.c line 87

Quoted 1 line

drivers/clk/samsung/clk-exynos5250.c +0 -0

  * for device tree based platforms. The clocks are categorized into

three

drivers/clk/samsung/clk-exynos5250.c void __init exynos5250_clk_init(struct device_node

Quoted 10 lines

drivers/clk/samsung/clk-exynos5250.c +2 -0

@@ -110,6 +129,8 @@ enum exynos5250_clks {
 static __initdata unsigned long exynos5250_clk_regs[] = {
        SRC_CPU,
        DIV_CPU0,
+       PWR_CTRL1,
+       PWR_CTRL2,
        SRC_CORE1,
        SRC_TOP0,
        SRC_TOP2,

@@ -474,6 +495,7 @@ void __init exynos5250_clk_init(struct device_node

*np)

Quoted 5 lines

drivers/clk/samsung/clk-exynos5250.c +1 -0

 {
        void __iomem *reg_base;
        struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+       unsigned int tmp;
 

drivers/clk/samsung/clk-exynos5250.c void __init exynos5250_clk_init(struct device_node

Quoted 3 lines

drivers/clk/samsung/clk-exynos5250.c +0 -0

        if (np) {
                reg_base = of_iomap(np, 0);

@@ -516,6 +538,26 @@ void __init exynos5250_clk_init(struct device_node

*np)

Quoted 20 lines

drivers/clk/samsung/clk-exynos5250.c +17 -0

        samsung_clk_register_gate(exynos5250_gate_clks,
                        ARRAY_SIZE(exynos5250_gate_clks));
 
+       /*
+        * Enable arm clock down (in idle) and set arm divider
+        * ratios in WFI/WFE state.
+        */
+       tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
+               PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
+               PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
+               PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
+       __raw_writel(tmp, reg_base + PWR_CTRL1);
+
+       /*
+        * Enable arm clock up (on exiting idle). Set arm divider
+        * ratios when not in idle along with the standby duration
+        * ratios.
+        */
+       tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
+               PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL

Quoted 11 lines

drivers/clk/samsung/clk-exynos5250.c +3 -1

+               PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
+       __raw_writel(tmp, reg_base + PWR_CTRL2);
+
        pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
                        _get_rate("armclk"));
 }
--

1.7.1

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soc" in

Quoted 2 lines

the body of a message to majordomo at vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform.

Cc Abhilash Kesavan <[email protected]>

Cc Thomas Abraham <[email protected]>

Signed-off-by Amit Daniel Kachhap <[email protected]>

Quoted 8 lines · Amit Daniel Kachhap

Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform.

Cc Abhilash Kesavan <[email protected]>

Cc Thomas Abraham <[email protected]>

Signed-off-by Amit Daniel Kachhap <[email protected]>

Hmm...I'm not sure it's better to handle the ARM core power down clock in common clock but the clock registers should be handled in one part, clock.

Acked-by Kukjin Kim <[email protected]>

Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this moment, so this patch will not create any conflict between samsung and clk.

Thanks,
- Kukjin

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Quoted 8 lines · Amit Daniel Kachhap

Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform.

Cc Abhilash Kesavan <[email protected]>

Cc Thomas Abraham <[email protected]>

Signed-off-by Amit Daniel Kachhap <[email protected]>

Hmm...I'm not sure it's better to handle the ARM core power down clock in common clock but the clock registers should be handled in one part, clock.

Acked-by Kukjin Kim <[email protected]>

Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this moment, so this patch will not create any conflict between samsung and clk.

Thanks,
- Kukjin

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Hi Mike,

Please merge this patch as it is pending since last merge window.

Thanks,
Amit

Quoted 20 lines · Kukjin Kim

Quoted 8 lines · Amit Daniel Kachhap

Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform.

Cc Abhilash Kesavan <[email protected]>

Cc Thomas Abraham <[email protected]>

Signed-off-by Amit Daniel Kachhap <[email protected]>

Hmm...I'm not sure it's better to handle the ARM core power down clock in common clock but the clock registers should be handled in one part, clock.

Acked-by Kukjin Kim <[email protected]>

Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this moment, so this patch will not create any conflict between samsung and clk.

Thanks,
- Kukjin

Hi,

Mike:

Could you please apply this patch? It is few months overdue..

Amit:

This patch no longer applies to -next. Could you please refresh and resend it?

You can add:

Reviewed-by Bartlomiej Zolnierkiewicz <[email protected]>

while at it.

Thanks.

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Quoted 28 lines · amit daniel kachhap

Hi Mike,

Please merge this patch as it is pending since last merge window.

Thanks,
Amit

Quoted 20 lines · Kukjin Kim

Quoted 8 lines · Amit Daniel Kachhap

Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform.

Cc Abhilash Kesavan <[email protected]>

Cc Thomas Abraham <[email protected]>

Signed-off-by Amit Daniel Kachhap <[email protected]>

Hmm...I'm not sure it's better to handle the ARM core power down clock in common clock but the clock registers should be handled in one part, clock.

Acked-by Kukjin Kim <[email protected]>

Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this moment, so this patch will not create any conflict between samsung and clk.

Thanks,
- Kukjin

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Hi,

Mike:

Could you please apply this patch? It is few months overdue..

Amit:

This patch no longer applies to -next. Could you please refresh and resend it?

You can add:

Reviewed-by Bartlomiej Zolnierkiewicz <[email protected]>

while at it.

Thanks.

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Quoted 28 lines · amit daniel kachhap

Hi Mike,

Please merge this patch as it is pending since last merge window.

Thanks,
Amit

Quoted 20 lines · Kukjin Kim

Quoted 8 lines · Amit Daniel Kachhap

Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform.

Cc Abhilash Kesavan <[email protected]>

Cc Thomas Abraham <[email protected]>

Signed-off-by Amit Daniel Kachhap <[email protected]>

Hmm...I'm not sure it's better to handle the ARM core power down clock in common clock but the clock registers should be handled in one part, clock.

Acked-by Kukjin Kim <[email protected]>

Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this moment, so this patch will not create any conflict between samsung and clk.

Thanks,
- Kukjin

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel