Allwinner R329/D1/R528/T113s Dual/Quad SPI modes support
Subsystems (4)
cover Allwinner R329/D1/R528/T113s Dual/Quad SPI modes support
This series extends the previous https://lore.kernel.org/all/[email protected]
And adds support for Dual and Quad SPI modes for the listed SoCs.
Both modes have been tested on the T113s and should work on
other Allwinner's SoCs that have a similar SPI conttoller.
It may also work for previous SoCs that support Dual/Quad modes.
One of them are H6 and H616.
Maksim Kiselev (3):
spi: sun6i: add quirk for dual and quad SPI modes support
spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s
riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port
.../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++ drivers/spi/spi-sun6i.c | 30 ++++++++++++++++--- 2 files changed, 33 insertions(+), 4 deletions(-)
Signature · 1 line
2.39.2
PATCH 1/3 spi: sun6i: add quirk for dual and quad SPI modes support
New Allwinner's SPI controllers can support dual and quad SPI modes. To enable one of these modes, we should set the corresponding bit in the SUN6I_BURST_CTL_CNT_REG register. DRM (28 bits) for dual mode and Quad_EN (29 bits) for quad transmission.
--- drivers/spi/spi-sun6i.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-)
drivers/spi/spi-sun6i.c +25 -4
@@ -83,6 +83,9 @@#define SUN6I_XMIT_CNT_REG 0x34#define SUN6I_BURST_CTL_CNT_REG 0x38 +#define SUN6I_BURST_CTL_CNT_STC_MASK GENMASK(23, 0) +#define SUN6I_BURST_CTL_CNT_DRM BIT(28) +#define SUN6I_BURST_CTL_CNT_QUAD_EN BIT(29)#define SUN6I_TXDATA_REG 0x200#define SUN6I_RXDATA_REG 0x300
@@ -90,6 +93,7 @@struct sun6i_spi_cfg {unsigned long fifo_depth;bool has_clk_ctl; +u32 mode_bits; };struct sun6i_spi {
@@ -266,7 +270,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,unsigned int div, div_cdr1, div_cdr2, timeout;unsigned int start, end, tx_time;unsigned int trig_level; -unsigned int tx_len =0 , rx_len =0 ; +unsigned int tx_len =0 , rx_len =0 , nbits =0 ;bool use_dma;int ret =0 ;u32 reg;
@@ -418,13 +422,29 @@ static int sun6i_spi_transfer_one(struct spi_master *master,sun6i_spi_write (sspi,SUN6I_GBL_CTL_REG , reg);/* Setup the transfer now... */ -if (sspi->tx_buf) +if (sspi->tx_buf) { tx_len = tfr->len; + nbits = tfr->tx_nbits; + }else if (tfr->rx_buf) { + nbits = tfr->rx_nbits; + } + +switch (nbits) { +case SPI_NBITS_DUAL : + reg =SUN6I_BURST_CTL_CNT_DRM ; +break ; +case SPI_NBITS_QUAD : + reg =SUN6I_BURST_CTL_CNT_QUAD_EN ; +break ; +case SPI_NBITS_SINGLE : +default : + reg =FIELD_PREP (SUN6I_BURST_CTL_CNT_STC_MASK , tx_len); + }/* Setup the counters */ +sun6i_spi_write (sspi,SUN6I_BURST_CTL_CNT_REG , reg);sun6i_spi_write (sspi,SUN6I_BURST_CNT_REG , tfr->len);sun6i_spi_write (sspi,SUN6I_XMIT_CNT_REG , tx_len); -sun6i_spi_write (sspi,SUN6I_BURST_CTL_CNT_REG , tx_len);if (!use_dma) {/* Fill the TX FIFO */
@@ -623,7 +643,8 @@ static int sun6i_spi_probe(struct platform_device *pdev) master->set_cs = sun6i_spi_set_cs; master->transfer_one = sun6i_spi_transfer_one; master->num_chipselect =4 ; - master->mode_bits =SPI_CPOL |SPI_CPHA |SPI_CS_HIGH |SPI_LSB_FIRST ; + master->mode_bits =SPI_CPOL |SPI_CPHA |SPI_CS_HIGH |SPI_LSB_FIRST | + sspi->cfg->mode_bits; master->bits_per_word_mask =SPI_BPW_MASK (8 ); master->dev.of_node = pdev->dev.of_node; master->auto_runtime_pm = true;
Signature · 1 line
2.39.2
Re: [PATCH v1 1/3] spi: sun6i: add quirk for dual and quad SPI modes support
…
Quoted 1 line
To enable one of these modes, we should set the corresponding bit …
Please choose imperative change suggestions.
Regards,
Markus
PATCH 2/3 spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s
In reply to Maksim KiselevListed SoCs have SPI controllers that can operate in dual or quad modes. This patch adds dual/quad mode bits for spi_master on these SoCS.
--- drivers/spi/spi-sun6i.c | 1 + 1 file changed, 1 insertion(+)
drivers/spi/spi-sun6i.c +1 -0
@@ -761,6 +761,7 @@ static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = {static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = { .fifo_depth =SUN8I_FIFO_DEPTH , + .mode_bits =SPI_RX_DUAL |SPI_TX_DUAL |SPI_RX_QUAD |SPI_TX_QUAD , };static const struct of_device_id sun6i_spi_match[] = {
Signature · 1 line
2.39.2
PATCH 3/3 riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port
In reply to Maksim KiselevAdd pinmux node that describes pins on PC port which required for QSPI mode.
--- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +7 -0
@@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { pins = "PB6", "PB7"; function = "uart3"; }; + + /omit-if-no-ref/ + qspi0_pc_pins: qspi0-pc-pins { + pins = "PC2", "PC3", "PC4", "PC5", "PC6", + "PC7"; + function = "spi0"; + }; }; ccu: clock-controller@2001000 {
Signature · 1 line
2.39.2
Jernej Škrabec
maintainerRe: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port
Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a):
Quoted 14 lines
Add pinmux node that describes pins on PC port which required for QSPI mode.
Signed-off-by Maksim Kiselev <[email protected]>--- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)(quoted diff) +0
-0
b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsiindex1bb1e5cae602..9f754dd03d85100644
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi uart3_pb_pins: uart3-pb-pins { · line 137
Quoted 7 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +4
-0@@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { pins = "PB6", "PB7"; function = "uart3"; }; + + /omit-if-no-ref/ + qspi0_pc_pins: qspi0-pc-pins { + pins = "PC2", "PC3", "PC4", "PC5",
"PC6",
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi uart3_pb_pins: uart3-pb-pins { · line 140
Quoted 3 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +3
-0+ "PC7"; + function = "spi0"; + };
Sorry for late review, but it seems I'm missing something. D1 manual says those are pins for ordinary SPI, with HOLD and WP signals. Can they be repurposed for quad SPI?
Best regards,
Jernej
Quoted 3 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +0
-0}; ccu: clock-controller@2001000 {
Re: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port
пн, 31 июл. 2023 г. в 01:30, Jernej Škrabec <[email protected]>:
Quoted 24 lines
Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a):
Quoted 14 lines
Add pinmux node that describes pins on PC port which required for QSPI mode.
Signed-off-by Maksim Kiselev <[email protected]>--- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)(quoted diff) +0
-0
b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsiindex1bb1e5cae602..9f754dd03d85100644arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi uart3_pb_pins: uart3-pb-pins { · line 137
Quoted 7 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +4
-0@@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { pins = "PB6", "PB7"; function = "uart3"; }; + + /omit-if-no-ref/ + qspi0_pc_pins: qspi0-pc-pins { + pins = "PC2", "PC3", "PC4", "PC5","PC6",
Quoted 8 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi uart3_pb_pins: uart3-pb-pins { · line 140
Quoted 3 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +3
-0+ "PC7"; + function = "spi0"; + };Sorry for late review, but it seems I'm missing something. D1 manual says those are pins for ordinary SPI, with HOLD and WP signals. Can they be repurposed for quad SPI?
Yes, they can. Here is a quote from D1 datasheet (9.3.3.8 SPI Quad-Input/Quad-Output Mode):
"Using the quad mode allows data to be transferred to or from the device at 4 times the rate of standard single mode, the data can be read
at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3 (HOLD#)) at the same time."
Re: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port
Dne ponedeljek, 31. julij 2023 ob 17:22:11 CEST je Maxim Kiselev napisal(a):
Quoted 38 lines
пн, 31 июл. 2023 г. в 01:30, Jernej Škrabec <[email protected]>:
Quoted 29 lines
Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a):
Quoted 15 lines
Add pinmux node that describes pins on PC port which required for QSPI mode.
Signed-off-by Maksim Kiselev <[email protected]>---
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)(quoted diff) +0
-0
b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsiindex1bb1e5cae602..9f754dd03d85100644arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi uart3_pb_pins: uart3-pb-pins { · line 140
Quoted 10 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +4
-0@@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { pins = "PB6", "PB7"; function = "uart3"; }; + + /omit-if-no-ref/ + qspi0_pc_pins: qspi0-pc-pins { + pins = "PC2", "PC3", "PC4", "PC5","PC6",
Quoted 7 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi uart3_pb_pins: uart3-pb-pins { · line 140
Quoted 3 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +3
-0+ "PC7"; + function = "spi0"; + };Sorry for late review, but it seems I'm missing something. D1 manual says those are pins for ordinary SPI, with HOLD and WP signals. Can they be repurposed for quad SPI?
Quoted 7 lines
Yes, they can. Here is a quote from D1 datasheet (9.3.3.8 SPI Quad-Input/Quad-Output Mode):
"Using the quad mode allows data to be transferred to or from the device at 4 times the rate of standard single mode, the data can be read
at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3 (HOLD#)) at the same time."
Alright then.
Best regards,
Jernej
Mark Brown
maintainerRe: (subset) [PATCH v1 0/3] Allwinner R329/D1/R528/T113s Dual/Quad SPI modes support
In reply to Maksim KiselevQuoted 8 lines · Maksim Kiselev
This series extends the previous https://lore.kernel.org/all/[email protected]
And adds support for Dual and Quad SPI modes for the listed SoCs.
Both modes have been tested on the T113s and should work on
other Allwinner's SoCs that have a similar SPI conttoller.
It may also work for previous SoCs that support Dual/Quad modes.
One of them are H6 and H616.[...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/3] spi: sun6i: add quirk for dual and quad SPI modes support
commit: 0605d9fb411f3337482976842a3901d6c125d298
[2/3] spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s
commit: 25453d797d7abe8801951c8290ea11ea8bba7b96All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks,
Mark