support 64 bit pci_alloc_consistent

This is patch which provides support for 64 bit address allocations from pci_alloc_consistent(), based on the address mask set through pci_set_consistent_dma_mask().

Hi Linus,

This is patch which provides support for 64 bit address allocations from pci_alloc_consistent(), based on the address mask set through pci_set_consistent_dma_mask(). This is necessary on some platforms which are unable to provide physical memory in the lower 4GB block and do not provide IOMMU support for cards operating in certain bus modes, such as PCI-X on the SGI SN2.

The default mask for pci_alloc_consistent() is still 32 bit as there are 64 bit capable hardware out there that doesn't support 64 bit addresses for descripters etc. Likewise, platforms which provide IOMMU support in all bus modes can ignore struct pci_dev->consistent_dma_mask and just return a 32 bit address as before.

The patch also includes changes to tg3.c to make it use the new api as well as a documentation update. I have done my best on the documentation part, if anyone feel the can make my scribbles clearer, please do.

Thanks to Dave Miller, Grant Grundler, James Bottomley, Colin Ngam, and Jeremy Higdon for input and code/documentation portions.

This patch should apply cleanly to 2.5.69-bk12.

Thanks,
Jes

diff -urN -X /home/jes/exclude-linux linux-2.5.69-030509-vanilla/Documentation/DMA-mapping.txt linux-2.5.69-pci/Documentation/DMA-mapping.txt

Documentation/DMA-mapping.txt +51 -13

@@ -83,6 +83,15 @@
 to be increased.  And for a device with limitations, as discussed in
 the previous paragraph, it needs to be decreased.
 
+pci_alloc_consistent() by default will return 32-bit DMA addresses.
+PCI-X specification requires PCI-X devices to support 64-bit
+addressing (DAC) for all transactions. And at least one platform (SGI
+SN2) requires 64-bit consistent allocations to operate correctly when
+the IO bus is in PCI-X mode. Therefore, like with pci_set_dma_mask(),
+it's good practice to call pci_set_consistent_dma_mask() to set the
+appropriate mask even if your device only supports 32-bit DMA
+(default) and especially if it's a PCI-X device.
+
 For correct operation, you must interrogate the PCI layer in your
 device probe routine to see if the PCI controller on the machine can
 properly support the DMA addressing limitation your device has.  It is

@@ -94,6 +103,11 @@
 
 	int pci_set_dma_mask(struct pci_dev *pdev, u64 device_mask);
 
+The query for consistent allocations is performed via a a call to
+pci_set_consistent_dma_mask():
+
+	int pci_set_consistent_dma_mask(struct pci_dev *pdev, u64 device_mask);
+
 Here, pdev is a pointer to the PCI device struct of your device, and
 device_mask is a bit mask describing which bits of a PCI address your
 device supports.  It returns zero if your card can perform DMA

@@ -133,7 +147,7 @@
 Sparc64 is one platform which behaves in this way.
 
 Here is how you would handle a 64-bit capable device which can drive
-all 64-bits during a DAC cycle:
+all 64-bits when accessing streaming DMA:
 
 	int using_dac;
 

@@ -147,6 +161,30 @@
 		goto ignore_this_device;
 	}
 
+If a card is capable of using 64-bit consistent allocations as well,
+the case would look like this:
+
+	int using_dac, consistent_using_dac;
+
+	if (!pci_set_dma_mask(pdev, 0xffffffffffffffff)) {
+		using_dac = 1;
+	   	consistent_using_dac = 1;
+		pci_set_consistent_dma_mask(pdev, 0xffffffffffffffff)
+	} else if (!pci_set_dma_mask(pdev, 0xffffffff)) {
+		using_dac = 0;
+		consistent_using_dac = 0;
+		pci_set_consistent_dma_mask(pdev, 0xffffffff)
+	} else {
+		printk(KERN_WARNING
+		       "mydev: No suitable DMA available.\n");
+		goto ignore_this_device;
+	}
+
+pci_set_consistent_dma_mask() will always be able to set the same or a
+smaller mask as pci_set_dma_mask(). However for the rare case that a
+device driver only uses consistent allocations, one would have to
+check the return value from pci_set_consistent().
+
 If your 64-bit device is going to be an enormous consumer of DMA
 mappings, this can be problematic since the DMA mappings are a
 finite resource on many platforms.  Please see the "DAC Addressing

@@ -215,9 +253,10 @@
 
   Think of "consistent" as "synchronous" or "coherent".
 
-  Consistent DMA mappings are always SAC addressable.  That is
-  to say, consistent DMA addresses given to the driver will always
-  be in the low 32-bits of the PCI bus space.
+  The current default is to return consistent memory in the low 32
+  bits of the PCI bus space.  However, for future compatibility you
+  should set the consistent mask even if this default is fine for your
+  driver.
 
   Good examples of what to use consistent mappings for are:
 

@@ -287,15 +326,14 @@
 driver needs regions sized smaller than a page, you may prefer using
 the pci_pool interface, described below.
 
-The consistent DMA mapping interfaces, for non-NULL dev, will always
-return a DMA address which is SAC (Single Address Cycle) addressable.
-Even if the device indicates (via PCI dma mask) that it may address
-the upper 32-bits and thus perform DAC cycles, consistent allocation
-will still only return 32-bit PCI addresses for DMA.  This is true
-of the pci_pool interface as well.
-
-In fact, as mentioned above, all consistent memory provided by the
-kernel DMA APIs are always SAC addressable.
+The consistent DMA mapping interfaces, for non-NULL dev, will by
+default return a DMA address which is SAC (Single Address Cycle)
+addressable.  Even if the device indicates (via PCI dma mask) that it
+may address the upper 32-bits and thus perform DAC cycles, consistent
+allocation will only return > 32-bit PCI addresses for DMA if the
+consistent dma mask has been explicitly changed via
+pci_set_consistent_dma_mask().  This is true of the pci_pool interface
+as well.
 
 pci_alloc_consistent returns two values: the virtual address which you
 can use to access it from the CPU and dma_handle which you pass to the

diff -urN -X /home/jes/exclude-linux linux-2.5.69-030509-vanilla/drivers/net/tg3.c linux-2.5.69-pci/drivers/net/tg3.c

drivers/net/tg3.c +7 -2

@@ -6400,8 +6400,7 @@
 	tw32(BUFMGR_MODE, 0);
 	tw32(FTQ_RESET, 0);
 
-	/* pci_alloc_consistent gives only non-DAC addresses */
-	test_desc.addr_hi = 0;
+	test_desc.addr_hi = ((u64) buf_dma) >> 32;
 	test_desc.addr_lo = buf_dma & 0xffffffff;
 	test_desc.nic_mbuf = 0x00002100;
 	test_desc.len = size;

@@ -6743,6 +6742,12 @@
 	/* Configure DMA attributes. */
 	if (!pci_set_dma_mask(pdev, (u64) 0xffffffffffffffff)) {
 		pci_using_dac = 1;
+		if (pci_set_consistent_dma_mask(pdev,
+						(u64) 0xffffffffffffffff)) {
+			printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
+			       "for consistent allocations\n");
+			goto err_out_free_res;
+		}
 	} else {
 		err = pci_set_dma_mask(pdev, (u64) 0xffffffff);
 		if (err) {

diff -urN -X /home/jes/exclude-linux linux-2.5.69-030509-vanilla/drivers/pci/pci.c linux-2.5.69-pci/drivers/pci/pci.c

drivers/pci/pci.c +12 -0

@@ -701,6 +701,17 @@
 	return 0;
 }
 
+int
+pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
+{
+	if (!pci_dma_supported(dev, mask))
+		return -EIO;
+
+	dev->consistent_dma_mask = mask;
+
+	return 0;
+}
+     
 static int __devinit pci_init(void)
 {
 	struct pci_dev *dev;

@@ -751,6 +762,7 @@
 EXPORT_SYMBOL(pci_clear_mwi);
 EXPORT_SYMBOL(pci_set_dma_mask);
 EXPORT_SYMBOL(pci_dac_set_dma_mask);
+EXPORT_SYMBOL(pci_set_consistent_dma_mask);
 EXPORT_SYMBOL(pci_assign_resource);
 EXPORT_SYMBOL(pci_find_parent_resource);
 

diff -urN -X /home/jes/exclude-linux linux-2.5.69-030509-vanilla/drivers/pci/probe.c linux-2.5.69-pci/drivers/pci/probe.c

drivers/pci/probe.c +1 -0

@@ -502,6 +502,7 @@
 	/* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
 	   set this higher, assuming the system even supports it.  */
 	dev->dma_mask = 0xffffffff;
+	dev->consistent_dma_mask = 0xffffffff;
 	if (pci_setup_device(dev) < 0) {
 		kfree(dev);
 		return NULL;

diff -urN -X /home/jes/exclude-linux linux-2.5.69-030509-vanilla/include/linux/pci.h linux-2.5.69-pci/include/linux/pci.h

include/linux/pci.h +6 -1

@@ -390,6 +390,11 @@
 					   or supports 64-bit transfers.  */
 	struct list_head pools;		/* pci_pools tied to this device */
 
+	u64		consistent_dma_mask;/* Like dma_mask, but for
+					       pci_alloc_consistent mappings as
+					       not all hardware supports
+					       64 bit addresses for consistent
+					       allocations such descriptors. */
 	u32             current_state;  /* Current operating state. In ACPI-speak,
 					   this is D0-D3, D0 being fully functional,
 					   and D3 being off. */

@@ -614,6 +619,7 @@
 void pci_clear_mwi(struct pci_dev *dev);
 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
 int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask);
+int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
 int pci_assign_resource(struct pci_dev *dev, int i);
 
 /* Power management related routines */
 
-

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Hi Linus,

This is patch which provides support for 64 bit address allocations from pci_alloc_consistent(), based on the address mask set through pci_set_consistent_dma_mask(). This is necessary on some platforms which are unable to provide physical memory in the lower 4GB block and do not provide IOMMU support for cards operating in certain bus modes, such as PCI-X on the SGI SN2.

WHile logically you are correct, the probing code is going to look basically identical.

Most drivers will just say "look I
can do THIS much. I don't give a flying fish about how much of that you actually use". At least in the probing code.

Quoted 3 lines · Arjan van de Ven

Most drivers will just say "look I
can do THIS much. I don't give a flying fish about how much of that you actually use". At least in the probing code.

The platform code needs a way to indicate the given mask will not work. Rejecting proposals by the driver seems reasonable if the driver only supports two different masks anyway (eg 64 and 32-bit).

In the case of a platform requiring 64-bit masks for consistent mappings, the platform DMA code must reject proposals for non-64-bit DMA masks. (eg PCI-X device implementing less than 64-bits)

In both cases the driver will care because it will crash the box otherwise.

In that case, the platform returns zero to "this much" being less than the full 64 bits implying there's no mask the platform and driver can agree on.

Quoted 3 lines · James Bottomley

In that case, the platform returns zero to "this much" being less than the full 64 bits implying there's no mask the platform and driver can agree on.

My point was it's better if the driver always check the return value regardless of which interface is ultimately agreed upon. (in reference to whether "no one cares a flying fish".)

If one accepts that requirement, the only improvement in Arjen's proposal is the platform DMA support can guess what might be better and make that the "effective" mask. The driver still needs to check the effective mask. I happen to agree with davem : redefining this interface in 2.5 for a trivial improvement doesn't seem reasonable at this point.

A full bit u64 mask should never fail...

Also, knowing the effective mask (and it would have to be set properly on return) would be extremely useful for drivers that have weird width modes (like aic with 64 vs 39 vs 32 bit addressing in the descriptors)

...it would allow me to eliminate the memory size checks in those drivers.

An interface like

#define PCI_DMA_64BIT 0xffffffffffffffffULL
#define PCI_DMA_32BIT 0xffffffffULL

void pci_set_dma_capabilities(device,

               u64 streaming_mask, u64 persistent_mask);

u64 pci_get_effective_streaming_mask(device);
u64 pci_get_effective_persistent_mask(device);

(it uses 32 bit addr and 32 bit len descriptors, but reduces len to 24 bits to steal the extra byte for 7 bits extra addressing). However, it is forced to request the full 64 bit address mask---I've never worked out what will happen to it on a machine with more than 512GB memory.

Quoted 4 lines · James Bottomley

(it uses 32 bit addr and 32 bit len descriptors, but reduces len to 24 bits to steal the extra byte for 7 bits extra addressing). However, it is forced to request the full 64 bit address mask---I've never worked out what will happen to it on a machine with more than 512GB memory.

Uh??? right now even in 2.4 arbitrary bitmasks are supported for non-coherent memory.