1/3 Support mpc823 board dbox2 (2.4.22-pre6)
PATCH 1/1 1/3 Support mpc823 board dbox2 (2.4.22-pre6)
Hi,
This patch adds basic support for the dbox2, a dvb receiver (set top box). It has been tested by a large user base and is stable since 2.4.2. The following two patches rely on it.
Regards,
Andreas
arch/ppc/boot/simple/embed_config.c +9 -0
@@ -755,3 +755,12 @@ }#endif +#ifdef CONFIG_DBOX2 +/* dbox2 +* doesn't do anything right now */ +void +embed_config (bd_t **bdp) +{ +} +#endif +
arch/ppc/config.in +1 -0
@@ -75,6 +75,7 @@ RPX-Classic CONFIG_RPXCLASSIC \ BSE-IP CONFIG_BSEIP \ FADS CONFIG_FADS \ + DBOX2 CONFIG_DBOX2 \ TQM823L CONFIG_TQM823L \ TQM850L CONFIG_TQM850L \ TQM855L CONFIG_TQM855L \
arch/ppc/platforms/dbox2.h +24 -0
@@ -0,0 +1,24 @@ +/* +* D-BOX2 board specific definitions +* +* Copyright (c) 2001-2002 Florian Schirmer ([email protected]) +*/ + +#ifndef __MACH_DBOX2_H +#define __MACH_DBOX2_H + +#include <linux/config.h> + +#include <asm/ppcboot.h> + +#define DBOX2_IMMR_BASE 0xFF000000/* phys. addr of IMMR */ +#define DBOX2_IMAP_SIZE (64 * 1024)/* size of mapped area */ + +#define IMAP_ADDR DBOX2_IMMR_BASE/* physical base address of IMMR area */ +#define IMAP_SIZE DBOX2_IMAP_SIZE/* mapped size of IMMR area */ + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +#endif /* __MACH_DBOX2_H */
include/asm-ppc/commproc.h +17 -0
@@ -466,6 +466,23 @@#define SICR_ENET_CLKRT ((uint)0x0000003d)#endif /* CONFIG_RPXCLASSIC */ +/*** D-BOX2 ***********************************************/ + +#ifdef CONFIG_DBOX2 + +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_RCLK ((ushort)0x0200) +#define PA_ENET_TCLK ((ushort)0x0800) + +#define PC_ENET_TENA ((ushort)0x0002) +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00003d00) +#endif /* CONFIG_DBOX2 */ +/*** TQM823L, TQM850L ***********************************************/ #if defined(CONFIG_TQM823L ) || defined(CONFIG_TQM850L )
include/asm-ppc/mpc8xx.h +4 -0
@@ -32,6 +32,10 @@#include <platforms/rpxclassic.h> #endif +#ifdef CONFIG_DBOX2 +#include <platforms/dbox2.h> +#endif +#if defined(CONFIG_TQM8xxL)#include <platforms/tqm8xx.h> #endif
PATCH 1/1 2/3 Support mpc8xx watchdog of dbox2 (2.4.22-pre6)
This one adds support for the watchdog timer which is unfortunately active before the kernel starts and can not be disabled without patching the binary bootloader.
arch/ppc/kernel/m8xx_setup.c +56 -0
@@ -117,6 +117,22 @@printk ("timebase_interrupt()\n" ); } +#ifdef CONFIG_DBOX2 +void m8xx_reset_watchdog (void ) +{ + ((volatile immap_t *)IMAP_ADDR )->im_siu_conf.sc_swsr =0x556c ;/* write magic1 */ + ((volatile immap_t *)IMAP_ADDR )->im_siu_conf.sc_swsr =0xaa39 ;/* write magic2 */ +} + +void pit_interrupt (int irq,void * dev,struct pt_regs * regs) +{ +m8xx_reset_watchdog (); + +/* clear irq */ + ((volatile immap_t *)IMAP_ADDR )->im_sit.sit_piscr |=PISCR_PS ; +} +#endif +/* The decrementer counts at the system (internal) clock frequency divided by * sixteen, or external oscillator divided by four. We force the processor * to use system clock divided by sixteen.
@@ -125,6 +141,10 @@ {bd_t *binfo = (bd_t *)__res;int freq, fp, divisor; +#ifdef CONFIG_DBOX2 +unsigned long sypcr; +unsigned short pitc, swtc, swp; +#endif /* Unlock the SCCR. */ ((volatile immap_t *)IMAP_ADDR )->im_clkrstk.cark_sccrk = ~KAPWR_KEY ;
@@ -184,6 +204,42 @@if (request_irq (DEC_INTERRUPT , timebase_interrupt,0 ,"tbint" ,NULL ) !=0 )panic ("Could not allocate timer IRQ!" ); + +#ifdef CONFIG_DBOX2 + sypcr = ((volatile immap_t *)IMAP_ADDR )->im_siu_conf.sc_sypcr; + +if ((sypcr >>2 ) &0x1 ) { +m8xx_reset_watchdog (); + +if (sypcr >>16 ) + swtc = sypcr >>16 ; +else + swtc =0xFFFF ; + +if (sypcr &0x1 ) + swp =2048 ; +else + swp =1 ; + +#define PITRTCLK 8192 + +/* Fire trigger if half of the wdt ticked down */ +if ((swp * swtc) > (UINT_MAX /PITRTCLK )) + pitc = swtc * swp / binfo->bi_intfreq *PITRTCLK /2 ; +else + pitc =PITRTCLK * swtc * swp / binfo->bi_intfreq /2 ; + + ((volatile immap_t *)IMAP_ADDR )->im_sit.sit_pitc = pitc <<16 ; + ((volatile immap_t *)IMAP_ADDR )->im_sit.sit_piscr = (mk_int_int_mask (PIT_INTERRUPT ) <<8 ) |PISCR_PIE |PISCR_PTE ; + +if (request_8xxirq (PIT_INTERRUPT , pit_interrupt,0 ,"pit" ,NULL ) !=0 ) +panic ("mpc8xx-wdt: could not allocate pit irq!" ); + +printk (KERN_INFO "mpc8xx-wdt: active wdt found (SWTC: 0x%04X, SWP: 0x%01X)\n" , sypcr >>16 , sypcr &0x1 ); +printk (KERN_INFO "mpc8xx-wdt: keep-alive trigger activated (PITC: 0x%04X)\n" , pitc); + } +#endif + }/* The RTC on the MPC8xx is an internal register.
arch/ppc/kernel/time.c +7 -0
@@ -71,6 +71,10 @@extern int do_sys_settimeofday (struct timeval *tv,struct timezone *tz); +#ifdef CONFIG_DBOX2 +extern void m8xx_reset_watchdog (void ); +#endif +/* keep track of when we need to update the rtc */ time_t last_rtc_update;extern rwlock_t xtime_lock;
@@ -320,6 +324,9 @@ sec = ppc_md.get_rtc_time (); elapsed =0 ; do { +#ifdef CONFIG_DBOX2 + m8xx_reset_watchdog(); +#endif old_stamp = stamp; old_sec = sec; stamp = get_native_tbl();
PATCH 1/1 3/3 handle level triggered irqs on dbox2 (2.4.22-pre6)
In reply to Andreas OberritterThis one is for components of the dbox2 which cannot be set up to do edge triggered irqs because no documentation is available. #ifdef CONFIG_DBOX2 is put around it because other boards don't seem to need it. Is there a better way to handle level based interrupts?
arch/ppc/kernel/irq.c +8 -0
@@ -507,6 +507,14 @@else if (irq_desc[irq].handler->enable) irq_desc[irq].handler->enable (irq); } + +#ifdef CONFIG_DBOX2 +if (action) { +if (action->flags &SA_ONESHOT ) +disable_irq_nosync (irq); + } +#endif +spin_unlock (&desc->lock); }