2.6.x libata update
PATCH 1/1 2.6.x libata update
Please do a
bk pull bk://gkernel.bkbits.net/libata-2.5
This will update the following files:
drivers/scsi/ata_piix.c | 6 +++--- drivers/scsi/libata-core.c | 40 ++++++++++++++++++++++++++++++++++++++-- drivers/scsi/libata-scsi.c | 4 ++-- drivers/scsi/libata.h | 6 +++--- drivers/scsi/sata_promise.c | 2 +- drivers/scsi/sata_via.c | 4 ++-- include/linux/ata.h | 4 ++-- include/linux/libata.h | 4 ++-- 8 files changed, 53 insertions(+), 17 deletions(-)
through these ChangeSets:
<[email protected]> (04/02/13 1.1635)
Bump libata, ata_piix to version 1.0.
Also update copyrights for 2004.
<[email protected]> (04/02/13 1.1634)
[libata] catch, and ack, spurious DMA interrupts
Hardware issue on Intel ICH5 requires an additional ack sequence over and above the normal IDE DMA interrupt ack requirements. Issue described in post to freebsd list:
http://www.mail-archive.com/[email protected]/msg58421.html
Since the bug workaround only requires a single additional PIO or MMIO read in the interrupt handler, it is applied to all chipsets using the standard libata interrupt handler.
Credit for research the issue, creating the patch, and testing the patch all go to Jon Burgess.
drivers/scsi/ata_piix.c +3 -3
@@ -3,8 +3,8 @@ ata_piix.c - Intel PATA/SATA controllers - Copyright 2003 Red Hat Inc - Copyright 2003 Jeff Garzik + Copyright 2003-2004 Red Hat Inc + Copyright 2003-2004 Jeff Garzik Copyright header from piix.c:
@@ -28,7 +28,7 @@#include <linux/libata.h> #define DRV_NAME "ata_piix" -#define DRV_VERSION "0.95" +#define DRV_VERSION "1.00"enum {PIIX_IOCFG =0x54 ,/* IDE I/O configuration register */
drivers/scsi/libata-core.c +38 -2
@@ -1,8 +1,8 @@/* libata-core.c - helper library for ATA -Copyright 2003 Red Hat, Inc. All rights reserved. -Copyright 2003 Jeff Garzik +Copyright 2003-2004 Red Hat, Inc. All rights reserved. +Copyright 2003-2004 Jeff Garzik The contents of this file are subject to the Open Software License version 1.1 that can be found at
@@ -2386,6 +2386,41 @@ }/** +* ata_chk_spurious_int - Check for spurious interrupts +* @ap: port to which command is being issued +* +* Examines the DMA status registers and clears +* unexpected interrupts. Created to work around +* hardware bug on Intel ICH5, but is applied to all +* chipsets using the standard irq handler, just for safety. +* If the bug is not present, this is simply a single +* PIO or MMIO read addition to the irq handler. +* +* LOCKING: +*/ +static inline void ata_chk_spurious_int (struct ata_port *ap) { +int host_stat; + +if (ap->flags &ATA_FLAG_MMIO ) { +void *mmio = (void *) ap->ioaddr.bmdma_addr; + host_stat =readb (mmio +ATA_DMA_STATUS ); + }else + host_stat =inb (ap->ioaddr.bmdma_addr +ATA_DMA_STATUS ); + +if ((host_stat & (ATA_DMA_INTR |ATA_DMA_ERR |ATA_DMA_ACTIVE )) ==ATA_DMA_INTR ) { +if (ap->flags &ATA_FLAG_MMIO ) { +void *mmio = (void *) ap->ioaddr.bmdma_addr; +writeb (host_stat & ~ATA_DMA_ERR , mmio +ATA_DMA_STATUS ); + }else +outb (host_stat & ~ATA_DMA_ERR , ap->ioaddr.bmdma_addr +ATA_DMA_STATUS ); + +DPRINTK ("ata%u: Caught spurious interrupt, status 0x%X\n" , ap->id, host_stat); +udelay (1 ); + } +} + + +/** * ata_interrupt - * @irq: * @dev_instance:
@@ -2417,6 +2452,7 @@ qc =ata_qc_from_tag (ap, ap->active_tag);if (qc && ((qc->flags &ATA_QCFLAG_POLL ) ==0 )) handled +=ata_host_intr (ap, qc); +ata_chk_spurious_int (ap); } }
drivers/scsi/libata-scsi.c +2 -2
@@ -1,8 +1,8 @@/* libata-scsi.c - helper library for ATA -Copyright 2003 Red Hat, Inc. All rights reserved. -Copyright 2003 Jeff Garzik +Copyright 2003-2004 Red Hat, Inc. All rights reserved. +Copyright 2003-2004 Jeff Garzik The contents of this file are subject to the Open Software License version 1.1 that can be found at
drivers/scsi/libata.h +3 -3
@@ -1,8 +1,8 @@/* libata.h - helper library for ATA -Copyright 2003 Red Hat, Inc. All rights reserved. -Copyright 2003 Jeff Garzik +Copyright 2003-2004 Red Hat, Inc. All rights reserved. +Copyright 2003-2004 Jeff Garzik The contents of this file are subject to the Open Software License version 1.1 that can be found at
@@ -26,7 +26,7 @@#define __LIBATA_H__#define DRV_NAME "libata" -#define DRV_VERSION "0.81"/* must be exactly four chars */ +#define DRV_VERSION "1.00"/* must be exactly four chars */ struct ata_scsi_args {struct ata_port *ap;
drivers/scsi/sata_promise.c +1 -1
@@ -1,7 +1,7 @@/* * sata_promise.c - Promise SATA * -* Copyright 2003 Red Hat, Inc. +* Copyright 2003-2004 Red Hat, Inc. * * The contents of this file are subject to the Open * Software License version 1.1 that can be found at
drivers/scsi/sata_via.c +2 -2
@@ -1,8 +1,8 @@/* sata_via.c - VIA Serial ATA controllers -Copyright 2003 Red Hat, Inc. All rights reserved. -Copyright 2003 Jeff Garzik +Copyright 2003-2004 Red Hat, Inc. All rights reserved. +Copyright 2003-2004 Jeff Garzik The contents of this file are subject to the Open Software License version 1.1 that can be found at
include/linux/ata.h +2 -2
@@ -1,7 +1,7 @@/* -Copyright 2003 Red Hat, Inc. All rights reserved. -Copyright 2003 Jeff Garzik +Copyright 2003-2004 Red Hat, Inc. All rights reserved. +Copyright 2003-2004 Jeff Garzik The contents of this file are subject to the Open Software License version 1.1 that can be found at
include/linux/libata.h +2 -2
@@ -1,6 +1,6 @@/* -Copyright 2003 Red Hat, Inc. All rights reserved. -Copyright 2003 Jeff Garzik +Copyright 2003-2004 Red Hat, Inc. All rights reserved. +Copyright 2003-2004 Jeff Garzik The contents of this file are subject to the Open Software License version 1.1 that can be found at
On Fri, 2004-02-13 at 20:43, Jeff Garzik wrote:
Hi
Quoted 8 lines
<[email protected]> (04/02/13 1.1634)
[libata] catch, and ack, spurious DMA interruptsHardware issue on Intel ICH5 requires an additional ack sequence over and above the normal IDE DMA interrupt ack requirements. Issue described in post to freebsd list:
http://www.mail-archive.com/[email protected]/msg58421.html
Quoted 7 lines
Since the bug workaround only requires a single additional PIO or MMIO read in the interrupt handler, it is applied to all chipsets using the standard libata interrupt handler.
Credit for research the issue, creating the patch, and testing the patch all go to Jon Burgess.
Did you miss the mail I sent about this locking my box in under 20-30 mins? It still looks the same as the previous one ....
Thanks,
Signature · 1 line
Martin Schlemmer
Quoted 17 lines · Martin Schlemmer
On Fri, 2004-02-13 at 20:43, Jeff Garzik wrote:
Hi
Quoted 12 lines
<[email protected]> (04/02/13 1.1634)
[libata] catch, and ack, spurious DMA interruptsHardware issue on Intel ICH5 requires an additional ack sequence over and above the normal IDE DMA interrupt ack requirements. Issue described in post to freebsd list:
http://www.mail-archive.com/[email protected]/msg58421.htmlSince the bug workaround only requires a single additional PIO or MMIO read in the interrupt handler, it is applied to all chipsets using the standard libata interrupt handler.
Quoted 7 lines
Quoted 3 lines
Credit for research the issue, creating the patch, and testing the patch all go to Jon Burgess.
Did you miss the mail I sent about this locking my box in under 20-30 mins? It still looks the same as the previous one ....
Yes, I did. Can you test 2.6.3-rc2 + this patch?
Jeff
Quoted 23 lines · Jeff Garzik
Quoted 22 lines · Martin Schlemmer
On Fri, 2004-02-13 at 20:43, Jeff Garzik wrote:
Hi
Quoted 15 lines
<[email protected]> (04/02/13 1.1634)
[libata] catch, and ack, spurious DMA interruptsHardware issue on Intel ICH5 requires an additional ack sequence over and above the normal IDE DMA interrupt ack requirements. Issue described in post to freebsd list:
http://www.mail-archive.com/[email protected]/msg58421.htmlSince the bug workaround only requires a single additional PIO or MMIO read in the interrupt handler, it is applied to all chipsets using the standard libata interrupt handler.
Credit for research the issue, creating the patch, and testing the patch all go to Jon Burgess.
Quoted 6 lines
Quoted 2 lines
Did you miss the mail I sent about this locking my box in under 20-30 mins? It still looks the same as the previous one ....
Yes, I did. Can you test 2.6.3-rc2 + this patch?
Yep, it still breaks it. I get a dma timeout on heavy disk access, and then things start to freeze (or do not start at all). Seems Jon is hitting the same issue with -bk4.
If you need debugging/whatever, just let me know what to do
Thanks,
Signature · 1 line
Martin Schlemmer
Quoted 3 lines · Martin Schlemmer
Yep, it still breaks it. I get a dma timeout on heavy disk access, and then things start to freeze (or do not start at all). Seems Jon is hitting the same issue with -bk4.
Thanks for re-verifying. The buggy patch is now reverted upstream, and I'll be looking into another way to fix the "too many interrupts on ICH5" problem.
Jeff
Quoted 9 lines · Jeff Garzik
Quoted 3 lines · Martin Schlemmer
Yep, it still breaks it. I get a dma timeout on heavy disk access, and then things start to freeze (or do not start at all). Seems Jon is hitting the same issue with -bk4.
Thanks for re-verifying. The buggy patch is now reverted upstream, and I'll be looking into another way to fix the "too many interrupts on ICH5" problem.
Stupid question - its not maybe fixed in later revisions of the controller (also those this breaks)? I never had the heavy interrupts problem some seems to have ...
--
# cat /proc/interrupts
CPU0 CPU1
0: 64547502 64536877 IO-APIC-edge timer
2: 0 0 XT-PIC cascade
8: 6702 945 IO-APIC-edge rtc
9: 0 0 IO-APIC-level acpi
14: 244 142 IO-APIC-edge ide0
15: 35 62 IO-APIC-edge ide1
169: 1287568 1399519 IO-APIC-level libata, uhci_hcd, eth0
177: 746886 747222 IO-APIC-level Intel ICH5
185: 5637855 5624744 IO-APIC-level uhci_hcd, uhci_hcd, nvidia
193: 0 0 IO-APIC-level uhci_hcd
201: 0 0 IO-APIC-level ehci_hcd
NMI: 0 0
LOC: 129049693 129049832
ERR: 0
MIS: 0
--(yes, with the patch it happens without nvidia as well)
--
Bus 0, device 31, function 1:
IDE interface: Intel Corp. 82801EB Ultra ATA Storage Controller (rev 2).
IRQ 169.
I/O at 0xfc00 [0xfc0f].
Non-prefetchable 32 bit memory at 0x40000000 [0x400003ff].
Bus 0, device 31, function 2:
IDE interface: Intel Corp. 82801EB Ultra ATA Storage Controller (rev 2).
IRQ 169.
I/O at 0xefe0 [0xefe7].
I/O at 0xefac [0xefaf].
I/O at 0xefa0 [0xefa7].
I/O at 0xefa8 [0xefab].
I/O at 0xef90 [0xef9f].--
Signature · 1 line
Martin Schlemmer
The patch that was undone would take my box down within five minutes of a boot. All it took was some kernel compiles. I'm running a RAID-1 arrary between the SATA and ATA drives.
=====
Jon Smirl
[email protected]
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