arm64: dts: rockchip: rock-3b: Add phy-supply to pcie30phy
Subsystems (2)
PATCH 1/1 arm64: dts: rockchip: rock-3b: Add phy-supply to pcie30phy
The PCIe 3.0 PHY requires its power supply regulator to be enabled before initialization. Without the phy-supply property, the PHY driver does not ensure the regulator is enabled, causing SRAM initialization to timeout with "lock failed" errors:
phy phy-fe8c0000.phy.1: phy poweron failed --> -110 rockchip-snps-pcie3-phy fe8c0000.phy: PCIe3PHY lock failed 0x6890000 rockchip-pcie fe280000.pcie: phy init failed: -110
This results in NVMe devices in the M.2 slot not being detected.
Add phy-supply referencing vcc3v3_pi6c_03 regulator (which controls the PI6C PCIe clock generator power via GPIO0_D4) to ensure proper power sequencing during PHY initialization.
--- arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 1 + 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +1 -0
@@ -404,6 +404,7 @@ &pcie2x1 { }; &pcie30phy { + phy-supply = <&vcc3v3_pi6c_03>; status = "okay"; };
--
2.39.5
Hi
Quoted 11 lines · 在 2026/02/13 星期五 23:14, MidG971 写道:
The PCIe 3.0 PHY requires its power supply regulator to be enabled before initialization. Without the phy-supply property, the PHY driver does not ensure the regulator is enabled, causing SRAM initialization to timeout with "lock failed" errors:
phy phy-fe8c0000.phy.1: phy poweron failed --> -110 rockchip-snps-pcie3-phy fe8c0000.phy: PCIe3PHY lock failed 0x6890000 rockchip-pcie fe280000.pcie: phy init failed: -110This results in NVMe devices in the M.2 slot not being detected.
Quoted 8 lines
Add phy-supply referencing
vcc3v3_pi6c_03regulator (which controls the PI6C PCIe clock generator power viaGPIO0_D4) to ensure proper power sequencing during PHY initialization.Fixes 846ef7748fa9 ("arm64: dts: rockchip: Add Radxa ROCK 3B")Signed-off-by MidG971 <[email protected]>Co-developed-by Claude <[email protected]>Signed-off-by Claude <[email protected]>
Should put your SOB at last.
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts &pcie2x1 { · line 407
Quoted 13 lines
--- arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 1 + 1 file changed, 1 insertion(+)arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +1
-0@@ -404,6 +404,7 @@ &pcie2x1 { }; &pcie30phy { + phy-supply = <&vcc3v3_pi6c_03>;
As a fix which need to be backported, it looks fine for just one-line change.
However, the whole commit message is misleading. power supply for
pcie30phy is powred up with all other phys' when booting, for instance,
USB, otherwise all IP using PHY should not work, not just PCIe. So actually it's not the power but the input refclk, and apprently pi6c is a 100MHz clock generator which was designed to be a regulator by
mistake in the first place.
If you would like to clean it up later, you could use a gated-fixed-clock like:
https://lore.kernel.org/linux-rockchip/[email protected]/T/#u
Quoted 11 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +0
-1status = "okay"; }; --2.39.5
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Hi,
Quoted 7 lines · Shawn Lin
Hi
Quoted 4 lines · 在 2026/02/13 星期五 23:14, MidG971 写道:
The PCIe 3.0 PHY requires its power supply regulator to be enabled before initialization. Without the phy-supply property, the PHY driver does not ensure the regulator is enabled, causing SRAM initialization to timeout with "lock failed" errors:
This is incorrect, as already mentioned the ref clock is modeled as a regulator, and this regulator is both boot-on and always-on and should not be referenced as the phy-supply, and the reason why I did not do it in the initial board device tree submission.
Quoted 4 lines
Quoted 4 lines
phy phy-fe8c0000.phy.1: phy poweron failed --> -110 rockchip-snps-pcie3-phy fe8c0000.phy: PCIe3PHY lock failed 0x6890000 rockchip-pcie fe280000.pcie: phy init failed: -110
How did you manage to get this? Did you use wrong/bad boot firmware?
Please try mainline U-Boot for the ROCK 3B target, that will ensure that both the ref clock "regulator" and the two Ethernet phys are reset before entering Linux (or other OS) using the mainline Linux device tree for this board.
Quoted 6 lines
Quoted 6 lines
This results in NVMe devices in the M.2 slot not being detected.
Add phy-supply referencing
vcc3v3_pi6c_03regulator (which controls the PI6C PCIe clock generator power viaGPIO0_D4) to ensure proper power sequencing during PHY initialization.
As already mentioned, this is not a phy regulator so adding it as a phy-supply does not correctly reflect the hardware.
Quoted 18 lines
Quoted 4 lines
Fixes 846ef7748fa9 ("arm64: dts: rockchip: Add Radxa ROCK 3B")Signed-off-by MidG971 <[email protected]>Co-developed-by Claude <[email protected]>Signed-off-by Claude <[email protected]>Should put your SOB at last.
Quoted 11 lines
--- arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 1 + 1 file changed, 1 insertion(+)arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +0
-0@@ -404,6 +404,7 @@ &pcie2x1 { };
Quoted 5 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts &pcie2x1 { · line 407
Quoted 2 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +1
-0&pcie30phy { + phy-supply = <&vcc3v3_pi6c_03>;As a fix which need to be backported, it looks fine for just one-line change.
I disagree, as you mention below, and as mentioned in a comment in the device tree, the ref clk generator is modeled as a regulator that is boot-on and always-on that is normally enabled by boot firmware.
Quoted 9 lines
However, the whole commit message is misleading. power supply for pcie30phy is powred up with all other phys' when booting, for instance, USB, otherwise all IP using PHY should not work, not just PCIe. So actually it's not the power but the input refclk, and apprently pi6c is a 100MHz clock generator which was designed to be a regulator by mistake in the first place.
If you would like to clean it up later, you could use a gated-fixed-clock like:
Agree, if anything please re-model the ref clk regulator as a gated-fixed-clock instead of adding an incorrect phy-supply.
And please try mainline U-Boot targeted for you board if you intend on using mainline Linux for your board, should most likely fix your PCIe issue.
Regards,
Jonas
Quoted 9 lines
https://lore.kernel.org/linux-rockchip/[email protected]/T/#u
Quoted 5 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +0
-1status = "okay"; }; --2.39.5
PATCH v2 1/1 arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
In reply to MidG971The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (vcc3v3_pi6c_03), with no clock output representation.
The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips.
The regulator node is kept as-is since it controls the power supply to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node references this regulator as its vdd-supply and provides a proper 100MHz clock output. The pcie3x2 node is updated to include the reference clock, matching the approach used in rk3588-rock-5-itx.dts.
---
Changes since v1 [1]:
- Drop phy-supply approach entirely (Jonas, Shawn)
- Model PI6C20100 as gated-fixed-clock instead
- Wire reference clock to pcie3x2 controller
- Follow pattern from rk3588-rock-5-itx.dts
[1] https://lore.kernel.org/linux-rockchip/[email protected]/
.../arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +17 -1
@@ -56,7 +56,16 @@ }; }; - /* pi6c pcie clock generator */ + /* PI6C20100 PCIe reference clock buffer (100MHz) */ + pcie30_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_03>; + }; + + /* PI6C20100 power supply - active-high GPIO0_D4 */ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { compatible = "regulator-fixed"; enable-active-high;
@@ -553,6 +562,13 @@ }; &pcie3x2 { + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&pcie30_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
--
2.39.5
Re: [PATCH v2] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
Quoted 10 lines · 在 2026/03/04 星期三 21:29, MidG971 写道:
The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (
vcc3v3_pi6c_03), with no clock output representation.The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips.
Quoted 7 lines
The regulator node is kept as-is since it controls the power supply to the PI6C20100 chip via
GPIO0_D4. The new gated-fixed-clock node references this regulator as its vdd-supply and provides a proper 100MHz clock output. The pcie3x2 node is updated to include the reference clock, matching the approach used inrk3588-rock-5-itx.dts.Signed-off-by Claude <[email protected]>
IIUC, you are using Claude to help generate this patch, please describe it properly, for example,
Co-developed-by: Claude claude-opus-4-20250514 [1] or
[1] https://lwn.net/Articles/1031473/
[2] https://docs.kernel.org/process/coding-assistants.html
Quoted 37 lines
Signed-off-by MidG971 <[email protected]>---
Changes since v1 [1]:
- Drop phy-supply approach entirely (Jonas, Shawn)
- Model PI6C20100 as gated-fixed-clock instead
- Wire reference clock to pcie3x2 controller
- Follow pattern fromrk3588-rock-5-itx.dts[1] https://lore.kernel.org/linux-rockchip/[email protected]/
.../arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +10
-1@@ -56,7 +56,16 @@ }; }; - /* pi6c pcie clock generator */ + /* PI6C20100 PCIe reference clock buffer (100MHz) */ + pcie30_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_03>; + }; + + /* PI6C20100 power supply - active-high GPIO0_D4 */ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { compatible = "regulator-fixed"; enable-active-high;
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts line 571
Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +7
-0@@ -553,6 +562,13 @@ }; &pcie3x2 { + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&pcie30_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "ref";
There is a missing pipe clock which should be fixed. Please refer to David's patch[3].
Quoted 12 lines
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +0
-1pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; --2.39.5
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Re: [PATCH v2] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
Quoted 9 lines · Shawn Lin
IIUC, you are using Claude to help generate this patch, please describe it properly, for example,
Co-developed-by: Claude claude-opus-4-20250514 [1] or
Assisted-by Claude:claude-3-opus [2][1] https://lwn.net/Articles/1031473/
[2] https://docs.kernel.org/process/coding-assistants.html
Thank you for the guidance. I used Claude as a coding assistant and will use the proper tag in v3:
Quoted 4 lines
There is a missing pipe clock which should be fixed. Please refer to David's patch[3].
Since our board-level &pcie3x2 override replaces the clocks property entirely, v3 adds CLK_PCIE30X2_PIPE_DFT ("pipe") as well, consistent with David's base DTS patch.
I tested v3 on the ROCK 3B (kernel 6.19.0-rc5): pcie3x2 probes successfully and the NVMe device is detected at 15.75 Gb/s. The pcie30_refclk clock appears in the clock tree at 100MHz with pcie3x2 as its consumer.
One note on the pipe clock test: CLK_PCIE30X2_PIPE_DFT is defined in rk3568-cru.h but was not yet registered in the CRU driver in the tested kernel build, so the pipe clock was excluded from the functional test (pcie3x2 probe fails with -ENOENT at clock index 5 when it is included). The gated-fixed-clock node and ref clock were verified working. I expect the pipe clock will work once the CRU driver registers it alongside David's DTS patch.
v3 is sent separately.
Best regards,
MidG971
Re: [PATCH v2] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
Quoted 31 lines · 在 2026/03/19 星期四 18:19, MidG971 写道:
Quoted 9 lines · Shawn Lin
IIUC, you are using Claude to help generate this patch, please describe it properly, for example,
Co-developed-by: Claude claude-opus-4-20250514 [1] or
Assisted-by Claude:claude-3-opus [2][1] https://lwn.net/Articles/1031473/
[2] https://docs.kernel.org/process/coding-assistants.htmlThank you for the guidance. I used Claude as a coding assistant and will use the proper tag in v3:
Assisted-by: Claude:claude-3-opus Signed-off-by: MidG971 <[email protected]>Quoted 4 lines
There is a missing pipe clock which should be fixed. Please refer to David's patch[3].
Since our board-level &pcie3x2 override replaces the clocks property entirely, v3 adds
CLK_PCIE30X2_PIPE_DFT("pipe") as well, consistent with David's base DTS patch.I tested v3 on the ROCK 3B (kernel 6.19.0-rc5): pcie3x2 probes successfully and the NVMe device is detected at 15.75 Gb/s. The
pcie30_refclkclock appears in the clock tree at 100MHz with pcie3x2 as its consumer.
Quoted 7 lines
One note on the pipe clock test:
CLK_PCIE30X2_PIPE_DFTis defined inrk3568-cru.hbut was not yet registered in the CRU driver in the tested kernel build, so the pipe clock was excluded from the functional test (pcie3x2 probe fails with-ENOENTat clock index 5 when it is included). The gated-fixed-clock node and ref clock were verified working. I expect the pipe clock will work once the CRU driver registers it alongside David's DTS patch.
Pipe clock support was applied and appears in linux-next[1], you could pick it into your tested kernel build if you'd like to have a try.
Quoted 11 lines
v3 is sent separately.
Best regards,
MidG971_______________________________________________
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PATCH v4 1/1 arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
In reply to MidG971The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (vcc3v3_pi6c_03), with no clock output representation.
The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips.
The regulator node is kept as-is since it controls the power supply to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node references this regulator as its vdd-supply and provides a proper 100MHz clock output. The pcie3x2 node is updated to include the pipe and reference clocks, matching the approach used in rk3588-rock-5-itx.dts.
---
Changes since v3 [1]:
- Add Reviewed-by from Shawn Lin
Changes since v2 [2]:
- Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
- Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks override (Shawn, referencing David's patch [3])
Changes since v1 [4]:
- Drop phy-supply approach entirely (Jonas, Shawn)
- Model PI6C20100 as gated-fixed-clock instead
- Wire reference clock to pcie3x2 controller
- Follow pattern from rk3588-rock-5-itx.dts
[1] https://lore.kernel.org/linux-rockchip/[email protected]/
[2] https://lore.kernel.org/linux-rockchip/[email protected]/
[3] https://lore.kernel.org/linux-rockchip/[email protected]/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
[4] https://lore.kernel.org/linux-rockchip/[email protected]/
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +18 -1
@@ -56,7 +56,16 @@ }; }; - /* pi6c pcie clock generator */ + /* PI6C20100 PCIe reference clock buffer (100MHz) */ + pcie30_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_03>; + }; + + /* PI6C20100 power supply - active-high GPIO0_D4 */ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { compatible = "regulator-fixed"; enable-active-high;
@@ -553,6 +562,15 @@ }; &pcie3x2 { + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>, + <&pcie30_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
--
2.39.5
Heiko Stuebner
maintainerRe: [PATCH v4] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
Am Donnerstag, 19. März 2026, 15:51:20 Mitteleuropäische Normalzeit schrieb MidG971:
Quoted 17 lines
The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (
vcc3v3_pi6c_03), with no clock output representation.The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips.
The regulator node is kept as-is since it controls the power supply to the PI6C20100 chip via
GPIO0_D4. The new gated-fixed-clock node references this regulator as its vdd-supply and provides a proper 100MHz clock output. The pcie3x2 node is updated to include the pipe and reference clocks, matching the approach used inrk3588-rock-5-itx.dts.
Quoted 3 lines
Assisted-by Claude:claude-3-opusReviewed-by Shawn Lin <[email protected]>Signed-off-by Midgy BALON <[email protected]>
Sorry for having to bring up the process again, but the patch author should match the Signed-off-by line.
You can update the patch author with something like:
git commit --author="Midgy BALON <[email protected]>" --amend
Also is the last name always "UPPER CASE" in your region?
Thanks a lot for staying on this
Heiko
Quoted 65 lines
---
Changes since v3 [1]:
- Add Reviewed-by from Shawn LinChanges since v2 [2]:
- Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
- Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks override (Shawn, referencing David's patch [3])Changes since v1 [4]:
- Drop phy-supply approach entirely (Jonas, Shawn)
- Model PI6C20100 as gated-fixed-clock instead
- Wire reference clock to pcie3x2 controller
- Follow pattern fromrk3588-rock-5-itx.dts[1] https://lore.kernel.org/linux-rockchip/[email protected]/
[2] https://lore.kernel.org/linux-rockchip/[email protected]/
[3] https://lore.kernel.org/linux-rockchip/[email protected]/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
[4] https://lore.kernel.org/linux-rockchip/[email protected]/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-)arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +18
-2@@ -56,7 +56,16 @@ }; }; - /* pi6c pcie clock generator */ + /* PI6C20100 PCIe reference clock buffer (100MHz) */ + pcie30_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_03>; + }; + + /* PI6C20100 power supply - active-high GPIO0_D4 */ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { compatible = "regulator-fixed"; enable-active-high;@@ -553,6 +562,15 @@ }; &pcie3x2 { + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>, + <&pcie30_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; --2.39.5
PATCH v5 1/1 arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
From: Midgy BALON <[email protected]>
The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (vcc3v3_pi6c_03), with no clock output representation.
The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips.
The regulator node is kept as-is since it controls the power supply to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node references this regulator as its vdd-supply and provides a proper 100MHz clock output. The pcie3x2 node is updated to include the pipe and reference clocks, matching the approach used in rk3588-rock-5-itx.dts.
---
Changes since v4:
- Fix From: line to match Signed-off-by (Heiko)
Changes since v3 [1]:
- Add Reviewed-by from Shawn Lin
Changes since v2 [2]:
- Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
- Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks override (Shawn, referencing David's patch [3])
Changes since v1 [4]:
- Drop phy-supply approach entirely (Jonas, Shawn)
- Model PI6C20100 as gated-fixed-clock instead
- Wire reference clock to pcie3x2 controller
- Follow pattern from rk3588-rock-5-itx.dts
[1] https://lore.kernel.org/linux-rockchip/[email protected]/
[2] https://lore.kernel.org/linux-rockchip/[email protected]/
[3] https://lore.kernel.org/linux-rockchip/[email protected]/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
[4] https://lore.kernel.org/linux-rockchip/[email protected]/
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +18 -1
@@ -56,7 +56,16 @@ }; }; - /* pi6c pcie clock generator */ + /* PI6C20100 PCIe reference clock buffer (100MHz) */ + pcie30_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_03>; + }; + + /* PI6C20100 power supply - active-high GPIO0_D4 */ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { compatible = "regulator-fixed"; enable-active-high;
@@ -553,6 +562,15 @@ }; &pcie3x2 { + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>, + <&pcie30_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
--
2.39.5
Re: [PATCH v5] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
Quoted 11 lines · On Fri, 20 Mar 2026 10:44:41 +0100, MidG971 wrote:
The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (
vcc3v3_pi6c_03), with no clock output representation.The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips.
[...]
Applied, thanks!
[1/1] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
commit: b61f3c69c87b5f061194f413d810723698534b02
As I somehow expected, that AI messed up ;-) .
In the 2nd part of the patch the reported number of lines in the header (the 15 there) does not match the number of lines in the diff itself (14). I've fixed that up to not have another round.
Best regards,
Signature · 1 line
Heiko Stuebner <[email protected]>
Re: [PATCH v5] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
Hi Heiko,
Quoted 7 lines · Heiko Stuebner
Quoted 5 lines · On Fri, 20 Mar 2026 10:44:41 +0100, MidG971 wrote:
The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (
vcc3v3_pi6c_03), with no clock output representation.
Quoted 8 lines
Quoted 6 lines
The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips.
[...]
Applied, thanks!
My comments from v3 [1] was not addressed in v4 och v5. E.g. regulator-always-on/boot-on not being removed and redundant comments.
[1] https://lore.kernel.org/all/[email protected]/
Regards,
Jonas
Quoted 12 lines
[1/1] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
commit: b61f3c69c87b5f061194f413d810723698534b02As I somehow expected, that AI messed up ;-) .
In the 2nd part of the patch the reported number of lines in the header (the 15 there) does not match the number of lines in the diff itself (14). I've fixed that up to not have another round.
Best regards,
Heiko Stuebner
maintainerRe: [PATCH v5] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
Hi Jonas,
Am Dienstag, 24. März 2026, 18:15:38 Mitteleuropäische Normalzeit schrieb Jonas Karlman:
Quoted 15 lines
Hi Heiko,
Quoted 12 lines · Heiko Stuebner
Quoted 10 lines · On Fri, 20 Mar 2026 10:44:41 +0100, MidG971 wrote:
The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (
vcc3v3_pi6c_03), with no clock output representation.The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips.
Quoted 8 lines
Quoted 3 lines
Quoted 1 line
[...]
Applied, thanks!
My comments from v3 [1] was not addressed in v4 och v5. E.g. regulator-always-on/boot-on not being removed and redundant comments.
thank you so much for noticing. Looks like that AI thing is working "well" ;-) .
I've droped the patch and recreated the for-next branch now.
@Midgy, please honor feedback in future revisions.
Thanks
Heiko
Re: [PATCH v5] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
Hello Heiko,
I apologize for missing Jonas' comments. It will be done for the next version as requested.
Indeed Claude works "well" :D . I'll be more careful next time.
Thanks,
Midgy
Quoted 39 lines · Heiko Stuebner
Hi Jonas,
Am Dienstag, 24. März 2026, 18:15:38 Mitteleuropäische Normalzeit schrieb Jonas Karlman:
Quoted 15 lines
Hi Heiko,
Quoted 12 lines · Heiko Stuebner
Quoted 10 lines · On Fri, 20 Mar 2026 10:44:41 +0100, MidG971 wrote:
The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (
vcc3v3_pi6c_03), with no clock output representation.The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips.
Quoted 8 lines
Quoted 3 lines
Quoted 1 line
[...]
Applied, thanks!
My comments from v3 [1] was not addressed in v4 och v5. E.g. regulator-always-on/boot-on not being removed and redundant comments.
thank you so much for noticing. Looks like that AI thing is working "well" ;-) .
I've droped the patch and recreated the for-next branch now.
@Midgy, please honor feedback in future revisions.
Thanks
Heiko
Re: [PATCH v4] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
In reply to Heiko StuebnerHello Heiko
Quoted 1 line
Sorry for having to bring up the process again,
but the patch
Quoted 1 line
author should match the Signed-off-by line.
Apologies for the inconsistency. I'll fix that in v5.
Quoted 1 line
Also is the last name always "UPPER CASE" in your
region?
Yes it is standard practice in France to write family names in all
capitals to distinguish them from given names, especially when the family name could be confused with a given name, not my case but I comply.
v5 sent separately.
Best regards,
Midgy BALON
Quoted 104 lines · Heiko Stuebner
Am Donnerstag, 19. März 2026, 15:51:20 Mitteleuropäische Normalzeit schrieb MidG971:
Quoted 17 lines
The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers. This chip is currently modeled only as a fixed regulator (
vcc3v3_pi6c_03), with no clock output representation.The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips.
The regulator node is kept as-is since it controls the power supply to the PI6C20100 chip via
GPIO0_D4. The new gated-fixed-clock node references this regulator as its vdd-supply and provides a proper 100MHz clock output. The pcie3x2 node is updated to include the pipe and reference clocks, matching the approach used inrk3588-rock-5-itx.dts.Quoted 3 lines
Assisted-by Claude:claude-3-opusReviewed-by Shawn Lin <[email protected]>Signed-off-by Midgy BALON <[email protected]>Sorry for having to bring up the process again, but the patch author should match the Signed-off-by line.
You can update the patch author with something like:
git commit --author="Midgy BALON <[email protected]>" --amendAlso is the last name always "UPPER CASE" in your region?
Thanks a lot for staying on this
HeikoQuoted 65 lines
---
Changes since v3 [1]:
- Add Reviewed-by from Shawn LinChanges since v2 [2]:
- Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
- Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks override (Shawn, referencing David's patch [3])Changes since v1 [4]:
- Drop phy-supply approach entirely (Jonas, Shawn)
- Model PI6C20100 as gated-fixed-clock instead
- Wire reference clock to pcie3x2 controller
- Follow pattern fromrk3588-rock-5-itx.dts[1] https://lore.kernel.org/linux-rockchip/[email protected]/
[2] https://lore.kernel.org/linux-rockchip/[email protected]/
[3] https://lore.kernel.org/linux-rockchip/[email protected]/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
[4] https://lore.kernel.org/linux-rockchip/[email protected]/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-)arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +18
-2@@ -56,7 +56,16 @@ }; }; - /* pi6c pcie clock generator */ + /* PI6C20100 PCIe reference clock buffer (100MHz) */ + pcie30_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_03>; + }; + + /* PI6C20100 power supply - active-high GPIO0_D4 */ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { compatible = "regulator-fixed"; enable-active-high;@@ -553,6 +562,15 @@ }; &pcie3x2 { + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>, + <&pcie30_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; --2.39.5