ppc32: Fix Apple Xserve G4 PCI probing
PATCH 1/1 ppc32: Fix Apple Xserve G4 PCI probing
Hi !
When pci_assign_all_busses is set, the common code will re-assign all the bus numbers, which we still need to do one various pmacs, at least until XFree/XOrg understands PCI domains properly. However, this process triggers a bug if during this renumbering, on a given segment, a P2P bridge not yet renumbered has conflicting downstream bus range with a P2P bridge just renumbered. The probing will just behave randomly and either miss devices, show duplicates, or just lockup in some circumstances. This is typically triggered on Apple Xserve G4s who have at least 2 P2P bridges built-in on the same segment of the first PCI (non-AGP) domain
The "workaround" we use on pmac that was in my tree for a while but got "lost" during the big merge a while ago is to offset the bus numbers between domains by 16. This avoids the above collision scenario in all practical cases.
The long term solution of course is to stop renumbering and make sure that all drivers are domain safe (there may be a couple issue remaining in the code that matches PCI / OF devices on ppc32) and XFree/XOrg has to be fixed.
arch/ppc/kernel/pci.c +2 -1
@@ -33,6 +33,7 @@unsigned long isa_io_base =0 ;unsigned long isa_mem_base =0 ;unsigned long pci_dram_offset =0 ; +int pcibios_assign_bus_offset =1 ;void pcibios_make_OF_bus_map (void );
@@ -1263,7 +1264,7 @@ bus =pci_scan_bus (hose->first_busno, hose->ops, hose); hose->last_busno = bus->subordinate;if (pci_assign_all_busses || next_busno <= hose->last_busno) - next_busno = hose->last_busno+1 ; + next_busno = hose->last_busno + pcibios_assign_bus_offset; } pci_bus_count = next_busno;
arch/ppc/platforms/pmac_pci.c +9 -0
@@ -50,6 +50,7 @@#endif /* CONFIG_POWER4 */ extern u8 pci_cache_line_size; +extern int pcibios_assign_bus_offset;struct pci_dev *k2_skiplist[2 ];
@@ -565,6 +566,14 @@init_p2pbridge ();fixup_nec_usb2 (); + +/* We are still having some issues with the Xserve G4, enabling +* some offset between bus number and domains for now when we +* assign all busses should help for now +*/ +if (pci_assign_all_busses) + pcibios_assign_bus_offset =0x10 ; +#ifdef CONFIG_POWER4 /* There is something wrong with DMA on U3/HT. I haven't figured out * the details yet, but if I set the cache line size to 128 bytes like