ppc/ppc64: Fix g5 access to PCI IO cycles

PATCH New Benjamin Herrenschmidt 1 participant 1 message Sep 29, 2004 PowerPC

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Benjamin Herrenschmidt

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2004-09-29 04:10 UTC #0 lore raw

PATCH 1/1 ppc/ppc64: Fix g5 access to PCI IO cycles

Hi !

Looks like we never needed them, since that bug has been there forever, I didn't get the right base for the IO cycles on the G5 host bridge in the first place (I probably misinterpreted some OF forth code or something like that).

Here's the fix:

===== arch/ppc/platforms/pmac_pci.c 1.23 vs edited =====

arch/ppc/platforms/pmac_pci.c +1 -1

@@ -716,7 +716,7 @@
 	 * properties or figuring out the U3 address space decoding logic and
 	 * then read its configuration register (if any).
 	 */
-	hose->io_base_phys = 0xf4000000 + 0x00400000;
+	hose->io_base_phys = 0xf4000000;
 	hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
 	isa_io_base = (unsigned long) hose->io_base_virt;
 	hose->io_resource.name = np->full_name;

===== arch/ppc64/kernel/pmac_pci.c 1.9 vs edited =====

arch/ppc64/kernel/pmac_pci.c +1 -1

@@ -419,7 +419,7 @@
 	 * properties or figuring out the U3 address space decoding logic and
 	 * then read it's configuration register (if any).
 	 */
-	hose->io_base_phys = 0xf4000000 + 0x00400000;
+	hose->io_base_phys = 0xf4000000;
 	hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
 	isa_io_base = pci_io_base = (unsigned long) hose->io_base_virt;
 	hose->io_resource.name = np->full_name;