Update ppc32-fix-errata-for-some-g3-cpus.patch
PATCH 1/1 Update ppc32-fix-errata-for-some-g3-cpus.patch
Hi Andrew !
The previous version of ppc32-fix-errata-for-some-g3-cpus.patch had an issue that would crash some G4 CPUs on boot. This is fixed in this new version, please replace the old one and send to linus asap (it's now been tested on enough CPUs).
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Some G3 CPUs can crash in funny way if a store from an FPU register instruction is executed on a register that has never been initialized since power on. This patch fixes it by making sure all FP registers have been properly initialized at kernel boot and when waking from sleep. It also makes the code that decides wether HID0_BTIC and HID0_DPM are allowed on a given CPU smarter (it can actually _clear_ them now if they are not allowed instead of just setting them when they are allowed in case the firmware got them wrong)
arch/ppc/kernel/cpu_setup_6xx.S +37 -7
@@ -30,12 +30,14 @@ blr _GLOBAL(__setup_cpu_750) mflr r4 + bl __init_fpu_registers bl setup_common_caches bl setup_750_7400_hid0 mtlr r4 blr _GLOBAL(__setup_cpu_750cx) mflr r4 + bl __init_fpu_registers bl setup_common_caches bl setup_750_7400_hid0 bl setup_750cx
@@ -43,6 +45,7 @@ blr _GLOBAL(__setup_cpu_750fx) mflr r4 + bl __init_fpu_registers bl setup_common_caches bl setup_750_7400_hid0 bl setup_750fx
@@ -50,6 +53,7 @@ blr _GLOBAL(__setup_cpu_7400) mflr r4 + bl __init_fpu_registers bl setup_7400_workarounds bl setup_common_caches bl setup_750_7400_hid0
@@ -57,6 +61,7 @@ blr _GLOBAL(__setup_cpu_7410) mflr r4 + bl __init_fpu_registers bl setup_7410_workarounds bl setup_common_caches bl setup_750_7400_hid0
@@ -80,7 +85,7 @@ bne 1f /* don't invalidate the D-cache */ ori r8,r8,HID0_DCI /* unless it wasn't enabled */ 1: sync - mtspr SPRN_HID0,r8 /* enable and invalidate caches */ + mtspr SPRN_HID0,r8 /* enable and invalidate caches */ sync mtspr SPRN_HID0,r11 /* enable caches */ sync
@@ -151,10 +156,14 @@ */ setup_750_7400_hid0: mfspr r11,SPRN_HID0 - ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC + ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC + oris r11,r11,HID0_DPM@h BEGIN_FTR_SECTION - oris r11,r11,HID0_DPM@h /* enable dynamic power mgmt */ -END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM) + xori r11,r11,HID0_BTIC +END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC) +BEGIN_FTR_SECTION + xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */ +END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) li r3,HID0_SPD andc r11,r11,r3 /* clear SPD: enable speculative */ li r3,0
@@ -218,13 +227,15 @@ /* All of the bits we have to set..... */ - ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE | HID0_LRSTK | HID0_BTIC + ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE + ori r11,r11,HID0_LRSTK | HID0_BTIC + oris r11,r11,HID0_DPM@h BEGIN_FTR_SECTION xori r11,r11,HID0_BTIC END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC) BEGIN_FTR_SECTION - oris r11,r11,HID0_DPM@h /* enable dynamic power mgmt */ -END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM) + xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */ +END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) /* All of the bits we have to clear.... */
@@ -248,6 +259,25 @@ isync blr +/* + * Initialize the FPU registers. This is needed to work around an errata + * in some 750 cpus where using a not yet initialized FPU register after + * power on reset may hang the CPU + */ +_GLOBAL(__init_fpu_registers) + mfmsr r10 + ori r11,r10,MSR_FP + mtmsr r11 + isync + addis r9,r3,empty_zero_page@ha + addi r9,r9,empty_zero_page@l + REST_32FPRS(0,r9) + sync + mtmsr r10 + isync + blr + + /* Definitions for the table use to save CPU states */ #define CS_HID0 0 #define CS_HID1 4
arch/ppc/platforms/pmac_sleep.S +4 -0
@@ -267,6 +267,10 @@ /* Restore various CPU config stuffs */ bl __restore_cpu_setup + /* Make sure all FPRs have been initialized */ + bl reloc_offset + bl __init_fpu_registers + /* Invalidate & enable L1 cache, we don't care about * whatever the ROM may have tried to write to memory */
Quoted 4 lines · Benjamin Herrenschmidt
The previous version of ppc32-fix-errata-for-some-g3-cpus.patch had an issue that would crash some G4 CPUs on boot. This is fixed in this new version, please replace the old one and send to linus asap (it's now been tested on enough CPUs).
Apparently not. I'm getting "floating point used in kernel" crashes during wakeup on my iBook G3 (750FX).
Andreas.
Signature · 4 lines
Andreas Schwab, SuSE Labs, [email protected] SuSE Linux Products GmbH, Maxfeldstraße 5, 90409 Nürnberg, Germany Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5 "And now for something completely different."
Quoted 9 lines · Andreas Schwab
Quoted 4 lines · Benjamin Herrenschmidt
The previous version of ppc32-fix-errata-for-some-g3-cpus.patch had an issue that would crash some G4 CPUs on boot. This is fixed in this new version, please replace the old one and send to linus asap (it's now been tested on enough CPUs).
Apparently not. I'm getting "floating point used in kernel" crashes during wakeup on my iBook G3 (750FX).
And does removing that patch fixes it ? That is very strange. The patch works fine here on a G3 Pismo and a couple of G4s, the code in the patch does enable the FPU before initilizing the registers, so the kernel shouldn't take any FP exception... Couldn't the above be a different problem ? What is the exact PC where the exception occurs ? what instruction does it correspond to ?
Ben.
Quoted 8 lines · Benjamin Herrenschmidt
Quoted 7 lines · Andreas Schwab
Quoted 4 lines · Benjamin Herrenschmidt
The previous version of ppc32-fix-errata-for-some-g3-cpus.patch had an issue that would crash some G4 CPUs on boot. This is fixed in this new version, please replace the old one and send to linus asap (it's now been tested on enough CPUs).
Quoted 4 lines
Quoted 2 lines
Apparently not. I'm getting "floating point used in kernel" crashes during wakeup on my iBook G3 (750FX).
And does removing that patch fixes it ?
Sorry, I have to take that back. It doesn't actually cause my wakeup problems (alone?). I will try to dig further into that tomorrow.
Andreas.
Signature · 4 lines
Andreas Schwab, SuSE Labs, [email protected] SuSE Linux Products GmbH, Maxfeldstraße 5, 90409 Nürnberg, Germany Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5 "And now for something completely different."