ssm/rsm sequences
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Quoted 5 lines · Grant Grundler
The example code is just that, an example:
SSM 0,gr0 ; initial RSM, SSM, or MTSM
...AFAICT, that sequence does nothing but burn some cycles.
*sigh*. The ssm 0,0/nop * 8/rsm sequence isn't so obvious. Richard Hirst added this comment to entry.S in 2001:
* The ssm is necessary due to a PCXT bug
http://lists.parisc-linux.org/hypermail/parisc-linux-cvs/3628.html
Richard, any clue what the bug is?
I don't have a PCX-T ERS or errata sheet to look this up.
thanks,
grant
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Quoted 9 lines · Grant Grundler
Quoted 5 lines
The example code is just that, an example:
SSM 0,gr0 ; initial RSM, SSM, or MTSM
...AFAICT, that sequence does nothing but burn some cycles.
*sigh*. The ssm 0,0/nop * 8/rsm sequence isn't so obvious. Richard Hirst added this comment to
entry.Sin 2001:
* The ssm is necessary due to a PCXT bug
Regardless of what this is for, the following patch adds pcxt_ssm_bug macro to assembly.h. pcxt_ssm_bug is only enabled for CONFIG_PA7000 which is only enabled for generic 32-bit kernel.
I've added pcxt_ssm_bug use to all the locations I could find where PSW_SM_Q was being twiddled. Until someone can tell me what the bug is exactly, my assumption is it is needed for all cases where we "rsm PSW_SM_Q" and not just at init time.
I've also tried to unify all the RFI asm into a similar layout that could be (hopefully) replaced with a macro in a future step. And I've made them all use "PSW_SM_Q+PSW_SM_I" just to be consistent.
I apologize in advance since this patch also replaces __LP64__ with CONFIG_64BIT. I thought it would only be a few but it turned out to interfer with the patch.
I can split out CONFIG_64BIT changes if someone really needs that before reviewing it. It's just too late tonight for me to do it.
Can the asm gurus please closely review this patch?
I don't plan on committing this before it's been tested too. I've only compiled kernels with it so far.
thanks,
grant
Index: arch/parisc/kernel/entry.S
===================================================================
RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/entry.S,v retrieving revision 1.27
parisc/kernel/entry.S +56 -65
@@ -37,7 +37,7 @@ #include <asm/unistd.h> #include <asm/thread_info.h> -#ifdef __LP64__ +#ifdef CONFIG_64BIT #define CMPIB cmpib,* #define CMPB cmpb,* #define COND(x) *x
@@ -214,7 +214,7 @@ va = r8 /* virtual address for which the trap occured */ spc = r24 /* space for which the trap occured */ -#ifndef __LP64__ +#ifndef CONFIG_64BIT /* * itlb miss interruption handler (parisc 1.1 - 32 bit)
@@ -236,7 +236,7 @@ .macro itlb_20 code mfctl %pcsq, spc -#ifdef __LP64__ +#ifdef CONFIG_64BIT b itlb_miss_20w #else b itlb_miss_20
@@ -246,7 +246,7 @@ .align 32 .endm -#ifndef __LP64__ +#ifndef CONFIG_64BIT /* * naitlb miss interruption handler (parisc 1.1 - 32 bit) *
@@ -283,7 +283,7 @@ .macro naitlb_20 code mfctl %isr,spc -#ifdef __LP64__ +#ifdef CONFIG_64BIT b itlb_miss_20w #else b itlb_miss_20
@@ -296,7 +296,7 @@ .align 32 .endm -#ifndef __LP64__ +#ifndef CONFIG_64BIT /* * dtlb miss interruption handler (parisc 1.1 - 32 bit) */
@@ -318,7 +318,7 @@ .macro dtlb_20 code mfctl %isr, spc -#ifdef __LP64__ +#ifdef CONFIG_64BIT b dtlb_miss_20w #else b dtlb_miss_20
@@ -328,7 +328,7 @@ .align 32 .endm -#ifndef __LP64__ +#ifndef CONFIG_64BIT /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */ .macro nadtlb_11 code
@@ -346,7 +346,7 @@ .macro nadtlb_20 code mfctl %isr,spc -#ifdef __LP64__ +#ifdef CONFIG_64BIT b nadtlb_miss_20w #else b nadtlb_miss_20
@@ -356,7 +356,7 @@ .align 32 .endm -#ifndef __LP64__ +#ifndef CONFIG_64BIT /* * dirty bit trap interruption handler (parisc 1.1 - 32 bit) */
@@ -378,7 +378,7 @@ .macro dbit_20 code mfctl %isr,spc -#ifdef __LP64__ +#ifdef CONFIG_64BIT b dbit_trap_20w #else b dbit_trap_20
@@ -391,7 +391,7 @@ /* The following are simple 32 vs 64 bit instruction * abstractions for the macros */ .macro EXTR reg1,start,length,reg2 -#ifdef __LP64__ +#ifdef CONFIG_64BIT extrd,u \reg1,32+\start,\length,\reg2 #else extrw,u \reg1,\start,\length,\reg2
@@ -399,7 +399,7 @@ .endm .macro DEP reg1,start,length,reg2 -#ifdef __LP64__ +#ifdef CONFIG_64BIT depd \reg1,32+\start,\length,\reg2 #else depw \reg1,\start,\length,\reg2
@@ -407,7 +407,7 @@ .endm .macro DEPI val,start,length,reg -#ifdef __LP64__ +#ifdef CONFIG_64BIT depdi \val,32+\start,\length,\reg #else depwi \val,\start,\length,\reg
@@ -418,7 +418,7 @@ * fault. We have to extract this and place it in the va, * zeroing the corresponding bits in the space register */ .macro space_adjust spc,va,tmp -#ifdef __LP64__ +#ifdef CONFIG_64BIT extrd,u \spc,63,SPACEID_SHIFT,\tmp depd %r0,63,SPACEID_SHIFT,\spc depd \tmp,31,SPACEID_SHIFT,\va
@@ -476,7 +476,7 @@ bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */ copy \pmd,%r9 -#ifdef __LP64__ +#ifdef CONFIG_64BIT shld %r9,PxD_VALUE_SHIFT,\pmd #else shlw %r9,PxD_VALUE_SHIFT,\pmd
@@ -607,7 +607,7 @@ .macro do_alias spc,tmp,tmp1,va,pte,prot,fault cmpib,COND(<>),n 0,\spc,\fault ldil L%(TMPALIAS_MAP_START),\tmp -#if defined(__LP64__) && (TMPALIAS_MAP_START >= 0x80000000) +#if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000) /* on LP64, ldi will sign extend into the upper 32 bits, * which is behaviour we don't want */ depdi 0,31,32,\tmp
@@ -621,7 +621,7 @@ * OK, it is in the temp alias region, check whether "from" or "to". * Check "subtle" note in pacache.S re: r23/r26. */ -#ifdef __LP64__ +#ifdef CONFIG_64BIT extrd,u,*= \va,41,1,%r0 #else extrw,u,= \va,9,1,%r0
@@ -688,7 +688,7 @@ fault_vector_20: def 30 def 31 -#ifndef __LP64__ +#ifndef CONFIG_64BIT .export fault_vector_11
@@ -761,7 +761,7 @@ __kernel_thread: copy %r30, %r1 ldo PT_SZ_ALGN(%r30),%r30 -#ifdef __LP64__ +#ifdef CONFIG_64BIT /* Yo, function pointers in wide mode are little structs... -PB */ ldd 24(%r26), %r2 STREG %r2, PT_GR27(%r1) /* Store childs %dp */
@@ -777,7 +777,7 @@ __kernel_thread: or %r26, %r24, %r26 /* will have kernel mappings. */ ldi 1, %r25 /* stack_start, signals kernel thread */ stw %r0, -52(%r30) /* user_tid */ -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif BL do_fork, %r2
@@ -806,7 +806,7 @@ ret_from_kernel_thread: LDREG TI_TASK-THREAD_SZ_ALGN(%r30), %r1 LDREG TASK_PT_GR25(%r1), %r26 -#ifdef __LP64__ +#ifdef CONFIG_64BIT LDREG TASK_PT_GR27(%r1), %r27 LDREG TASK_PT_GR22(%r1), %r22 #endif
@@ -814,7 +814,7 @@ ret_from_kernel_thread: ble 0(%sr7, %r1) copy %r31, %r2 -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ loadgp /* Thread could have been in a module */ #endif
@@ -835,7 +835,7 @@ __execve: STREG %r26, PT_GR26(%r16) STREG %r25, PT_GR25(%r16) STREG %r24, PT_GR24(%r16) -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif BL sys_execve, %r2
@@ -893,9 +893,6 @@ _switch_to_ret: * this way, then we will need to copy %sr3 in to PT_SR[3..7], and * adjust IASQ[0..1]. * - * Note that the following code uses a "relied upon translation". - * See the parisc ACD for details. The ssm is necessary due to a - * PCXT bug. */ .align 4096
@@ -916,7 +913,7 @@ syscall_exit_rfi: STREG %r19,PT_IAOQ1(%r16) LDREG PT_PSW(%r16),%r19 load32 USER_PSW_MASK,%r1 -#ifdef __LP64__ +#ifdef CONFIG_64BIT load32 USER_PSW_HI_MASK,%r20 depd %r20,31,32,%r1 #endif
@@ -960,7 +957,7 @@ intr_return: /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount ** irq_stat[] is defined using ____cacheline_aligned. */ -#ifdef __LP64__ +#ifdef CONFIG_64BIT shld %r1, 6, %r20 #else shlw %r1, 5, %r20
@@ -990,24 +987,18 @@ intr_restore: rest_fp %r1 rest_general %r29 - /* Create a "relied upon translation" PA 2.0 Arch. F-5 */ - ssm 0,%r0 - nop - nop - nop - nop - nop - nop - nop + pcxt_ssm_bug tophys_r1 %r29 - rsm (PSW_SM_Q|PSW_SM_P|PSW_SM_D|PSW_SM_I),%r0 + rsm PSW_SM_QUIET,%r0 /* prepare for rfi */ /* Restore space id's and special cr's from PT_REGS - * structure pointed to by r29 */ + * structure pointed to by r29 + */ rest_specials %r29 - /* Important: Note that rest_stack restores r29 - * last (we are using it)! It also restores r1 and r30. */ + /* IMPORTANT: rest_stack restores r29 last (we are using it)! + * It also restores r1 and r30. + */ rest_stack rfi
@@ -1023,7 +1014,7 @@ intr_restore: .import do_softirq,code intr_do_softirq: BL do_softirq,%r2 -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #else nop
@@ -1041,7 +1032,7 @@ intr_do_resched: CMPIB= 0,%r20,intr_restore /* backward */ nop -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif
@@ -1074,7 +1065,7 @@ intr_do_signal: copy %r0, %r24 /* unsigned long in_syscall */ copy %r16, %r25 /* struct pt_regs *regs */ -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif
@@ -1098,7 +1089,7 @@ intr_extint: mfctl %cr31,%r1 copy %r30,%r17 /* FIXME! depi below has hardcoded idea of interrupt stack size (32k)*/ -#ifdef __LP64__ +#ifdef CONFIG_64BIT depdi 0,63,15,%r17 #else depi 0,31,15,%r17
@@ -1125,7 +1116,7 @@ intr_extint: ldil L%intr_return, %r2 -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif
@@ -1168,7 +1159,7 @@ intr_save: mfctl %cr20, %r16 /* isr */ mfctl %cr21, %r17 /* ior */ -#ifdef __LP64__ +#ifdef CONFIG_64BIT /* * If the interrupted code was running with W bit off (32 bit), * clear the b bits (bits 0 & 1) in the ior.
@@ -1202,7 +1193,7 @@ skip_save_ior: loadgp copy %r29, %r25 /* arg1 is pt_regs */ -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif
@@ -1240,7 +1231,7 @@ skip_save_ior: spc = r24 /* space for which the trap occured */ ptp = r25 /* page directory/page table pointer */ -#ifdef __LP64__ +#ifdef CONFIG_64BIT dtlb_miss_20w: space_adjust spc,va,t0
@@ -1531,7 +1522,7 @@ nadtlb_probe_check: nop -#ifdef __LP64__ +#ifdef CONFIG_64BIT itlb_miss_20w: /*
@@ -1598,7 +1589,7 @@ itlb_miss_20: #endif -#ifdef __LP64__ +#ifdef CONFIG_64BIT dbit_trap_20w: space_adjust spc,va,t0
@@ -1807,7 +1798,7 @@ sys_fork_wrapper: STREG %r2,-RP_OFFSET(%r30) ldo FRAME_SIZE(%r30),%r30 -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif
@@ -1857,7 +1848,7 @@ sys_clone_wrapper: STREG %r2,-RP_OFFSET(%r30) ldo FRAME_SIZE(%r30),%r30 -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif
@@ -1879,7 +1870,7 @@ sys_vfork_wrapper: STREG %r2,-RP_OFFSET(%r30) ldo FRAME_SIZE(%r30),%r30 -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif
@@ -1907,7 +1898,7 @@ sys_vfork_wrapper: STREG %r2,-RP_OFFSET(%r30) ldo FRAME_SIZE(%r30),%r30 -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif BL \execve,%r2
@@ -1933,7 +1924,7 @@ error_\execve: sys_execve_wrapper: execve_wrapper sys_execve -#ifdef __LP64__ +#ifdef CONFIG_64BIT .export sys32_execve_wrapper .import sys32_execve
@@ -1947,7 +1938,7 @@ sys_rt_sigreturn_wrapper: ldo TASK_REGS(%r26),%r26 /* get pt regs */ /* Don't save regs, we are going to restore them from sigcontext. */ STREG %r2, -RP_OFFSET(%r30) -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo FRAME_SIZE(%r30), %r30 BL sys_rt_sigreturn,%r2 ldo -16(%r30),%r29 /* Reference param save area */
@@ -1978,7 +1969,7 @@ sys_sigaltstack_wrapper: ldo TASK_REGS(%r1),%r24 /* get pt regs */ LDREG TASK_PT_GR30(%r24),%r24 STREG %r2, -RP_OFFSET(%r30) -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo FRAME_SIZE(%r30), %r30 b,l do_sigaltstack,%r2 ldo -16(%r30),%r29 /* Reference param save area */
@@ -1992,7 +1983,7 @@ sys_sigaltstack_wrapper: bv %r0(%r2) nop -#ifdef __LP64__ +#ifdef CONFIG_64BIT .export sys32_sigaltstack_wrapper sys32_sigaltstack_wrapper: /* Get the user stack pointer */
@@ -2016,7 +2007,7 @@ sys_rt_sigsuspend_wrapper: reg_save %r24 STREG %r2, -RP_OFFSET(%r30) -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo FRAME_SIZE(%r30), %r30 b,l sys_rt_sigsuspend,%r2 ldo -16(%r30),%r29 /* Reference param save area */
@@ -2089,7 +2080,7 @@ syscall_check_bh: ldw TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */ /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */ -#ifdef __LP64__ +#ifdef CONFIG_64BIT shld %r26, 6, %r20 #else shlw %r26, 5, %r20
@@ -2154,7 +2145,7 @@ syscall_restore: depi 3,31,2,%r31 /* ensure return to user mode. */ -#ifdef __LP64__ +#ifdef CONFIG_64BIT /* decide whether to reset the wide mode bit * * For a syscall, the W bit is stored in the lowest bit
@@ -2250,7 +2241,7 @@ syscall_do_softirq: .import schedule,code syscall_do_resched: BL schedule,%r2 -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #else nop
@@ -2270,7 +2261,7 @@ syscall_do_signal: ldi 1, %r24 /* unsigned long in_syscall */ -#ifdef __LP64__ +#ifdef CONFIG_64BIT ldo -16(%r30),%r29 /* Reference param save area */ #endif BL do_signal,%r2
Index: arch/parisc/kernel/head.S
===================================================================
RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/head.S,v retrieving revision 1.11
parisc/kernel/head.S +12 -30
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Index: arch/parisc/kernel/pacache.S
===================================================================
RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/pacache.S,v retrieving revision 1.17
parisc/kernel/pacache.S +27 -46
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Index: arch/parisc/kernel/real2.S
===================================================================
RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/real2.S,v retrieving revision 1.17
parisc/kernel/real2.S +5 -21
@@ -147,17 +147,9 @@ restore_control_regs: .text rfi_virt2real: /* switch to real mode... */ - ssm 0,0 /* See "relied upon translation" */ - nop /* PA 2.0 Arch. F-5 */ - nop - nop - nop - nop - nop - nop - nop + pcxt_ssm_bug - rsm (PSW_SM_Q|PSW_SM_I),%r0 /* disable Q & I bits to load iia queue */ + rsm PSW_SM_Q+PSW_SM_I,%r0 /* prep to load iia queue */ mtctl %r0, %cr17 /* Clear IIASQ tail */ mtctl %r0, %cr17 /* Clear IIASQ head */ load32 PA(rfi_v2r_1), %r1
@@ -184,17 +176,9 @@ rfi_v2r_1: .text .align 128 rfi_real2virt: - ssm 0,0 /* See "relied upon translation" */ - nop /* PA 2.0 Arch. F-5 */ - nop - nop - nop - nop - nop - nop - nop - - rsm PSW_SM_Q,%r0 /* disable Q bit to load iia queue */ + pcxt_ssm_bug + + rsm PSW_SM_Q+PSW_SM_I,%r0 /* prep to load iia queue */ mtctl %r0, %cr17 /* Clear IIASQ tail */ mtctl %r0, %cr17 /* Clear IIASQ head */ load32 (rfi_r2v_1), %r1
Index: include/asm-parisc/assembly.h
===================================================================
RCS file: /var/cvs/linux-2.6/include/asm-parisc/assembly.h,v retrieving revision 1.10
asm-parisc/assembly.h +18 -0
@@ -450,5 +450,23 @@ REST_CR (%cr22, PT_PSW (\regs)) .endm +#if defined(CONFIG_PA7000 ) + .macro pcxt_ssm_bug + /* Create a "relied upon translation" PA 2.0 Arch. page F-4 and F-5 + * The ssm is necessary due to a PCXT bug. Ie not needed for 64-bit. + */ + ssm 0,%r0 +nop /* 1 */ + nop /* 2 */ +nop /* 3 */ + nop /* 4 */ +nop /* 5 */ + nop /* 6 */ + nop/* 7 */ + .endm +#else +#define pcxt_ssm_bug/* Thank $DIETY. You don't have brain damaged HW. */ +#endif +#endif /* __ASSEMBLY__ */ #endif
Index: include/asm-parisc/psw.h
===================================================================
RCS file: /var/cvs/linux-2.6/include/asm-parisc/psw.h,v retrieving revision 1.1
asm-parisc/psw.h +23 -25
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Grant,
Quoted 15 lines
+++
include/asm-parisc/assembly.h27 Apr 2005 06:27:59 -0000asm-parisc/assembly.h +10
-0@@ -450,5 +450,23 @@ REST_CR (%cr22, PT_PSW (\regs)) .endm +#if defined(CONFIG_PA7000 ) + .macro pcxt_ssm_bug + /* Create a "relied upon translation" PA 2.0 Arch. page F-4 and F-5 + * The ssm is necessary due to a PCXT bug. Ie not needed for 64-bit. + */ + ssm 0,%r0 +nop /* 1 */ + nop /* 2 */ +nop /* 3 */ + nop/* 4 */
asm-parisc/assembly.h line 472
Quoted 10 lines
asm-parisc/assembly.h +8
-0+nop /* 5 */ + nop /* 6 */ + nop/* 7 */ + .endm +#else +#define pcxt_ssm_bug/* Thank $DIETY. You don't have brain damaged HW. */ +#endif +#endif /* __ASSEMBLY__ */ #endif
Make that $DEITY - or is this the weight-watchers version ;-)
-Andy
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Quoted 1 line · Andy Walker
Make that $DEITY - or is this the weight-watchers version ;-)
hehe. fixed.
thanks,
grant
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Hello Grant,
Quoted 6 lines
Regardless of what this is for, the following patch adds
pcxt_ssm_bugmacro toassembly.h.pcxt_ssm_bugis only enabled forCONFIG_PA7000which is only enabled for generic 32-bit kernel.
(what's up for other PA7xxx?)
Quoted 10 lines
I've added
pcxt_ssm_buguse to all the locations I could find wherePSW_SM_Qwas being twiddled. Until someone can tell me what the bug is exactly, my assumption is it is needed for all cases where we "rsmPSW_SM_Q" and not just at init time.I've also tried to unify all the RFI asm into a similar layout that could be (hopefully) replaced with a macro in a future step. And I've made them all use "PSW_SM_Q+PSW_SM_I" just to be consistent.
Cool you just did in one shoot what I was testing step by step ;-)
Quoted 4 lines
I apologize in advance since this patch also replaces
__LP64__withCONFIG_64BIT. I thought it would only be a few but it turned out to interfer with the patch.
Exact, that's confusing me a bit so I prepare (here below) sample geting rid of this change ;-)
Quoted 7 lines
I can split out
CONFIG_64BITchanges if someone really needs that before reviewing it. It's just too late tonight for me to do it.Can the asm gurus please closely review this patch?
I don't plan on committing this before it's been tested too.
Thanks for a break to let me test some config (b180, b2k, c110, d380)
So the essence of this patch is:
parisc/kernel/entry.S renamed from parisc/kernel/entry.S.orig +7 -16
@@ -893,9 +893,6 @@ * this way, then we will need to copy %sr3 in to PT_SR[3..7], and * adjust IASQ[0..1]. * - * Note that the following code uses a "relied upon translation". - * See the parisc ACD for details. The ssm is necessary due to a - * PCXT bug. */ .align 4096
@@ -990,24 +987,18 @@ rest_fp %r1 rest_general %r29 - /* Create a "relied upon translation" PA 2.0 Arch. F-5 */ - ssm 0,%r0 - nop - nop - nop - nop - nop - nop - nop + pcxt_ssm_bug tophys_r1 %r29 - rsm (PSW_SM_Q|PSW_SM_P|PSW_SM_D|PSW_SM_I),%r0 + rsm PSW_SM_QUIET,%r0 /* prepare for rfi */ /* Restore space id's and special cr's from PT_REGS - * structure pointed to by r29 */ + * structure pointed to by r29 + */ rest_specials %r29 - /* Important: Note that rest_stack restores r29 - * last (we are using it)! It also restores r1 and r30. */ + /* IMPORTANT: rest_stack restores r29 last (we are using it)! + * It also restores r1 and r30. + */ rest_stack rfi
parisc/kernel/head.S renamed from parisc/kernel/head.S.orig +4 -22
@@ -254,32 +254,14 @@ $install_iva: mtctl %r10,%cr14 -#ifdef __LP64__ b aligned_rfi nop - .align 256 + .align 128 aligned_rfi: - ssm 0,0 - nop /* 1 */ - nop /* 2 */ - nop /* 3 */ - nop /* 4 */ - nop /* 5 */ - nop /* 6 */ - nop /* 7 */ - nop /* 8 */ -#endif - -#ifdef __LP64__ /* move to psw.h? */ -#define PSW_BITS PSW_Q+PSW_I+PSW_D+PSW_P+PSW_R -#else -#define PSW_BITS PSW_SM_Q -#endif - -$rfi: - /* turn off troublesome PSW bits */ - rsm PSW_BITS,%r0 + pcxt_ssm_bug + rsm PSW_SM_QUIET,%r0 /* off troublesome PSW bits */ + /* Don't need NOPs, have 8 compliant insn below */ /* kernel PSW: * - no interruptions except HPMC and TOC (which are handled by PDC)
parisc/kernel/pacache.S renamed from parisc/kernel/pacache.S.orig +27 -46
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parisc/kernel/real2.S renamed from parisc/kernel/real2.S.orig +1 -10
@@ -147,17 +147,9 @@ .text rfi_virt2real: /* switch to real mode... */ - ssm 0,0 /* See "relied upon translation" */ - nop /* PA 2.0 Arch. F-5 */ - nop - nop - nop - nop - nop - nop - nop + pcxt_ssm_bug - rsm (PSW_SM_Q|PSW_SM_I),%r0 /* disable Q & I bits to load
iia queue */
+ rsm PSW_SM_Q+PSW_SM_I,%r0 /* prep to load iia queue */
mtctl %r0, %cr17 /* Clear IIASQ tail */
mtctl %r0, %cr17 /* Clear IIASQ head */
load32 PA(rfi_v2r_1), %r1
@@ -184,17 +176,9 @@
.text
.align 128
rfi_real2virt:
- ssm 0,0 /* See "relied upon translation" */
- nop /* PA 2.0 Arch. F-5 */
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- rsm PSW_SM_Q,%r0 /* disable Q bit to load iia queue */
+ pcxt_ssm_bug
+
+ rsm PSW_SM_Q+PSW_SM_I,%r0 /* prep to load iia queue */
mtctl %r0, %cr17 /* Clear IIASQ tail */
mtctl %r0, %cr17 /* Clear IIASQ head */
load32 (rfi_r2v_1), %r1
asm-parisc/assembly.h renamed from asm-parisc/assembly.h.orig +18 -0
@@ -450,5 +450,23 @@ REST_CR (%cr22, PT_PSW (\regs)) .endm +#if defined(CONFIG_PA7000 ) + .macro pcxt_ssm_bug + /* Create a "relied upon translation" PA 2.0 Arch. page F-4 and F-5 + * The ssm is necessary due to a PCXT bug. Ie not needed for 64-bit. + */ + ssm 0,%r0 +nop /* 1 */ + nop /* 2 */ +nop /* 3 */ + nop /* 4 */ +nop /* 5 */ + nop /* 6 */ + nop/* 7 */ + .endm +#else +#define pcxt_ssm_bug/* Thank $DIETY. You don't have brain damaged HW. */ +#endif +#endif /* __ASSEMBLY__ */ #endif
asm-parisc/psw.h renamed from asm-parisc/psw.h.orig +11 -17
@@ -9,6 +9,16 @@#define PSW_G 0x00000040/* PA1.x only */ #define PSW_O 0x00000080/* PA2.0 only */ +/* ssm/rsm instructions number PSW_W and PSW_E differently */ +#define PSW_SM_I PSW_I/* Enable External Interrupts */ +#define PSW_SM_D PSW_D +#define PSW_SM_P PSW_P +#define PSW_SM_Q PSW_Q/* Enable Interrupt State Collection */ +#define PSW_SM_R PSW_R/* Enable Recover Counter Trap */ +#define PSW_SM_W 0x200/* PA2.0 only : Enable Wide Mode */ + +#define PSW_SM_QUIET PSW_SM_R+PSW_SM_Q+PSW_SM_P+PSW_SM_D+PSW_SM_I +#define PSW_CB 0x0000ff00#define PSW_M 0x00010000
@@ -31,32 +41,20 @@#define PSW_Y 0x80000000/* PA1.x only */ #ifdef __LP64__ -#define PSW_HI_CB 0x000000ff/* PA2.0 only */ +# define PSW_HI_CB 0x000000ff/* PA2.0 only */ #endif -/* PSW bits to be used with ssm/rsm */ -#define PSW_SM_I 0x1 -#define PSW_SM_D 0x2 -#define PSW_SM_P 0x4 -#define PSW_SM_Q 0x8 -#define PSW_SM_R 0x10 -#define PSW_SM_F 0x20 -#define PSW_SM_G 0x40 -#define PSW_SM_O 0x80 -#define PSW_SM_E 0x100 -#define PSW_SM_W 0x200 -#ifdef __LP64__ -# define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I) -# define KERNEL_PSW (PSW_W | PSW_C | PSW_Q | PSW_P | PSW_D) -# define REAL_MODE_PSW (PSW_W | PSW_Q) -# define USER_PSW_MASK (PSW_W | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V |
PSW_CB)
-# define USER_PSW_HI_MASK (PSW_HI_CB)
-#else
-# define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I) -# define KERNEL_PSW (PSW_C | PSW_Q | PSW_P | PSW_D) -# define REAL_MODE_PSW (PSW_Q) -# define USER_PSW_MASK (PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB) +# define USER_PSW_HI_MASK PSW_HI_CB +# define WIDE_PSW PSW_W
+#else
+# define WIDE_PSW 0
#endif
+/* Used when setting up for rfi */
+#define KERNEL_PSW (WIDE_PSW | PSW_C | PSW_Q | PSW_P | PSW_D) +#define REAL_MODE_PSW (WIDE_PSW | PSW_Q) +#define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V
| PSW_CB)
+#define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
+
#endif
====<>====
notes:
o already test with success for b180, d380 (32bit smp) following:
#define PSW_BITS PSW_Q+PSW_I+PSW_D+PSW_P+PSW_R
o jda also suggesting;
.align 128srdis_done:
(and most probably also for 'fdtdone:' I will try to test too)
Hth and thanks again,
Joel
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Hello Grant,
Quoted 1 line
mmm aleady reach to reboot without pb (b180 32bit and b2k 64bit) :-)
unfortunately b180 pb is always there:
Backtrace: [<1015146c>] cache_grow+0xd4/0x1ac [<101516ec>] cache_alloc_refill+0x1a8/0x26c [<10151a10>] kmem_cache_alloc+0x48/0x4c [<101b634c>] ext3_alloc_inode+0x18/0x40 [<10187158>] alloc_inode+0x28/0x1a0 [<10187dac>] new_inode+0x10/0x8c [<101aaf90>] ext3_new_inode+0xc4/0x744 [<101b43a0>] ext3_mkdir+0xc0/0x38c [<1017c8c8>] vfs_mkdir+0xcc/0x12c [<1017c9ec>] sys_mkdir+0xc4/0x120 [<1010d120>] syscall_exit+0x0/0x14
Kernel Fault: Code=3D15 regs=3D14cb0540 (Addr=3D27b274cc)
YZrvWESTHLNXBCVMcbcbcbcbOGFRQPDI
PSW: 00000000000001001110011100001111 Not tainted
r00-03 00000000 10517e58 1015146c 105044f8 r04-07 17623000 100e36e0 00000010 00000050 r08-11 00000001 14cd43c0 1216d5d4 000001ed r12-15 16eccdd4 000041ed 0004db4e 000edec8 r16-19 000edfc8 000edda8 00000000 27b274f8 r20-23 27b274bc 000001bc 000001c8 00000050 r24-27 105044bc 17623000 100e36e0 10400010 r28-31 27b274bc 00000000 14cb0540 10153dc4 sr0-3 00000000 00000000 00000000 00000a4b sr4-7 00000000 00000000 00000000 00000000
IASQ: 00000000 00000000 IAOQ: 101511f4 101511f8
IIR: 6b800020 ISR: 00000000 IOR: 27b274cc
CPU: 0 CR30: 14cb0000 CR31: 10464000
ORIG_R28: 00000000
IAOQ[0]: alloc_slabmgmt+0x30/0x6c IAOQ[1]: alloc_slabmgmt+0x34/0x6c RP(r2): cache_grow+0xd4/0x1ac
Kernel panic - not syncing: Kernel Fault <0>Rebooting in 120 seconds..
Sorry,
Joel
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Quoted 3 lines · Grant Grundler
*sigh*. The ssm 0,0/nop * 8/rsm sequence isn't so obvious. Richard Hirst added this comment to
entry.Sin 2001:
* The ssm is necessary due to a PCXT bug
Here's a new patch WITHOUT the s/__lp64__/CONFIG_64BIT/ changes.
Please review.
grant
Index: arch/parisc/kernel/entry.S
===================================================================
RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/entry.S,v retrieving revision 1.27
parisc/kernel/entry.S +7 -16
@@ -893,9 +893,6 @@ _switch_to_ret: * this way, then we will need to copy %sr3 in to PT_SR[3..7], and * adjust IASQ[0..1]. * - * Note that the following code uses a "relied upon translation". - * See the parisc ACD for details. The ssm is necessary due to a - * PCXT bug. */ .align 4096
@@ -990,24 +987,18 @@ intr_restore: rest_fp %r1 rest_general %r29 - /* Create a "relied upon translation" PA 2.0 Arch. F-5 */ - ssm 0,%r0 - nop - nop - nop - nop - nop - nop - nop + pcxt_ssm_bug tophys_r1 %r29 - rsm (PSW_SM_Q|PSW_SM_P|PSW_SM_D|PSW_SM_I),%r0 + rsm PSW_SM_QUIET,%r0 /* prepare for rfi */ /* Restore space id's and special cr's from PT_REGS - * structure pointed to by r29 */ + * structure pointed to by r29 + */ rest_specials %r29 - /* Important: Note that rest_stack restores r29 - * last (we are using it)! It also restores r1 and r30. */ + /* IMPORTANT: rest_stack restores r29 last (we are using it)! + * It also restores r1 and r30. + */ rest_stack rfi
Index: arch/parisc/kernel/head.S
===================================================================
RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/head.S,v retrieving revision 1.11
parisc/kernel/head.S +4 -22
@@ -254,32 +254,14 @@ $is_pa20: $install_iva: mtctl %r10,%cr14 -#ifdef __LP64__ b aligned_rfi nop - .align 256 + .align 128 aligned_rfi: - ssm 0,0 - nop /* 1 */ - nop /* 2 */ - nop /* 3 */ - nop /* 4 */ - nop /* 5 */ - nop /* 6 */ - nop /* 7 */ - nop /* 8 */ -#endif - -#ifdef __LP64__ /* move to psw.h? */ -#define PSW_BITS PSW_Q+PSW_I+PSW_D+PSW_P+PSW_R -#else -#define PSW_BITS PSW_SM_Q -#endif - -$rfi: - /* turn off troublesome PSW bits */ - rsm PSW_BITS,%r0 + pcxt_ssm_bug + rsm PSW_SM_QUIET,%r0 /* off troublesome PSW bits */ + /* Don't need NOPs, have 8 compliant insn below */ /* kernel PSW: * - no interruptions except HPMC and TOC (which are handled by PDC)
Index: arch/parisc/kernel/pacache.S
===================================================================
RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/pacache.S,v retrieving revision 1.17
parisc/kernel/pacache.S +27 -46
139 lines not on this page · raw message
Index: arch/parisc/kernel/real2.S
===================================================================
RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/real2.S,v retrieving revision 1.17
parisc/kernel/real2.S +5 -21
@@ -147,17 +147,9 @@ restore_control_regs: .text rfi_virt2real: /* switch to real mode... */ - ssm 0,0 /* See "relied upon translation" */ - nop /* PA 2.0 Arch. F-5 */ - nop - nop - nop - nop - nop - nop - nop + pcxt_ssm_bug - rsm (PSW_SM_Q|PSW_SM_I),%r0 /* disable Q & I bits to load iia queue */ + rsm PSW_SM_Q+PSW_SM_I,%r0 /* prep to load iia queue */ mtctl %r0, %cr17 /* Clear IIASQ tail */ mtctl %r0, %cr17 /* Clear IIASQ head */ load32 PA(rfi_v2r_1), %r1
@@ -184,17 +176,9 @@ rfi_v2r_1: .text .align 128 rfi_real2virt: - ssm 0,0 /* See "relied upon translation" */ - nop /* PA 2.0 Arch. F-5 */ - nop - nop - nop - nop - nop - nop - nop - - rsm PSW_SM_Q,%r0 /* disable Q bit to load iia queue */ + pcxt_ssm_bug + + rsm PSW_SM_Q+PSW_SM_I,%r0 /* prep to load iia queue */ mtctl %r0, %cr17 /* Clear IIASQ tail */ mtctl %r0, %cr17 /* Clear IIASQ head */ load32 (rfi_r2v_1), %r1
Index: include/asm-parisc/assembly.h
===================================================================
RCS file: /var/cvs/linux-2.6/include/asm-parisc/assembly.h,v retrieving revision 1.10
asm-parisc/assembly.h +18 -0
@@ -450,5 +450,23 @@ REST_CR (%cr22, PT_PSW (\regs)) .endm +#if defined(CONFIG_PA7000 ) + .macro pcxt_ssm_bug + /* Create a "relied upon translation" PA 2.0 Arch. page F-4 and F-5 + * The ssm is necessary due to a PCXT bug. Ie not needed for 64-bit. + */ + ssm 0,%r0 +nop /* 1 */ + nop /* 2 */ +nop /* 3 */ + nop /* 4 */ +nop /* 5 */ + nop /* 6 */ + nop/* 7 */ + .endm +#else +#define pcxt_ssm_bug/* Thank $DEITY. You don't have brain damaged HW. */ +#endif +#endif /* __ASSEMBLY__ */ #endif
Index: include/asm-parisc/psw.h
===================================================================
RCS file: /var/cvs/linux-2.6/include/asm-parisc/psw.h,v retrieving revision 1.1
asm-parisc/psw.h +23 -25
62 lines not on this page · raw message
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Quoted 1 line · Grant Grundler
Here's a new patch WITHOUT the s/__lp64__/CONFIG_64BIT/ changes.
I tested this patch on a500 and the kernel blew up when /etc/init.d/firewall script was started.
Something in iptables triggered a WARN_ON in our smp_call_function. Thinking this might be related to the missing "ssm/nop*8" sequence, I removed the ifdef around the pcxt_ssm_bug so it's always used. Still panics in basically the same way:
....
Setting up IP spoofing protection: rp_filter.
Configuring network interfaces...done.
Starting portmap daemon: portmap.
Setting the System Clock using the Hardware Clock as reference... System Clock set. Local time: Thu Apr 28 07:29:51 PDT 2005
eth10: Setting full-duplex based on MII#1 link partner capability of 41e1. Initializing random number generator...done.
Recovering nvi editor sessions... done.
Setting up X server socket directory /tmp/.X11-unix...tg3: eth11: Link is up at 1000 Mbps, full duplex.
tg3: eth11: Flow control is off for TX and off for RX.
done.
Setting up ICE socket directory /tmp/.ICE-unix...done.
INIT: Entering runlevel: 2
Starting system log daemon: syslogd.
Starting kernel log daemon: klogd.
Starting firewall (iptables):Badness in smp_call_function at arch/parisc/kernel/smp.c:340
Backtrace: [<0000000010114d70>] dump_stack+0x18/0x28 [<000000001011f74c>] smp_call_function+0x474/0x480 [<00000000101ab470>] unmap_vm_area+0xa0/0x328 [<00000000101abe4c>] remove_vm_area+0x94/0xd8 [<00000000101abf3c>] __vunmap+0xac/0x1e0 [<00000000101ac098>] vfree+0x28/0x80 [<0000000000398bb0>] do_ipt_set_ctl+0x1040/0x1268 [ip_tables] [<00000000103c8598>] nf_sockopt+0x200/0x3c0 [<00000000103c8774>] nf_setsockopt+0x1c/0x28 [<00000000103e4b98>] ip_setsockopt+0x288/0xdc0 [<0000000010408324>] raw_setsockopt+0x3c/0x90 [<00000000103aad70>] sock_common_setsockopt+0x28/0x38 [<00000000103a6f68>] sys_setsockopt+0x90/0xf8 [<00000000103cb2a0>] compat_sys_setsockopt+0x538/0x548 [<0000000010107fb4>] syscall_exit+0x0/0x14
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 1
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 2
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 3
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 4
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 5
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 6
...
Looks like unmap_vm_area() has changed for every 2.6.12-rc release. I expect the WARN_ON is invoked via flush_tlb_kernel_range(). Anyone have a clue what's up here?
thanks,
grant
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Hello Grant,
Quoted 57 lines · Grant Grundler
Quoted 1 line · Grant Grundler
Here's a new patch WITHOUT the s/__lp64__/CONFIG_64BIT/ changes.
I tested this patch on a500 and the kernel blew up when
/etc/init.d/firewallscript was started.
Something in iptables triggered aWARN_ONin oursmp_call_function. Thinking this might be related to the missing "ssm/nop*8" sequence, I removed the ifdef around thepcxt_ssm_bugso it's always used. Still panics in basically the same way:....
Setting up IP spoofing protection:rp_filter.
Configuring network interfaces...done.
Starting portmap daemon: portmap.Setting the System Clock using the Hardware Clock as reference... System Clock set. Local time: Thu Apr 28 07:29:51 PDT 2005
eth10: Setting full-duplex based on MII#1 link partner capability of 41e1. Initializing random number generator...done.
Recovering nvi editor sessions... done.
Setting up X server socket directory/tmp/.X11-unix...tg3: eth11: Link is up at 1000 Mbps, full duplex.
tg3: eth11: Flow control is off for TX and off for RX.
done.
Setting up ICE socket directory/tmp/.ICE-unix...done.
INIT: Entering runlevel: 2
Starting system log daemon: syslogd.
Starting kernel log daemon: klogd.
Starting firewall (iptables):Badness insmp_call_functionatarch/parisc/kernel/smp.c:340Backtrace: [<0000000010114d70>] dump_stack+0x18/0x28 [<000000001011f74c>] smp_call_function+0x474/0x480 [<00000000101ab470>] unmap_vm_area+0xa0/0x328 [<00000000101abe4c>] remove_vm_area+0x94/0xd8 [<00000000101abf3c>] __vunmap+0xac/0x1e0 [<00000000101ac098>] vfree+0x28/0x80 [<0000000000398bb0>] do_ipt_set_ctl+0x1040/0x1268 [ip_tables] [<00000000103c8598>] nf_sockopt+0x200/0x3c0 [<00000000103c8774>] nf_setsockopt+0x1c/0x28 [<00000000103e4b98>] ip_setsockopt+0x288/0xdc0 [<0000000010408324>] raw_setsockopt+0x3c/0x90 [<00000000103aad70>] sock_common_setsockopt+0x28/0x38 [<00000000103a6f68>] sys_setsockopt+0x90/0xf8 [<00000000103cb2a0>] compat_sys_setsockopt+0x538/0x548 [<0000000010107fb4>] syscall_exit+0x0/0x14SMP CALL FUNCTION TIMED OUT! (cpu=0), try 1
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 2
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 3
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 4
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 5
SMP CALL FUNCTION TIMED OUT! (cpu=0), try 6
...
Quoted 4 lines
Looks like
unmap_vm_area()has changed for every 2.6.12-rc release. I expect theWARN_ONis invoked viaflush_tlb_kernel_range(). Anyone have a clue what's up here?
no sorry but I tested pa8000 64bit up on b2k (but no fw iptable :-( ) and I didn't encounter any pb:
o my stress test during about 20h: no panic, no error, ... :-)
btw I found another way to make panicing 32bit:
o vi a big file (e.g. a kernel objdump) and launch a dG cmd
(it takes obviously some minutes to copy the recovery file)
then try to save: no pb with 64bit on b2k but panicing quickly with 32bit on b180
I also tested on pa8000 32bit smp on the d380:
o boot fine;
o but hanging on the smp_call_function() WARN_ON() when simply vi my big file (need to check without patch?)
that said, iirc jda already mentioned such fw iptable pb (but not yet find the time to track down in more, sorry :-( )
hth,
Joel
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Quoted 9 lines · Grant Grundler
Quoted 1 line · Grant Grundler
Here's a new patch WITHOUT the s/__lp64__/CONFIG_64BIT/ changes.
I tested this patch on a500 and the kernel blew up when
/etc/init.d/firewallscript was started.
Something in iptables triggered aWARN_ONin oursmp_call_function. Thinking this might be related to the missing "ssm/nop*8" sequence, I removed the ifdef around thepcxt_ssm_bugso it's always used. Still panics in basically the same way:
I've restored the #ifdef CONFIG_64BIT around pcxt_ssm_bug so my 64-bit kernels don't use it *and* disabled /etc/init.d/firewall so iptables doesn't get invoked. The system boots to a login prompt but when I ssh to the box, I get the following WARNON with several different stack traces:
Badness in smp_call_function at arch/parisc/kernel/smp.c:340
Backtrace: [<0000000010114cf0>] dump_stack+0x18/0x28 [<000000001011f6cc>] smp_call_function+0x474/0x480 [<00000000101130f8>] flush_tlb_all+0x108/0x238 [<00000000101a6e88>] exit_mmap+0x238/0x2a0 [<000000001014928c>] mmput+0xdc/0x200 [<00000000101ce82c>] flush_old_exec+0x8c4/0xe38 [<000000001012188c>] load_elf_binary+0x56c/0x1970 [<00000000101cf304>] search_binary_handler+0x174/0x580 [<00000000102000a8>] compat_do_execve+0x1d0/0x3e0 [<0000000010124700>] sys32_execve+0x70/0xf8 [<0000000010107e04>] sys32_execve_wrapper+0x1c/0x30
Badness in smp_call_function at arch/parisc/kernel/smp.c:340
Backtrace: [<0000000010114cf0>] dump_stack+0x18/0x28 [<000000001011f6cc>] smp_call_function+0x474/0x480 [<00000000101130f8>] flush_tlb_all+0x108/0x238 [<000000001019e0f0>] unmap_vmas+0x528/0xb78 [<00000000101a6d5c>] exit_mmap+0x10c/0x2a0 [<000000001014928c>] mmput+0xdc/0x200 [<00000000101ce82c>] flush_old_exec+0x8c4/0xe38 [<000000001012188c>] load_elf_binary+0x56c/0x1970 [<00000000101cf304>] search_binary_handler+0x174/0x580 [<00000000102000a8>] compat_do_execve+0x1d0/0x3e0 [<0000000010124700>] sys32_execve+0x70/0xf8 [<0000000010107e04>] sys32_execve_wrapper+0x1c/0x30
Besides the basic issue, this also implies flush_tlb_all() is called twice in the same code path. That might be ok if flush_tlb_all() took parameters, but it does not.
Any clue what the basic issue is here?
grant
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Quoted 19 lines · Grant Grundler
Quoted 9 lines
Quoted 1 line · Grant Grundler
Here's a new patch WITHOUT the s/__lp64__/CONFIG_64BIT/ changes.
I tested this patch on a500 and the kernel blew up when
/etc/init.d/firewallscript was started.
Something in iptables triggered aWARN_ONin oursmp_call_function. Thinking this might be related to the missing "ssm/nop*8" sequence, I removed the ifdef around thepcxt_ssm_bugso it's always used. Still panics in basically the same way:I've restored the #ifdef
CONFIG_64BITaroundpcxt_ssm_bugso my 64-bit kernels don't use it *and* disabled/etc/init.d/firewallso iptables doesn't get invoked. The system boots to a login prompt but when I ssh to the box, I get the following WARNON with several different stack traces:Badness in
smp_call_functionatarch/parisc/kernel/smp.c:340
Quoted 8 lines
Backtrace: [<0000000010114cf0>] dump_stack+0x18/0x28 [<000000001011f6cc>] smp_call_function+0x474/0x480 [<00000000101130f8>] flush_tlb_all+0x108/0x238Besides the basic issue, this also implies
flush_tlb_all()is called twice in the same code path. That might be ok ifflush_tlb_all()took parameters, but it does not.
Twice?
Quoted 1 line
Any clue what the basic issue is here?
flush_tlb_all doesn't call anything. I'm guessing but I think this implies that smp_call_function is getting called because a TLB miss fault has occured. It appears from the backtrace that the fault has occurred in the part of flush_tlb_all with the REAL_MODE_PSW flags set (W and Q). Interrupts are off, so this causes the warning.
Dave
Signature · 6 lines
J. David Anglin [email protected] National Research Council of Canada (613) 990-0752 (FAX: 952-6602) _______________________________________________ parisc-linux mailing list [email protected] http://lists.parisc-linux.org/mailman/listinfo/parisc-linux
Quoted 5 lines · John David Anglin
Quoted 3 lines
Besides the basic issue, this also implies
flush_tlb_all()is called twice in the same code path. That might be ok ifflush_tlb_all()took parameters, but it does not.Twice?
Yes. Once from
exit_mmap() -> flush_tlb_mm() -> flush_tlb_all() and again unmap_vmas() -> unmap_page_range() -> tlb_end_vma() -> flush_tlb_range() -> flush_tlb_all()
But flush_tlb_range() only calls flush_tlb_all() IFF:
...
if (npages >= 512) /* XXX arbitrary, should be tuned */
flush_tlb_all();
else {...
That may be why I'm not seeing it more often.
jejb, any insight here?
Quoted 3 lines
Quoted 1 line
Any clue what the basic issue is here?
flush_tlb_alldoesn't call anything.
Eh?! I'm looking at arch/parisc/mm/init.c and it is:
...
}
spin_unlock(&sid_lock);
on_each_cpu((void (*)(void *))flush_tlb_all_local, NULL, 1, 1);
if (do_recycle) {...
Quoted 5 lines
I'm guessing but I think this
implies thatsmp_call_functionis getting called because a TLB miss fault has occured. It appears from the backtrace that the fault has occurred in the part offlush_tlb_allwith theREAL_MODE_PSWflags set (W and Q). Interrupts are off, so this causes the warning.
Wouldn't we see more gunk on the stack trace?
If I'm reading the PA 2.0 Arch correctly, PDTLB/PDTLBE insn can NOT cause a TLB Miss. But I don't really know.
It also doesn't make sense for a TLB miss if we are in REAL_MODE.
thanks,
grant
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Quoted 3 lines
Quoted 1 line
flush_tlb_alldoesn't call anything.Eh?! I'm looking at
arch/parisc/mm/init.cand it is:
Oops, I was looking at flush_tlb_all_local. It's still not obvious how we got to the warning.
Dave
Signature · 6 lines
J. David Anglin [email protected] National Research Council of Canada (613) 990-0752 (FAX: 952-6602) _______________________________________________ parisc-linux mailing list [email protected] http://lists.parisc-linux.org/mailman/listinfo/parisc-linux
Quoted 3 lines · Grant Grundler
That may be why I'm not seeing it more often.
jejb, any insight here?
Yes, but you're not going to like it. For this to show up twice for the same process, we must have done a full tlb flush so often that we've completely cycled around the spaces.
This, in turn, looks to be because we have a total screw up in our tlb flushing implementation. What's supposed to happen is that the
tlb_gather_mmu()
...tlb_finish_mmu()
is supposed simply to say "I promise to flush the tlb when I'm done, so don't actually flush anywhere within, just add the dirty tlbs to the list".
Unfortunately, our implementation of tlb_end_vma() meaning either flush this vma or add it to the tlb list seems to flush every time, which is why we do this so often.
James
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Quoted 10 lines · Grant Grundler
Quoted 5 lines · Grant Grundler
The example code is just that, an example:
SSM 0,gr0 ; initial RSM, SSM, or MTSM
...AFAICT, that sequence does nothing but burn some cycles.
*sigh*. The ssm 0,0/nop * 8/rsm sequence isn't so obvious. Richard Hirst added this comment to
entry.Sin 2001:
* The ssm is necessary due to a PCXT bug
Dave Anglin (offlist) pointed out it's part of the PA 2.0 Architecture:
| The first bullet in point 2., page F-4: | | The RSM or MTSM instruction which sets the PSW Q-bit (the clearing | RSM or MTSM) is preceded by another RSM, SSM, or MTSM instruction | which does not affect the Q-bit and which appears at least 8 | instructions prior.
Kudos to Dave for being persistent. I had read this before but didn't really understand what it said.
My copy of "PA-RISC 1.1 Architecture and Instruction Set" (3rd Edition, Feb 1994) has change bars in front of the first two bullets on page 3-20. This suggests it was added later - maybe after finding the "feature" in PCX-T.
I've got research to do before moving forward with the pcxt_ssm_bug patch.
thanks,
grant
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