NAND: AMD Au1550 driver reads write only register

Hello.

I have noticed that during the last commit to AMD Au1550 NAND driver the
old buglet was reintroduced: as MEM_STNDCTL register is write only, and seem to always read as 0x31, read-modify-write of it in au1xxx_nand_init() will cause undesirable effect of enabling -RCS0/1 pin override (bits 4/5 of this reg.), thus possibly causing a contention on the static bus when the NOR flash (which uses -RCS0) or board control status regs. (using -RCS2) are read. Luckily, this now goes away with a first NAND access, since au1550_hwcontrol() doesn't try to read this register before writing anymore.
There's another issue with that though -- to be addressed by the next
patch...

WBR, Sergei

plain text document attachment (Au1550-NAND-STNDCTL-write-only.patch)

Signed-off-by Sergei Shtylyov <[email protected]>

Index: au1550nd.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/nand/au1550nd.c,v retrieving revision 1.12
diff -a -u -p -r1.12 au1550nd.c

au1550nd.c +2 -5

@@ -343,11 +343,8 @@ int __init au1xxx_nand_init (void)
 	au1550_mtd->priv = this;
 
 
-	/* disable interrupts */
-	au_writel(au_readl(MEM_STNDCTL) & ~(1<<8), MEM_STNDCTL);
- 
-	/* disable NAND boot */
-	au_writel(au_readl(MEM_STNDCTL) & ~(1<<0), MEM_STNDCTL);
+	/* MEM_STNDCTL: disable ints, disable nand boot */
+	au_writel(0, MEM_STNDCTL);
 
 #ifdef CONFIG_MIPS_PB1550
 	/* set gpio206 high */