Add the cpu and board specific code for MPC8349E rev3.1 MDS

PATCH New Xie Xiaobo 1 participant 1 message Feb 14, 2007 2 messages not in the archive

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Xie Xiaobo

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2007-02-14 10:26 UTC #2 lore raw

PATCH 1/3 Add the cpu and board specific code for MPC8349E rev3.1 MDS

MPC8349E rev3.1 have new spridr,and PVR value,
The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM.

Signed-off-by Xie Xiaobo<[email protected]>

---
This patch applies to the mpc83xx branch of the opensource.freescale.com u-boot-83xx.git tree

 cpu/mpc83xx/cpu.c             |   17 +++++++++++++--
 include/configs/MPC8349EMDS.h |   44 +++++++++++++++++++++++++++++++++-------
 include/mpc83xx.h             |   13 ++++++++++-
 3 files changed, 61 insertions(+), 13 deletions(-)

cpu/mpc83xx/cpu.c +14 -3

index c24a20f..9f55f18 100644
@@ -56,30 +56,38 @@ int checkcpu(void)
 	switch(spridr) {
 	case SPR_8349E_REV10:
 	case SPR_8349E_REV11:
+	case SPR_8349E_REV31:
 		puts("MPC8349E, ");
 		break;
 	case SPR_8349_REV10:
 	case SPR_8349_REV11:
+	case SPR_8349_REV31:
 		puts("MPC8349, ");
 		break;
 	case SPR_8347E_REV10_TBGA:
 	case SPR_8347E_REV11_TBGA:
+	case SPR_8347E_REV31_TBGA:
 	case SPR_8347E_REV10_PBGA:
 	case SPR_8347E_REV11_PBGA:
+	case SPR_8347E_REV31_PBGA:
 		puts("MPC8347E, ");
 		break;
 	case SPR_8347_REV10_TBGA:
 	case SPR_8347_REV11_TBGA:
+	case SPR_8347_REV31_TBGA:
 	case SPR_8347_REV10_PBGA:
 	case SPR_8347_REV11_PBGA:
+	case SPR_8347_REV31_PBGA:
 		puts("MPC8347, ");
 		break;
 	case SPR_8343E_REV10:
 	case SPR_8343E_REV11:
+	case SPR_8343E_REV31:
 		puts("MPC8343E, ");
 		break;
 	case SPR_8343_REV10:
 	case SPR_8343_REV11:
+	case SPR_8343_REV31:
 		puts("MPC8343, ");
 		break;
 	case SPR_8360E_REV10:

@@ -109,12 +117,15 @@ int checkcpu(void)
 		puts("MPC8321, ");
 		break;
 	default:
-		puts("Rev: Unknown\n");
-		return -1;	/* Not sure what this is */
+		puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
+		return 0;
 	}
 
 #if defined(CONFIG_MPC834X)
-	printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock));
+	/* Multiple revisons of 834x processors may have the same SPRIDR value.
+	 * So use PVR to identify the revision number.
+	 */
+	printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
 #else
 	printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
 #endif

include/configs/MPC8349EMDS.h +36 -8

89 lines not on this page · raw message

include/mpc83xx.h +11 -2

index 1b62f81..73f2721 100644
@@ -68,6 +68,15 @@
 #define SPR_8343E_REV11			0x80360101
 #define SPR_8343_REV11			0x80370101
 
+#define SPR_8349E_REV31			0x80300300
+#define SPR_8349_REV31			0x80310300
+#define SPR_8347E_REV31_TBGA		0x80320300
+#define SPR_8347_REV31_TBGA		0x80330300
+#define SPR_8347E_REV31_PBGA		0x80340300
+#define SPR_8347_REV31_PBGA		0x80350300
+#define SPR_8343E_REV31			0x80360300
+#define SPR_8343_REV31			0x80370300
+
 #define SPR_8360E_REV10			0x80480010
 #define SPR_8360_REV10			0x80490010
 #define SPR_8360E_REV11			0x80480011

@@ -573,8 +582,8 @@
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */
-#define TIMING_CFG2_CPO			0x0F000000
-#define TIMING_CFG2_CPO_SHIFT		24
+#define TIMING_CFG2_CPO			0x0F800000
+#define TIMING_CFG2_CPO_SHIFT		23
 #define TIMING_CFG2_ACSM		0x00080000
 #define TIMING_CFG2_WR_DATA_DELAY	0x00001C00
 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT	10

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