mx31: Move EHCI definitions to ehci-fsl.h

PATCH Superseded Benoît Thébaudeau 4 participants 54 messages Nov 5, 2012 – Nov 16, 2012

Subsystems (5)

Arm (32-bit) USB Arm i.MX and Layerscape Arm/actions semi architecture +1 more subsystems

lore

Share & tools

lore

Benoît Thébaudeau

author

2012-11-05 20:09 UTC #0 lore raw

PATCH 1/13 mx31: Move EHCI definitions to ehci-fsl.h

The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../arch/arm/include/asm/arch-mx31/imx-regs.h      |   26 --------------------
 .../include/usb/ehci-fsl.h                         |   22 +++++++++++++++++
 2 files changed, 22 insertions(+), 26 deletions(-)

arch/arm/include/asm/arch-mx31/imx-regs.h +0 ~~-26~~

index 8fd3d08..01a849d 100644
@@ -896,32 +896,6 @@ struct esdc_regs {
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
 #define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
 
-/* USB portsc */
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
-#define MXC_EHCI_FORCE_FS		(1 << 24)
-#define MXC_EHCI_UTMI_8BIT		(0 << 28)
-#define MXC_EHCI_UTMI_16BIT		(1 << 28)
-#define MXC_EHCI_SERIAL			(1 << 29)
-#define MXC_EHCI_MODE_UTMI		(0 << 30)
-#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
-#define MXC_EHCI_MODE_ULPI		(2 << 30)
-#define MXC_EHCI_MODE_SERIAL		(3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
-#define MXC_EHCI_INTERFACE_MASK		(0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
-#define MXC_EHCI_TTL_ENABLED		(1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY		(1 << 7)
-#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
-#define MXC_EHCI_IPPUE_UP		(1 << 9)
-
 /*
  * CSPI register definitions
  */

include/usb/ehci-fsl.h +22 -0

index 2869302..4dee5b0 100644
@@ -246,9 +246,31 @@ struct usb_ehci {
 /*
  * For MXC SOCs
  */
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
+#define MXC_EHCI_FORCE_FS		(1 << 24)
+#define MXC_EHCI_UTMI_8BIT		(0 << 28)
+#define MXC_EHCI_UTMI_16BIT		(1 << 28)
+#define MXC_EHCI_SERIAL			(1 << 29)
+#define MXC_EHCI_MODE_UTMI		(0 << 30)
+#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
+#define MXC_EHCI_MODE_ULPI		(2 << 30)
+#define MXC_EHCI_MODE_SERIAL		(3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
+#define MXC_EHCI_INTERFACE_MASK		(0xf)
+
 #define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
 #define MXC_EHCI_TTL_ENABLED		(1 << 6)
+
 #define MXC_EHCI_INTERNAL_PHY		(1 << 7)
+#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
+#define MXC_EHCI_IPPUE_UP		(1 << 9)
 
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);

Benoît Thébaudeau

author

2012-11-05 20:10 UTC #1 lore raw

PATCH 2/13 ehci-mxc: Clean up

Clean up ehci-mxc:
- Remove useless #if's.
- Fix identation.
- Issue a #error if used with an unsupported platform.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../drivers/usb/host/ehci-mxc.c                    |   86 +++++++++-----------
 1 file changed, 40 insertions(+), 46 deletions(-)

drivers/usb/host/ehci-mxc.c +40 ~~-46~~

index a38bc9c..e21f2c5 100644
@@ -28,14 +28,11 @@
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
-#ifdef CONFIG_MX25
 #define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
 #define MX25_USB_CTRL_HSTD_BIT		(1<<5)
 #define MX25_USB_CTRL_USBTE_BIT		(1<<4)
 #define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
-#endif
 
-#ifdef CONFIG_MX31
 #define MX31_OTG_SIC_SHIFT	29
 #define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
 #define MX31_OTG_PM_BIT		(1 << 24)

@@ -49,59 +46,56 @@
 #define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
 #define MX31_H1_PM_BIT		(1 << 8)
 #define MX31_H1_DT_BIT		(1 << 4)
-#endif
 
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
 
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25)
 	v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
 		MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#endif
+#elif defined(CONFIG_MX31)
+	v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
 
-#ifdef CONFIG_MX31
-		v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-
-		switch (port) {
-		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
-
-			break;
-		case 1: /* H1 port */
-			v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
-				MX31_H1_DT_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-						<< MX31_H1_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_H1_PM_BIT;
-
-			if (!(flags & MXC_EHCI_TTL_ENABLED))
-				v |= MX31_H1_DT_BIT;
-
-			break;
-		case 2:	/* H2 port */
-			v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
-				MX31_H2_DT_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-						<< MX31_H2_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_H2_PM_BIT;
-
-			if (!(flags & MXC_EHCI_TTL_ENABLED))
-				v |= MX31_H2_DT_BIT;
-
-			break;
-		default:
-			return -EINVAL;
-		}
-#endif
+	switch (port) {
+	case 0:	/* OTG port */
+		v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_OTG_PM_BIT;
+
+		break;
+	case 1: /* H1 port */
+		v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
 
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_H1_PM_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX31_H1_DT_BIT;
+
+		break;
+	case 2:	/* H2 port */
+		v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_H2_PM_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX31_H2_DT_BIT;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+#else
+#error MXC EHCI USB driver not supported on this platform
+#endif
 	writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+
 	return 0;
 }

Benoît Thébaudeau

author

2012-11-05 20:10 UTC #2 lore raw

PATCH 3/13 ehci-mx5: Clean up

In reply to Benoît Thébaudeau

Clean up ehci-mx5:
- Fix column alignments.
- Fix comments.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../drivers/usb/host/ehci-mx5.c                    |   34 ++++++++++----------
 1 file changed, 17 insertions(+), 17 deletions(-)

drivers/usb/host/ehci-mx5.c +17 ~~-17~~

index 9a2c295..66ab25d 100644
@@ -29,9 +29,9 @@
 #define MX5_USBOTHER_REGS_OFFSET 0x800
 
 
-#define MXC_OTG_OFFSET		0
-#define MXC_H1_OFFSET		0x200
-#define MXC_H2_OFFSET		0x400
+#define MXC_OTG_OFFSET			0
+#define MXC_H1_OFFSET			0x200
+#define MXC_H2_OFFSET			0x400
 
 #define MXC_USBCTRL_OFFSET		0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET	0x8

@@ -40,23 +40,23 @@
 #define MXC_USBH2CTRL_OFFSET		0x14
 
 /* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT	(1 << 27) /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT	(1 << 24) /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT	(1 << 12) /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT	(1 << 11) /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT	(1 << 8) /* HOST1 power mask */
+#define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)	/* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)	/* OTG power mask */
+#define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)	/* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)	/* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1PM_BIT		(1 << 8)	/* HOST1 power mask */
 
 /* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT	(1 << 5) /* UH1 Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)	/* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT		(1 << 5)	/* UH1 Disable Overcurrent Event */
 
 /* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT	(1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT	(1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT	(1 << 4)
+#define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
 
 /* USB_CTRL_1 */
-#define MXC_USB_CTRL_UH1_EXT_CLK_EN		(1 << 25)
+#define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)
 
 /* USB pin configuration */
 #define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \

@@ -160,7 +160,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;
-	case 1:	/* Host 1 Host ULPI */
+	case 1:	/* Host 1 ULPI */
 #ifdef CONFIG_MX51
 		/* The clock for the USBH1 ULPI port will come externally
 		   from the PHY. */

@@ -171,7 +171,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
 		else
 			v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
 		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);

@@ -187,7 +187,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 	case 2: /* Host 2 ULPI */
 		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
 		else
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */

Benoît Thébaudeau

author

2012-11-05 20:10 UTC #3 lore raw

PATCH 4/13 ehci-mx5: Fix OC_DIS usage

In reply to Benoît Thébaudeau

MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like MXC_H1_OC_DIS_BIT, not the opposite.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../drivers/usb/host/ehci-mx5.c                                  |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/usb/host/ehci-mx5.c +3 -3

index 66ab25d..1248671 100644
@@ -144,11 +144,11 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			v = __raw_readl(usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-				/* OC/USBPWR is not used */
-				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-			else
 				/* OC/USBPWR is used */
 				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+			else
+				/* OC/USBPWR is not used */
+				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
 			__raw_writel(v, usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);

Benoît Thébaudeau

author

2012-11-05 20:11 UTC #4 lore raw

PATCH 5/13 ehci-mx5: Fix OPM usage

In reply to Benoît Thébaudeau

MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like MXC_H1_UCTRL_H1PM_BIT and MXC_H2_UCTRL_H2PM_BIT, not the opposite.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../drivers/usb/host/ehci-mx5.c                                    |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/usb/host/ehci-mx5.c +2 -2

index 1248671..bd1f119 100644
@@ -154,9 +154,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 
 			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-				v |= MXC_OTG_UCTRL_OPM_BIT;
-			else
 				v &= ~MXC_OTG_UCTRL_OPM_BIT;
+			else
+				v |= MXC_OTG_UCTRL_OPM_BIT;
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;

Benoît Thébaudeau

author

2012-11-05 20:11 UTC #5 lore raw

PATCH 6/13 ehci-mx5: Fix *PM usage for i.MX53

In reply to Benoît Thébaudeau

The MXC_*_UCTRL_*PM_BIT bits are available only on i.MX51.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../drivers/usb/host/ehci-mx5.c                                  |    6 ++++++
 1 file changed, 6 insertions(+)

drivers/usb/host/ehci-mx5.c +6 -0

index bd1f119..8e42e56 100644
@@ -153,10 +153,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
 
 			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 				v &= ~MXC_OTG_UCTRL_OPM_BIT;
 			else
 				v |= MXC_OTG_UCTRL_OPM_BIT;
+#endif
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;

@@ -170,10 +172,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 #endif
 
 		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
 		else
 			v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+#endif
 		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
 		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

@@ -186,10 +190,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		break;
 	case 2: /* Host 2 ULPI */
 		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+#ifdef CONFIG_MX51
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
 		else
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+#endif
 
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
 		break;

Benoît Thébaudeau

author

2012-11-05 20:11 UTC #6 lore raw

PATCH 7/13 ehci-mx5: Add missing OC_DIS for i.MX53

In reply to Benoît Thébaudeau

The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../drivers/usb/host/ehci-mx5.c                    |   25 ++++++++++++++++++++
 1 file changed, 25 insertions(+)

drivers/usb/host/ehci-mx5.c +25 -0

index 8e42e56..7da1398 100644
@@ -32,12 +32,14 @@
 #define MXC_OTG_OFFSET			0
 #define MXC_H1_OFFSET			0x200
 #define MXC_H2_OFFSET			0x400
+#define MXC_H3_OFFSET			0x600
 
 #define MXC_USBCTRL_OFFSET		0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET	0x8
 #define MXC_USB_PHY_CTR_FUNC2_OFFSET	0xc
 #define MXC_USB_CTRL_1_OFFSET		0x10
 #define MXC_USBH2CTRL_OFFSET		0x14
+#define MXC_USBH3CTRL_OFFSET		0x18
 
 /* USB_CTRL */
 #define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)	/* OTG wakeup intr enable */

@@ -51,10 +53,16 @@
 #define MXC_H1_OC_DIS_BIT		(1 << 5)	/* UH1 Disable Overcurrent Event */
 
 /* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_DIS_BIT	(1 << 30)
 #define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
 #define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
 #define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
 
+/* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_DIS_BIT	(1 << 30)
+#define MXC_H3_UCTRL_H3UIE_BIT		(1 << 8)
+#define MXC_H3_UCTRL_H3WIE_BIT		(1 << 7)
+
 /* USB_CTRL_1 */
 #define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

@@ -196,9 +204,26 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		else
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
 #endif
+#ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+			v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
+		else
+			v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+#endif
 
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
 		break;
+#ifdef CONFIG_MX53
+	case 3: /* Host 3 ULPI */
+		v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+			v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
+		else
+			v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+
+		__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
+		break;
+#endif
 	}
 
 	return ret;

Benoît Thébaudeau

author

2012-11-05 20:12 UTC #7 lore raw

PATCH 8/13 ehci-mxc: Make EHCI power/oc polarities configurable

In reply to Benoît Thébaudeau

Make EHCI power and overcurrent polarities configurable. If not set, these new configurartions keep the default register values so that existing board files do not have to be changed.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../drivers/usb/host/ehci-mx5.c                    |   51 ++++++++++++++++++++
 .../include/usb/ehci-fsl.h                         |   10 ++--
 2 files changed, 57 insertions(+), 4 deletions(-)

drivers/usb/host/ehci-mx5.c +51 -0

index 7da1398..52aeae5 100644
@@ -44,24 +44,33 @@
 /* USB_CTRL */
 #define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)	/* OTG wakeup intr enable */
 #define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)	/* OTG power mask */
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT	(1 << 24)	/* OTG power pin polarity */
 #define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)	/* Host1 ULPI interrupt enable */
 #define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)	/* HOST1 wakeup intr enable */
 #define MXC_H1_UCTRL_H1PM_BIT		(1 << 8)	/* HOST1 power mask */
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT	(1 << 8)	/* HOST1 power pin polarity */
 
 /* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_POL_BIT	(1 << 9)	/* OTG Polarity of Overcurrent */
 #define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)	/* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_POL_BIT		(1 << 6)	/* UH1 Polarity of Overcurrent */
 #define MXC_H1_OC_DIS_BIT		(1 << 5)	/* UH1 Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT	(1 << 3)	/* OTG Power Pin Polarity */
 
 /* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_POL_BIT	(1 << 31)
 #define MXC_H2_UCTRL_H2_OC_DIS_BIT	(1 << 30)
 #define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
 #define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
 #define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
+#define MXC_H2_UCTRL_H2_PWR_POL_BIT	(1 << 4)
 
 /* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_POL_BIT	(1 << 31)
 #define MXC_H3_UCTRL_H3_OC_DIS_BIT	(1 << 30)
 #define MXC_H3_UCTRL_H3UIE_BIT		(1 << 8)
 #define MXC_H3_UCTRL_H3WIE_BIT		(1 << 7)
+#define MXC_H3_UCTRL_H3_PWR_POL_BIT	(1 << 4)
 
 /* USB_CTRL_1 */
 #define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

@@ -151,12 +160,22 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		if (flags & MXC_EHCI_INTERNAL_PHY) {
 			v = __raw_readl(usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
+			if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+				v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
+			else
+				v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 				/* OC/USBPWR is used */
 				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
 			else
 				/* OC/USBPWR is not used */
 				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+#ifdef CONFIG_MX51
+			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+				v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
+			else
+				v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
+#endif
 			__raw_writel(v, usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);

@@ -167,6 +186,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			else
 				v |= MXC_OTG_UCTRL_OPM_BIT;
 #endif
+#ifdef CONFIG_MX53
+			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+				v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
+			else
+				v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
+#endif
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;

@@ -186,9 +211,19 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		else
 			v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
 #endif
+#ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
+		else
+			v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
+#endif
 		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
 		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H1_OC_POL_BIT;
+		else
+			v &= ~MXC_H1_OC_POL_BIT;
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
 		else

@@ -205,10 +240,18 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
 #endif
 #ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
+		else
+			v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
 		else
 			v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
+		else
+			v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
 #endif
 
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);

@@ -216,10 +259,18 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 #ifdef CONFIG_MX53
 	case 3: /* Host 3 ULPI */
 		v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
+		else
+			v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
 		else
 			v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
+		else
+			v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
 
 		__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
 		break;

include/usb/ehci-fsl.h +6 -4

index 4dee5b0..a1438d6 100644
@@ -266,11 +266,13 @@ struct usb_ehci {
 #define MXC_EHCI_INTERFACE_MASK		(0xf)
 
 #define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
-#define MXC_EHCI_TTL_ENABLED		(1 << 6)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH	(1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW	(1 << 7)
+#define MXC_EHCI_TTL_ENABLED		(1 << 8)
 
-#define MXC_EHCI_INTERNAL_PHY		(1 << 7)
-#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
-#define MXC_EHCI_IPPUE_UP		(1 << 9)
+#define MXC_EHCI_INTERNAL_PHY		(1 << 9)
+#define MXC_EHCI_IPPUE_DOWN		(1 << 10)
+#define MXC_EHCI_IPPUE_UP		(1 << 11)
 
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);

Benoît Thébaudeau

author

2012-11-05 20:12 UTC #8 lore raw

PATCH 9/13 ehci-mxc: Make i.MX25 EHCI configurable

In reply to Benoît Thébaudeau

Use EHCI MXC configuration options for i.MX25.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Matthias Weisser <[email protected]>

---
 .../drivers/usb/host/ehci-mxc.c                    |   71 +++++++++++++++++---
 .../include/configs/zmx25.h                        |    6 +-
 2 files changed, 66 insertions(+), 11 deletions(-)

drivers/usb/host/ehci-mxc.c +63 -8

index e21f2c5..711c4a7 100644
@@ -28,10 +28,21 @@
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
-#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
-#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
+#define MX25_OTG_SIC_SHIFT	29
+#define MX25_OTG_SIC_MASK	(0x3 << MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BIT		(1 << 24)
+#define MX25_OTG_PP_BIT		(1 << 11)
+#define MX25_OTG_OCPOL_BIT	(1 << 3)
+
+#define MX25_H1_SIC_SHIFT	21
+#define MX25_H1_SIC_MASK	(0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT		(1 << 18)
+#define MX25_H1_PM_BIT		(1 << 8)
+#define MX25_H1_IPPUE_UP_BIT	(1 << 7)
+#define MX25_H1_IPPUE_DOWN_BIT	(1 << 6)
+#define MX25_H1_TLL_BIT		(1 << 5)
+#define MX25_H1_USBTE_BIT	(1 << 4)
+#define MX25_H1_OCPOL_BIT	(1 << 2)
 
 #define MX31_OTG_SIC_SHIFT	29
 #define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)

@@ -51,12 +62,56 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
 
-#if defined(CONFIG_MX25)
-	v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
-		MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#elif defined(CONFIG_MX31)
 	v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+#if defined(CONFIG_MX25)
+	switch (port) {
+	case 0:	/* OTG port */
+		v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
+			MX25_OTG_OCPOL_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX25_OTG_PM_BIT;
+
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MX25_OTG_PP_BIT;
+
+		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+			v |= MX25_OTG_OCPOL_BIT;
+
+		break;
+	case 1: /* H1 port */
+		v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
+			MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
+			MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX25_H1_PM_BIT;
+
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MX25_H1_PP_BIT;
+
+		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+			v |= MX25_H1_OCPOL_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX25_H1_TLL_BIT;
+
+		if (flags & MXC_EHCI_INTERNAL_PHY)
+			v |= MX25_H1_USBTE_BIT;
+
+		if (flags & MXC_EHCI_IPPUE_DOWN)
+			v |= MX25_H1_IPPUE_DOWN_BIT;
 
+		if (flags & MXC_EHCI_IPPUE_UP)
+			v |= MX25_H1_IPPUE_UP_BIT;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+#elif defined(CONFIG_MX31)
 	switch (port) {
 	case 0:	/* OTG port */
 		v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);

include/configs/zmx25.h +3 -3

index 447683a..e9216d9 100644
@@ -109,9 +109,9 @@
 #define CONFIG_USB_EHCI			/* Enable EHCI USB support */
 #define CONFIG_USB_EHCI_MXC
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT	2
-#define CONFIG_MXC_USB_PORTSC	0xC0000000
-#define CONFIG_MXC_USB_FLAGS	0
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	MXC_EHCI_MODE_SERIAL
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_STORAGE
 #define CONFIG_DOS_PARTITION

Benoît Thébaudeau

author

2012-11-05 20:12 UTC #9 lore raw

PATCH 10/13 ehci-mxc: Define host offsets

In reply to Benoît Thébaudeau

Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at SoC level.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../arch/arm/include/asm/arch-mx25/imx-regs.h                        |    1 +
 .../arch/arm/include/asm/arch-mx31/imx-regs.h                        |    1 +
 .../drivers/usb/host/ehci-mxc.c                                      |    2 +-
 3 files changed, 3 insertions(+), 1 deletion(-)

arch/arm/include/asm/arch-mx25/imx-regs.h +1 -0

index e780296..c1bc4bc 100644
@@ -246,6 +246,7 @@ struct aips_regs {
 #define IMX_RTIC_BASE		(0x53FEC000)
 #define IMX_IIM_BASE		(0x53FF0000)
 #define IMX_USB_BASE		(0x53FF4000)
+#define IMX_USB_PORT_OFFSET	0x200
 #define IMX_CSI_BASE		(0x53FF8000)
 #define IMX_DRYICE_BASE		(0x53FFC000)

arch/arm/include/asm/arch-mx31/imx-regs.h +1 -0

index 01a849d..ae3658b 100644
@@ -895,6 +895,7 @@ struct esdc_regs {
 
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
 #define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_PORT_OFFSET	0x200
 
 /*
  * CSPI register definitions

drivers/usb/host/ehci-mxc.c +1 -1

index 711c4a7..cd09462 100644
@@ -168,7 +168,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 	udelay(80);
 
 	ehci = (struct usb_ehci *)(IMX_USB_BASE +
-		(0x200 * CONFIG_MXC_USB_PORT));
+			IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
 	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
 			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

Benoît Thébaudeau

author

2012-11-05 20:13 UTC #10 lore raw

PATCH 11/13 ehci-mxc: Add support for i.MX35

In reply to Benoît Thébaudeau

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../arch/arm/include/asm/arch-mx35/imx-regs.h      |    2 +
 .../drivers/usb/host/ehci-mxc.c                    |   68 ++++++++++++++++++++
 2 files changed, 70 insertions(+)

arch/arm/include/asm/arch-mx35/imx-regs.h +2 -0

index 7b09809..cd7716f 100644
@@ -82,6 +82,8 @@
 #define PWM_BASE_ADDR		0x53FE0000
 #define RTIC_BASE_ADDR		0x53FEC000
 #define IIM_BASE_ADDR		0x53FF0000
+#define IMX_USB_BASE		0x53FF4000
+#define IMX_USB_PORT_OFFSET	0x400
 
 #define IMX_CCM_BASE		CCM_BASE_ADDR

drivers/usb/host/ehci-mxc.c +68 -0

86 lines not on this page · raw message

Benoît Thébaudeau

author

2012-11-05 20:13 UTC #11 lore raw

PATCH 12/13 mx35pdk: Add support for OTG

In reply to Benoît Thébaudeau

Add support for the OTG port on the mx35pdk Personality board.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Marek Vasut <[email protected]>

---
Note: I have tested this on a similar board, but not on the mx35pdk itself. So please, someone test on mx35pdk. Stefano?

 .../board/freescale/mx35pdk/lowlevel_init.S         |    4 ++++
 .../board/freescale/mx35pdk/mx35pdk.c               |   19 +++++++++++++++++++
 .../include/configs/mx35pdk.h                       |   14 ++++++++++++++
 3 files changed, 37 insertions(+)

board/freescale/mx35pdk/lowlevel_init.S +4 -0

index 698c4cf..6f4d4e0 100644
@@ -178,6 +178,10 @@
 	orr r1, r1, #0x00000C00
 	orr r1, r1, #0x00000003
 	str r1, [r0, #CLKCTL_CGR1]
+
+	ldr r1, [r0, #CLKCTL_CGR2]
+	orr r1, r1, #0x00C00000
+	str r1, [r0, #CLKCTL_CGR2]
 .endm
 
 .macro setup_sdram

board/freescale/mx35pdk/mx35pdk.c +19 -0

index 7cb6b30..e9ef4d1 100644
@@ -97,6 +97,24 @@ static void setup_iomux_spi(void)
 	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
 }
 
+static void setup_iomux_usbotg(void)
+{
+	int in_pad, out_pad;
+
+	/* Set up pins for USBOTG. */
+	mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+	in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+		PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+	out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+		PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+	mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+	mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
 static void setup_iomux_fec(void)
 {
 	int pad;

@@ -188,6 +206,7 @@ int board_early_init_f(void)
 	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 
 	setup_iomux_i2c();
+	setup_iomux_usbotg();
 	setup_iomux_fec();
 	setup_iomux_spi();

include/configs/mx35pdk.h +14 -0

index 826c912..69b7d23 100644
@@ -110,6 +110,8 @@
 #define CONFIG_NET_RETRY_COUNT	100
 #define CONFIG_CMD_DATE
 
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
 #define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION

@@ -242,6 +244,18 @@
 #define CONFIG_MXC_NAND_HWECC
 #define CONFIG_SYS_NAND_LARGEPAGE
 
+/* EHCI driver */
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT	0
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERFACE_DIFF_UNI | \
+				 MXC_EHCI_POWER_PINS_ENABLED | \
+				 MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
 /* mmc driver */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC

Stefano Babic

2012-11-07 14:30 UTC #12 lore raw

PATCH 12/13 mx35pdk: Add support for OTG

Quoted 8 lines · Beno?t Th?baudeau

Add support for the OTG port on the mx35pdk Personality board.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Marek Vasut <[email protected]>
---
Note: I have tested this on a similar board, but not on the mx35pdk itself. So please, someone test on mx35pdk. Stefano?

Yes, I will do it.

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2012-11-07 16:16 UTC #13 lore raw

PATCH 12/13 mx35pdk: Add support for OTG

In reply to Benoît Thébaudeau

Quoted 9 lines · Beno?t Th?baudeau

Add support for the OTG port on the mx35pdk Personality board.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Marek Vasut <[email protected]>
---
Note: I have tested this on a similar board, but not on the mx35pdk itself. So please, someone test on mx35pdk. Stefano?

It works on mx35pdk, too ;-)

Tested-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Benoît Thébaudeau

author

2012-11-07 16:27 UTC #14 lore raw

PATCH 12/13 mx35pdk: Add support for OTG

Hi Stefano,

Quoted 12 lines · Stefano Babic

Quoted 10 lines · Beno?t Th?baudeau
Add support for the OTG port on the mx35pdk Personality board.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Marek Vasut <[email protected]>
---
Note: I have tested this on a similar board, but not on the mx35pdk itself. So
please, someone test on mx35pdk. Stefano?

Quoted 3 lines

It works on mx35pdk, too ;-)
Tested-by Stefano Babic <[email protected]>

Great! Thanks for testing.

Are you also OK with the other patches in this series? Can I send a v2 with just the change that Marek asked for 13/13?

Best regards,
Beno?t

Stefano Babic

2012-11-07 16:33 UTC #15 lore raw

PATCH 12/13 mx35pdk: Add support for OTG

Quoted 15 lines · Beno?t Th?baudeau

Hi Stefano,
Quoted 12 lines · Stefano Babic
Quoted 10 lines · Beno?t Th?baudeau
Add support for the OTG port on the mx35pdk Personality board.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Marek Vasut <[email protected]>
---
Note: I have tested this on a similar board, but not on the mx35pdk itself. So
please, someone test on mx35pdk. Stefano?

Quoted 8 lines

Quoted 3 lines
It works on mx35pdk, too ;-)
Tested-by Stefano Babic <[email protected]>
Great! Thanks for testing.
Are you also OK with the other patches in this series? Can I send a v2 with just the change that Marek asked for 13/13?

IMHO they are ok, I have not found relevant issues.

Best regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Benoît Thébaudeau

author

2012-11-05 20:13 UTC #16 lore raw

PATCH 13/13 ehci-mx5: Make board_ehci_hcd_init() optional

In reply to Benoît Thébaudeau

A custom board_ehci_hcd_init() may be unneeded, so add a weak default implementation doing nothing.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../drivers/usb/host/ehci-mx5.c                                |    8 ++++++++
 1 file changed, 8 insertions(+)

drivers/usb/host/ehci-mx5.c +8 -0

index 52aeae5..e3818be 100644
@@ -280,6 +280,14 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 	return ret;
 }
 
+int __board_ehci_hcd_init(int port)
+{
+	return 0;
+}
+
+int board_ehci_hcd_init(int port)
+	__attribute((weak, alias("__board_ehci_hcd_init")));
+
 void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
 {
 }

Benoît Thébaudeau

author

2012-11-05 23:34 UTC #18 lore raw

PATCH 13/13 ehci-mx5: Make board_ehci_hcd_init() optional

Dear Marek Vasut,

Quoted 25 lines · Marek Vasut

Dear Beno?t Th?baudeau,
Quoted 23 lines
A custom board_ehci_hcd_init() may be unneeded, so add a weak default
implementation doing nothing.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>
---
.../drivers/usb/host/ehci-mx5.c |
    8
++++++++ 1 file changed, 8 insertions(+)
(quoted diff) +0 -0
u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c index 52aeae5..e3818be
100644
drivers/usb/host/ehci-mx5.c +0 -0
@@ -280,6 +280,14 @@ int mxc_set_usbcontrol(int port, unsigned int
 flags)
 	return ret;
 }
 

Quoted 10 lines

drivers/usb/host/ehci-mx5.c int mxc_set_usbcontrol(int port, unsigned int flags) · line 290
Quoted 8 lines
drivers/usb/host/ehci-mx5.c +8 -0
+int __board_ehci_hcd_init(int port)
+{
+	return 0;
+}
+
+int board_ehci_hcd_init(int port)
+	__attribute((weak, alias("__board_ehci_hcd_init")));
+
Include linux/compiler.h and use simple __weak

Will do.

Best regards,
Beno?t

Marek Vasut

2012-11-05 22:55 UTC #19 lore raw

PATCH 1/13 mx31: Move EHCI definitions to ehci-fsl.h

In reply to Benoît Thébaudeau

Dear Beno?t Th?baudeau,

Quoted 6 lines

The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>

[...]

I'll delegate review of this patchset to Stefano .. .Stefano, is it ok with you?

Best regards,
Marek Vasut

Stefano Babic

2012-11-07 16:31 UTC #20 lore raw

PATCH 1/13 mx31: Move EHCI definitions to ehci-fsl.h

Quoted 11 lines · Marek Vasut

Dear Beno?t Th?baudeau,
Quoted 6 lines
The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>
[...]
I'll delegate review of this patchset to Stefano .. .Stefano, is it ok with you?

Of course, it is.

Best regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Benoît Thébaudeau

author

2012-11-08 20:27 UTC #21 lore raw

PATCH v2 1/13 mx31: Move EHCI definitions to ehci-fsl.h

In reply to Benoît Thébaudeau

The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.

 .../arch/arm/include/asm/arch-mx31/imx-regs.h      |   26 --------------------
 .../include/usb/ehci-fsl.h                         |   22 +++++++++++++++++
 2 files changed, 22 insertions(+), 26 deletions(-)

arch/arm/include/asm/arch-mx31/imx-regs.h +0 ~~-26~~

index 8fd3d08..01a849d 100644
@@ -896,32 +896,6 @@ struct esdc_regs {
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
 #define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
 
-/* USB portsc */
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
-#define MXC_EHCI_FORCE_FS		(1 << 24)
-#define MXC_EHCI_UTMI_8BIT		(0 << 28)
-#define MXC_EHCI_UTMI_16BIT		(1 << 28)
-#define MXC_EHCI_SERIAL			(1 << 29)
-#define MXC_EHCI_MODE_UTMI		(0 << 30)
-#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
-#define MXC_EHCI_MODE_ULPI		(2 << 30)
-#define MXC_EHCI_MODE_SERIAL		(3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
-#define MXC_EHCI_INTERFACE_MASK		(0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
-#define MXC_EHCI_TTL_ENABLED		(1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY		(1 << 7)
-#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
-#define MXC_EHCI_IPPUE_UP		(1 << 9)
-
 /*
  * CSPI register definitions
  */

include/usb/ehci-fsl.h +22 -0

index 2869302..4dee5b0 100644
@@ -246,9 +246,31 @@ struct usb_ehci {
 /*
  * For MXC SOCs
  */
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
+#define MXC_EHCI_FORCE_FS		(1 << 24)
+#define MXC_EHCI_UTMI_8BIT		(0 << 28)
+#define MXC_EHCI_UTMI_16BIT		(1 << 28)
+#define MXC_EHCI_SERIAL			(1 << 29)
+#define MXC_EHCI_MODE_UTMI		(0 << 30)
+#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
+#define MXC_EHCI_MODE_ULPI		(2 << 30)
+#define MXC_EHCI_MODE_SERIAL		(3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
+#define MXC_EHCI_INTERFACE_MASK		(0xf)
+
 #define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
 #define MXC_EHCI_TTL_ENABLED		(1 << 6)
+
 #define MXC_EHCI_INTERNAL_PHY		(1 << 7)
+#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
+#define MXC_EHCI_IPPUE_UP		(1 << 9)
 
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);

Benoît Thébaudeau

author

2012-11-08 20:28 UTC #22 lore raw

PATCH v2 2/13 ehci-mxc: Clean up

Clean up ehci-mxc:
- Remove useless #if's.
- Fix identation.
- Issue a #error if used with an unsupported platform.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.

 .../drivers/usb/host/ehci-mxc.c                    |   86 +++++++++-----------
 1 file changed, 40 insertions(+), 46 deletions(-)

drivers/usb/host/ehci-mxc.c +40 ~~-46~~

index a38bc9c..e21f2c5 100644
@@ -28,14 +28,11 @@
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
-#ifdef CONFIG_MX25
 #define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
 #define MX25_USB_CTRL_HSTD_BIT		(1<<5)
 #define MX25_USB_CTRL_USBTE_BIT		(1<<4)
 #define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
-#endif
 
-#ifdef CONFIG_MX31
 #define MX31_OTG_SIC_SHIFT	29
 #define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
 #define MX31_OTG_PM_BIT		(1 << 24)

@@ -49,59 +46,56 @@
 #define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
 #define MX31_H1_PM_BIT		(1 << 8)
 #define MX31_H1_DT_BIT		(1 << 4)
-#endif
 
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
 
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25)
 	v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
 		MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#endif
+#elif defined(CONFIG_MX31)
+	v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
 
-#ifdef CONFIG_MX31
-		v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-
-		switch (port) {
-		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
-
-			break;
-		case 1: /* H1 port */
-			v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
-				MX31_H1_DT_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-						<< MX31_H1_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_H1_PM_BIT;
-
-			if (!(flags & MXC_EHCI_TTL_ENABLED))
-				v |= MX31_H1_DT_BIT;
-
-			break;
-		case 2:	/* H2 port */
-			v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
-				MX31_H2_DT_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-						<< MX31_H2_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_H2_PM_BIT;
-
-			if (!(flags & MXC_EHCI_TTL_ENABLED))
-				v |= MX31_H2_DT_BIT;
-
-			break;
-		default:
-			return -EINVAL;
-		}
-#endif
+	switch (port) {
+	case 0:	/* OTG port */
+		v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_OTG_PM_BIT;
+
+		break;
+	case 1: /* H1 port */
+		v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
 
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_H1_PM_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX31_H1_DT_BIT;
+
+		break;
+	case 2:	/* H2 port */
+		v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_H2_PM_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX31_H2_DT_BIT;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+#else
+#error MXC EHCI USB driver not supported on this platform
+#endif
 	writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+
 	return 0;
 }

Benoît Thébaudeau

author

2012-11-08 20:28 UTC #23 lore raw

PATCH v2 3/13 ehci-mx5: Clean up

In reply to Benoît Thébaudeau

Clean up ehci-mx5:
- Fix column alignments.
- Fix comments.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.

 .../drivers/usb/host/ehci-mx5.c                    |   34 ++++++++++----------
 1 file changed, 17 insertions(+), 17 deletions(-)

drivers/usb/host/ehci-mx5.c +17 ~~-17~~

index 9a2c295..66ab25d 100644
@@ -29,9 +29,9 @@
 #define MX5_USBOTHER_REGS_OFFSET 0x800
 
 
-#define MXC_OTG_OFFSET		0
-#define MXC_H1_OFFSET		0x200
-#define MXC_H2_OFFSET		0x400
+#define MXC_OTG_OFFSET			0
+#define MXC_H1_OFFSET			0x200
+#define MXC_H2_OFFSET			0x400
 
 #define MXC_USBCTRL_OFFSET		0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET	0x8

@@ -40,23 +40,23 @@
 #define MXC_USBH2CTRL_OFFSET		0x14
 
 /* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT	(1 << 27) /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT	(1 << 24) /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT	(1 << 12) /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT	(1 << 11) /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT	(1 << 8) /* HOST1 power mask */
+#define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)	/* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)	/* OTG power mask */
+#define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)	/* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)	/* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1PM_BIT		(1 << 8)	/* HOST1 power mask */
 
 /* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT	(1 << 5) /* UH1 Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)	/* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT		(1 << 5)	/* UH1 Disable Overcurrent Event */
 
 /* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT	(1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT	(1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT	(1 << 4)
+#define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
 
 /* USB_CTRL_1 */
-#define MXC_USB_CTRL_UH1_EXT_CLK_EN		(1 << 25)
+#define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)
 
 /* USB pin configuration */
 #define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \

@@ -160,7 +160,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;
-	case 1:	/* Host 1 Host ULPI */
+	case 1:	/* Host 1 ULPI */
 #ifdef CONFIG_MX51
 		/* The clock for the USBH1 ULPI port will come externally
 		   from the PHY. */

@@ -171,7 +171,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
 		else
 			v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
 		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);

@@ -187,7 +187,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 	case 2: /* Host 2 ULPI */
 		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
 		else
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */

Benoît Thébaudeau

author

2012-11-08 20:28 UTC #24 lore raw

PATCH v2 4/13 ehci-mx5: Fix OC_DIS usage

In reply to Benoît Thébaudeau

MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like MXC_H1_OC_DIS_BIT, not the opposite.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.

 .../drivers/usb/host/ehci-mx5.c                                  |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/usb/host/ehci-mx5.c +3 -3

index 66ab25d..1248671 100644
@@ -144,11 +144,11 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			v = __raw_readl(usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-				/* OC/USBPWR is not used */
-				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-			else
 				/* OC/USBPWR is used */
 				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+			else
+				/* OC/USBPWR is not used */
+				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
 			__raw_writel(v, usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);

Benoît Thébaudeau

author

2012-11-08 20:29 UTC #25 lore raw

PATCH v2 5/13 ehci-mx5: Fix OPM usage

In reply to Benoît Thébaudeau

MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like MXC_H1_UCTRL_H1PM_BIT and MXC_H2_UCTRL_H2PM_BIT, not the opposite.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.

 .../drivers/usb/host/ehci-mx5.c                                    |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/usb/host/ehci-mx5.c +2 -2

index 1248671..bd1f119 100644
@@ -154,9 +154,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 
 			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-				v |= MXC_OTG_UCTRL_OPM_BIT;
-			else
 				v &= ~MXC_OTG_UCTRL_OPM_BIT;
+			else
+				v |= MXC_OTG_UCTRL_OPM_BIT;
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;

Benoît Thébaudeau

author

2012-11-08 20:29 UTC #26 lore raw

PATCH v2 6/13 ehci-mx5: Fix *PM usage for i.MX53

In reply to Benoît Thébaudeau

The MXC_*_UCTRL_*PM_BIT bits are available only on i.MX51.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.

 .../drivers/usb/host/ehci-mx5.c                                  |    6 ++++++
 1 file changed, 6 insertions(+)

drivers/usb/host/ehci-mx5.c +6 -0

index bd1f119..8e42e56 100644
@@ -153,10 +153,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
 
 			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 				v &= ~MXC_OTG_UCTRL_OPM_BIT;
 			else
 				v |= MXC_OTG_UCTRL_OPM_BIT;
+#endif
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;

@@ -170,10 +172,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 #endif
 
 		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
 		else
 			v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+#endif
 		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
 		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

@@ -186,10 +190,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		break;
 	case 2: /* Host 2 ULPI */
 		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+#ifdef CONFIG_MX51
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
 		else
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+#endif
 
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
 		break;

Benoît Thébaudeau

author

2012-11-08 20:29 UTC #27 lore raw

PATCH v2 7/13 ehci-mx5: Add missing OC_DIS for i.MX53

In reply to Benoît Thébaudeau

The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.

 .../drivers/usb/host/ehci-mx5.c                    |   25 ++++++++++++++++++++
 1 file changed, 25 insertions(+)

drivers/usb/host/ehci-mx5.c +25 -0

index 8e42e56..7da1398 100644
@@ -32,12 +32,14 @@
 #define MXC_OTG_OFFSET			0
 #define MXC_H1_OFFSET			0x200
 #define MXC_H2_OFFSET			0x400
+#define MXC_H3_OFFSET			0x600
 
 #define MXC_USBCTRL_OFFSET		0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET	0x8
 #define MXC_USB_PHY_CTR_FUNC2_OFFSET	0xc
 #define MXC_USB_CTRL_1_OFFSET		0x10
 #define MXC_USBH2CTRL_OFFSET		0x14
+#define MXC_USBH3CTRL_OFFSET		0x18
 
 /* USB_CTRL */
 #define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)	/* OTG wakeup intr enable */

@@ -51,10 +53,16 @@
 #define MXC_H1_OC_DIS_BIT		(1 << 5)	/* UH1 Disable Overcurrent Event */
 
 /* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_DIS_BIT	(1 << 30)
 #define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
 #define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
 #define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
 
+/* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_DIS_BIT	(1 << 30)
+#define MXC_H3_UCTRL_H3UIE_BIT		(1 << 8)
+#define MXC_H3_UCTRL_H3WIE_BIT		(1 << 7)
+
 /* USB_CTRL_1 */
 #define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

@@ -196,9 +204,26 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		else
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
 #endif
+#ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+			v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
+		else
+			v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+#endif
 
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
 		break;
+#ifdef CONFIG_MX53
+	case 3: /* Host 3 ULPI */
+		v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+			v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
+		else
+			v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+
+		__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
+		break;
+#endif
 	}
 
 	return ret;

Benoît Thébaudeau

author

2012-11-08 20:29 UTC #28 lore raw

PATCH v2 8/13 ehci-mxc: Make EHCI power/oc polarities configurable

In reply to Benoît Thébaudeau

Make EHCI power and overcurrent polarities configurable. If not set, these new configurartions keep the default register values so that existing board files do not have to be changed.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.

 .../drivers/usb/host/ehci-mx5.c                    |   51 ++++++++++++++++++++
 .../include/usb/ehci-fsl.h                         |   10 ++--
 2 files changed, 57 insertions(+), 4 deletions(-)

drivers/usb/host/ehci-mx5.c +51 -0

index 7da1398..52aeae5 100644
@@ -44,24 +44,33 @@
 /* USB_CTRL */
 #define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)	/* OTG wakeup intr enable */
 #define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)	/* OTG power mask */
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT	(1 << 24)	/* OTG power pin polarity */
 #define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)	/* Host1 ULPI interrupt enable */
 #define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)	/* HOST1 wakeup intr enable */
 #define MXC_H1_UCTRL_H1PM_BIT		(1 << 8)	/* HOST1 power mask */
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT	(1 << 8)	/* HOST1 power pin polarity */
 
 /* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_POL_BIT	(1 << 9)	/* OTG Polarity of Overcurrent */
 #define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)	/* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_POL_BIT		(1 << 6)	/* UH1 Polarity of Overcurrent */
 #define MXC_H1_OC_DIS_BIT		(1 << 5)	/* UH1 Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT	(1 << 3)	/* OTG Power Pin Polarity */
 
 /* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_POL_BIT	(1 << 31)
 #define MXC_H2_UCTRL_H2_OC_DIS_BIT	(1 << 30)
 #define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
 #define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
 #define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
+#define MXC_H2_UCTRL_H2_PWR_POL_BIT	(1 << 4)
 
 /* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_POL_BIT	(1 << 31)
 #define MXC_H3_UCTRL_H3_OC_DIS_BIT	(1 << 30)
 #define MXC_H3_UCTRL_H3UIE_BIT		(1 << 8)
 #define MXC_H3_UCTRL_H3WIE_BIT		(1 << 7)
+#define MXC_H3_UCTRL_H3_PWR_POL_BIT	(1 << 4)
 
 /* USB_CTRL_1 */
 #define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

@@ -151,12 +160,22 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		if (flags & MXC_EHCI_INTERNAL_PHY) {
 			v = __raw_readl(usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
+			if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+				v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
+			else
+				v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 				/* OC/USBPWR is used */
 				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
 			else
 				/* OC/USBPWR is not used */
 				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+#ifdef CONFIG_MX51
+			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+				v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
+			else
+				v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
+#endif
 			__raw_writel(v, usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);

@@ -167,6 +186,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			else
 				v |= MXC_OTG_UCTRL_OPM_BIT;
 #endif
+#ifdef CONFIG_MX53
+			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+				v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
+			else
+				v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
+#endif
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;

@@ -186,9 +211,19 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		else
 			v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
 #endif
+#ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
+		else
+			v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
+#endif
 		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
 		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H1_OC_POL_BIT;
+		else
+			v &= ~MXC_H1_OC_POL_BIT;
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
 		else

@@ -205,10 +240,18 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
 #endif
 #ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
+		else
+			v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
 		else
 			v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
+		else
+			v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
 #endif
 
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);

@@ -216,10 +259,18 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 #ifdef CONFIG_MX53
 	case 3: /* Host 3 ULPI */
 		v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
+		else
+			v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
 		else
 			v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
+		else
+			v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
 
 		__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
 		break;

include/usb/ehci-fsl.h +6 -4

index 4dee5b0..a1438d6 100644
@@ -266,11 +266,13 @@ struct usb_ehci {
 #define MXC_EHCI_INTERFACE_MASK		(0xf)
 
 #define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
-#define MXC_EHCI_TTL_ENABLED		(1 << 6)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH	(1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW	(1 << 7)
+#define MXC_EHCI_TTL_ENABLED		(1 << 8)
 
-#define MXC_EHCI_INTERNAL_PHY		(1 << 7)
-#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
-#define MXC_EHCI_IPPUE_UP		(1 << 9)
+#define MXC_EHCI_INTERNAL_PHY		(1 << 9)
+#define MXC_EHCI_IPPUE_DOWN		(1 << 10)
+#define MXC_EHCI_IPPUE_UP		(1 << 11)
 
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);

Benoît Thébaudeau

author

2012-11-08 20:30 UTC #29 lore raw

PATCH v2 9/13 ehci-mxc: Make i.MX25 EHCI configurable

In reply to Benoît Thébaudeau

Use EHCI MXC configuration options for i.MX25.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Matthias Weisser <[email protected]>

---
Changes for v2: None.

 .../drivers/usb/host/ehci-mxc.c                    |   71 +++++++++++++++++---
 .../include/configs/zmx25.h                        |    6 +-
 2 files changed, 66 insertions(+), 11 deletions(-)

drivers/usb/host/ehci-mxc.c +63 -8

index e21f2c5..711c4a7 100644
@@ -28,10 +28,21 @@
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
-#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
-#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
+#define MX25_OTG_SIC_SHIFT	29
+#define MX25_OTG_SIC_MASK	(0x3 << MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BIT		(1 << 24)
+#define MX25_OTG_PP_BIT		(1 << 11)
+#define MX25_OTG_OCPOL_BIT	(1 << 3)
+
+#define MX25_H1_SIC_SHIFT	21
+#define MX25_H1_SIC_MASK	(0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT		(1 << 18)
+#define MX25_H1_PM_BIT		(1 << 8)
+#define MX25_H1_IPPUE_UP_BIT	(1 << 7)
+#define MX25_H1_IPPUE_DOWN_BIT	(1 << 6)
+#define MX25_H1_TLL_BIT		(1 << 5)
+#define MX25_H1_USBTE_BIT	(1 << 4)
+#define MX25_H1_OCPOL_BIT	(1 << 2)
 
 #define MX31_OTG_SIC_SHIFT	29
 #define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)

@@ -51,12 +62,56 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
 
-#if defined(CONFIG_MX25)
-	v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
-		MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#elif defined(CONFIG_MX31)
 	v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+#if defined(CONFIG_MX25)
+	switch (port) {
+	case 0:	/* OTG port */
+		v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
+			MX25_OTG_OCPOL_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX25_OTG_PM_BIT;
+
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MX25_OTG_PP_BIT;
+
+		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+			v |= MX25_OTG_OCPOL_BIT;
+
+		break;
+	case 1: /* H1 port */
+		v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
+			MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
+			MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX25_H1_PM_BIT;
+
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MX25_H1_PP_BIT;
+
+		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+			v |= MX25_H1_OCPOL_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX25_H1_TLL_BIT;
+
+		if (flags & MXC_EHCI_INTERNAL_PHY)
+			v |= MX25_H1_USBTE_BIT;
+
+		if (flags & MXC_EHCI_IPPUE_DOWN)
+			v |= MX25_H1_IPPUE_DOWN_BIT;
 
+		if (flags & MXC_EHCI_IPPUE_UP)
+			v |= MX25_H1_IPPUE_UP_BIT;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+#elif defined(CONFIG_MX31)
 	switch (port) {
 	case 0:	/* OTG port */
 		v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);

include/configs/zmx25.h +3 -3

index 447683a..e9216d9 100644
@@ -109,9 +109,9 @@
 #define CONFIG_USB_EHCI			/* Enable EHCI USB support */
 #define CONFIG_USB_EHCI_MXC
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT	2
-#define CONFIG_MXC_USB_PORTSC	0xC0000000
-#define CONFIG_MXC_USB_FLAGS	0
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	MXC_EHCI_MODE_SERIAL
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_STORAGE
 #define CONFIG_DOS_PARTITION

Benoît Thébaudeau

author

2012-11-08 20:30 UTC #30 lore raw

PATCH v2 10/13 ehci-mxc: Define host offsets

In reply to Benoît Thébaudeau

Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at SoC level.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.

 .../arch/arm/include/asm/arch-mx25/imx-regs.h                        |    1 +
 .../arch/arm/include/asm/arch-mx31/imx-regs.h                        |    1 +
 .../drivers/usb/host/ehci-mxc.c                                      |    2 +-
 3 files changed, 3 insertions(+), 1 deletion(-)

arch/arm/include/asm/arch-mx25/imx-regs.h +1 -0

index e780296..c1bc4bc 100644
@@ -246,6 +246,7 @@ struct aips_regs {
 #define IMX_RTIC_BASE		(0x53FEC000)
 #define IMX_IIM_BASE		(0x53FF0000)
 #define IMX_USB_BASE		(0x53FF4000)
+#define IMX_USB_PORT_OFFSET	0x200
 #define IMX_CSI_BASE		(0x53FF8000)
 #define IMX_DRYICE_BASE		(0x53FFC000)

arch/arm/include/asm/arch-mx31/imx-regs.h +1 -0

index 01a849d..ae3658b 100644
@@ -895,6 +895,7 @@ struct esdc_regs {
 
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
 #define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_PORT_OFFSET	0x200
 
 /*
  * CSPI register definitions

drivers/usb/host/ehci-mxc.c +1 -1

index 711c4a7..cd09462 100644
@@ -168,7 +168,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 	udelay(80);
 
 	ehci = (struct usb_ehci *)(IMX_USB_BASE +
-		(0x200 * CONFIG_MXC_USB_PORT));
+			IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
 	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
 			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

Benoît Thébaudeau

author

2012-11-08 20:30 UTC #31 lore raw

PATCH v2 11/13 ehci-mxc: Add support for i.MX35

In reply to Benoît Thébaudeau

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.

 .../arch/arm/include/asm/arch-mx35/imx-regs.h      |    2 +
 .../drivers/usb/host/ehci-mxc.c                    |   68 ++++++++++++++++++++
 2 files changed, 70 insertions(+)

arch/arm/include/asm/arch-mx35/imx-regs.h +2 -0

index 7b09809..cd7716f 100644
@@ -82,6 +82,8 @@
 #define PWM_BASE_ADDR		0x53FE0000
 #define RTIC_BASE_ADDR		0x53FEC000
 #define IIM_BASE_ADDR		0x53FF0000
+#define IMX_USB_BASE		0x53FF4000
+#define IMX_USB_PORT_OFFSET	0x400
 
 #define IMX_CCM_BASE		CCM_BASE_ADDR

drivers/usb/host/ehci-mxc.c +68 -0

86 lines not on this page · raw message

Benoît Thébaudeau

author

2012-11-08 20:31 UTC #32 lore raw

PATCH v2 12/13 mx35pdk: Add support for OTG

In reply to Benoît Thébaudeau

Add support for the OTG port on the mx35pdk Personality board.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Tested-by Stefano Babic <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Marek Vasut <[email protected]>

---
Changes for v2:
- Tested by Stefano.

 .../board/freescale/mx35pdk/lowlevel_init.S         |    4 ++++
 .../board/freescale/mx35pdk/mx35pdk.c               |   19 +++++++++++++++++++
 .../include/configs/mx35pdk.h                       |   14 ++++++++++++++
 3 files changed, 37 insertions(+)

board/freescale/mx35pdk/lowlevel_init.S +4 -0

index 698c4cf..6f4d4e0 100644
@@ -178,6 +178,10 @@
 	orr r1, r1, #0x00000C00
 	orr r1, r1, #0x00000003
 	str r1, [r0, #CLKCTL_CGR1]
+
+	ldr r1, [r0, #CLKCTL_CGR2]
+	orr r1, r1, #0x00C00000
+	str r1, [r0, #CLKCTL_CGR2]
 .endm
 
 .macro setup_sdram

board/freescale/mx35pdk/mx35pdk.c +19 -0

index 7cb6b30..e9ef4d1 100644
@@ -97,6 +97,24 @@ static void setup_iomux_spi(void)
 	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
 }
 
+static void setup_iomux_usbotg(void)
+{
+	int in_pad, out_pad;
+
+	/* Set up pins for USBOTG. */
+	mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+	in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+		PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+	out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+		PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+	mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+	mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
 static void setup_iomux_fec(void)
 {
 	int pad;

@@ -188,6 +206,7 @@ int board_early_init_f(void)
 	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 
 	setup_iomux_i2c();
+	setup_iomux_usbotg();
 	setup_iomux_fec();
 	setup_iomux_spi();

include/configs/mx35pdk.h +14 -0

index 826c912..69b7d23 100644
@@ -110,6 +110,8 @@
 #define CONFIG_NET_RETRY_COUNT	100
 #define CONFIG_CMD_DATE
 
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
 #define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION

@@ -242,6 +244,18 @@
 #define CONFIG_MXC_NAND_HWECC
 #define CONFIG_SYS_NAND_LARGEPAGE
 
+/* EHCI driver */
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT	0
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERFACE_DIFF_UNI | \
+				 MXC_EHCI_POWER_PINS_ENABLED | \
+				 MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
 /* mmc driver */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC

Benoît Thébaudeau

author

2012-11-08 20:31 UTC #33 lore raw

PATCH v2 13/13 ehci-mx5/6: Make board_ehci_hcd_init() optional

In reply to Benoît Thébaudeau

A custom board_ehci_hcd_init() may be unneeded, so add a weak default implementation doing nothing.

By the way, use simple __weak from linux/compiler.h for board_ehci_hcd_postinit() instead of weak alias with full attribute.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Use simple __weak from linux/compiler.h instead of __attribute__.
- Also use __weak instead of __attribute__ for board_ehci_hcd_postinit().
- Extend to ehci-mx6.c.

 .../drivers/usb/host/ehci-mx5.c                                |    8 +++++---
 .../drivers/usb/host/ehci-mx6.c                                |    5 +++++
 2 files changed, 10 insertions(+), 3 deletions(-)

drivers/usb/host/ehci-mx5.c +5 -3

index 52aeae5..be43d90 100644
@@ -280,12 +280,14 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 	return ret;
 }
 
-void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+int __weak board_ehci_hcd_init(int port)
 {
+	return 0;
 }
 
-void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
-	__attribute((weak, alias("__board_ehci_hcd_postinit")));
+void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+{
+}
 
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {

drivers/usb/host/ehci-mx6.c +5 -0

index 9ce25da..1b20e41 100644
@@ -159,6 +159,11 @@ static void usbh1_oc_config(void)
 	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
 }
 
+int __weak board_ehci_hcd_init(int port)
+{
+	return 0;
+}
+
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	struct usb_ehci *ehci;

Stefano Babic

2012-11-10 07:42 UTC #34 lore raw

PATCH v2 1/13 mx31: Move EHCI definitions to ehci-fsl.h

In reply to Benoît Thébaudeau

Quoted 7 lines · Beno?t Th?baudeau

The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>
---

Hi Beno?t,

Quoted 6 lines

Changes for v2: None.

 .../arch/arm/include/asm/arch-mx31/imx-regs.h      |   26 --------------------
 .../include/usb/ehci-fsl.h                         |   22 +++++++++++++++++
 2 files changed, 22 insertions(+), 26 deletions(-)

By applying this patchset I see several minor issues reported by checkpatch:

WARNING: line over 80 characters
#303: FILE: drivers/usb/host/ehci-mx5.c:43:
+#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */

WARNING: line over 80 characters
#305: FILE: drivers/usb/host/ehci-mx5.c:45:
+#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */

WARNING: line over 80 characters
#306: FILE: drivers/usb/host/ehci-mx5.c:46:
+#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */

WARNING: line over 80 characters
#312: FILE: drivers/usb/host/ehci-mx5.c:50:
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent
Event */

WARNING: line over 80 characters
#313: FILE: drivers/usb/host/ehci-mx5.c:51:
+#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */

WARNING: line over 80 characters
#343: FILE: drivers/usb/host/ehci-mx5.c:174:
+ v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */

WARNING: line over 80 characters
#352: FILE: drivers/usb/host/ehci-mx5.c:190:
+ v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */

WARNING: line over 80 characters
#641: FILE: drivers/usb/host/ehci-mx5.c:47:
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin polarity */

WARNING: line over 80 characters
#645: FILE: drivers/usb/host/ehci-mx5.c:51:
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin polarity */

WARNING: line over 80 characters
#648: FILE: drivers/usb/host/ehci-mx5.c:54:
+#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of
Overcurrent */

WARNING: line over 80 characters
#650: FILE: drivers/usb/host/ehci-mx5.c:56:
+#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */

WARNING: line over 80 characters
#652: FILE: drivers/usb/host/ehci-mx5.c:58:
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */

WARNING: line over 80 characters
#873: FILE: drivers/usb/host/ehci-mxc.c:85:
+ MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |

WARNING: line over 80 characters
#1078: FILE: drivers/usb/host/ehci-mxc.c:184:
+ MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |

WARNING: line over 80 characters
#1179: FILE: board/freescale/mx35pdk/mx35pdk.c:105:
+ mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION | MUX_CONFIG_FUNC);

WARNING: line over 80 characters
#1180: FILE: board/freescale/mx35pdk/mx35pdk.c:106:
+ mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION | MUX_CONFIG_FUNC);

total: 0 errors, 16 warnings, 810 lines checked

Can you fix them ? Thanks !

Best regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: [email protected]
=====================================================================

Benoît Thébaudeau

author

2012-11-10 12:37 UTC #35 lore raw

PATCH v2 1/13 mx31: Move EHCI definitions to ehci-fsl.h

Hi Stefano,

Quoted 101 lines · Stefano Babic

Quoted 8 lines · Beno?t Th?baudeau
The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to
ehci-fsl.h so that all MXC SoCs can use them.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>
---
Hi Beno?t,
Quoted 8 lines
Changes for v2: None.
 .../arch/arm/include/asm/arch-mx31/imx-regs.h      |   26
 --------------------
 .../include/usb/ehci-fsl.h                         |   22
 +++++++++++++++++
 2 files changed, 22 insertions(+), 26 deletions(-)
By applying this patchset I see several minor issues reported by checkpatch:
WARNING: line over 80 characters
#303: FILE: drivers/usb/host/ehci-mx5.c:43:
+#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable
*/
WARNING: line over 80 characters
#305: FILE: drivers/usb/host/ehci-mx5.c:45:
+#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt
enable */
WARNING: line over 80 characters
#306: FILE: drivers/usb/host/ehci-mx5.c:46:
+#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr
enable */
WARNING: line over 80 characters
#312: FILE: drivers/usb/host/ehci-mx5.c:50:
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable
Overcurrent
Event */
WARNING: line over 80 characters
#313: FILE: drivers/usb/host/ehci-mx5.c:51:
+#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event
*/
WARNING: line over 80 characters
#343: FILE: drivers/usb/host/ehci-mx5.c:174:
(quoted diff) +1 -0
+			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
WARNING: line over 80 characters
#352: FILE: drivers/usb/host/ehci-mx5.c:190:
(quoted diff) +1 -0
+			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
WARNING: line over 80 characters
#641: FILE: drivers/usb/host/ehci-mx5.c:47:
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin
polarity */
WARNING: line over 80 characters
#645: FILE: drivers/usb/host/ehci-mx5.c:51:
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin
polarity */
WARNING: line over 80 characters
#648: FILE: drivers/usb/host/ehci-mx5.c:54:
+#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of
Overcurrent */
WARNING: line over 80 characters
#650: FILE: drivers/usb/host/ehci-mx5.c:56:
+#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent
*/
WARNING: line over 80 characters
#652: FILE: drivers/usb/host/ehci-mx5.c:58:
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin
Polarity */
WARNING: line over 80 characters
#873: FILE: drivers/usb/host/ehci-mxc.c:85:
(quoted diff) +1 -0
+			MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
WARNING: line over 80 characters
#1078: FILE: drivers/usb/host/ehci-mxc.c:184:
(quoted diff) +1 -0
+			MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
WARNING: line over 80 characters
#1179: FILE: board/freescale/mx35pdk/mx35pdk.c:105:
(quoted diff) +1 -0
+	mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION |
MUX_CONFIG_FUNC);
WARNING: line over 80 characters
#1180: FILE: board/freescale/mx35pdk/mx35pdk.c:106:
(quoted diff) +1 -0
+	mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION |
MUX_CONFIG_FUNC);

Quoted 3 lines

total: 0 errors, 16 warnings, 810 lines checked
Can you fix them ? Thanks !

OK, I'll do that. For the #define-s, do you prefer that I move the comment to the previous line, or that I split the end of the comment to the next line?

Best regards,
Beno?t

Albert ARIBAUD

2012-11-10 12:46 UTC #36 lore raw

PATCH v2 1/13 mx31: Move EHCI definitions to ehci-fsl.h

Hi Beno?t,

Quoted 104 lines · Beno?t Th?baudeau

Hi Stefano,
Quoted 101 lines · Stefano Babic
Quoted 8 lines · Beno?t Th?baudeau
The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to
ehci-fsl.h so that all MXC SoCs can use them.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>
---
Hi Beno?t,
Quoted 8 lines
Changes for v2: None.
 .../arch/arm/include/asm/arch-mx31/imx-regs.h      |   26
 --------------------
 .../include/usb/ehci-fsl.h                         |   22
 +++++++++++++++++
 2 files changed, 22 insertions(+), 26 deletions(-)
By applying this patchset I see several minor issues reported by checkpatch:
WARNING: line over 80 characters
#303: FILE: drivers/usb/host/ehci-mx5.c:43:
+#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable
*/
WARNING: line over 80 characters
#305: FILE: drivers/usb/host/ehci-mx5.c:45:
+#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt
enable */
WARNING: line over 80 characters
#306: FILE: drivers/usb/host/ehci-mx5.c:46:
+#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr
enable */
WARNING: line over 80 characters
#312: FILE: drivers/usb/host/ehci-mx5.c:50:
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable
Overcurrent
Event */
WARNING: line over 80 characters
#313: FILE: drivers/usb/host/ehci-mx5.c:51:
+#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event
*/
WARNING: line over 80 characters
#343: FILE: drivers/usb/host/ehci-mx5.c:174:
(quoted diff) +1 -0
+			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
WARNING: line over 80 characters
#352: FILE: drivers/usb/host/ehci-mx5.c:190:
(quoted diff) +1 -0
+			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
WARNING: line over 80 characters
#641: FILE: drivers/usb/host/ehci-mx5.c:47:
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin
polarity */
WARNING: line over 80 characters
#645: FILE: drivers/usb/host/ehci-mx5.c:51:
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin
polarity */
WARNING: line over 80 characters
#648: FILE: drivers/usb/host/ehci-mx5.c:54:
+#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of
Overcurrent */
WARNING: line over 80 characters
#650: FILE: drivers/usb/host/ehci-mx5.c:56:
+#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent
*/
WARNING: line over 80 characters
#652: FILE: drivers/usb/host/ehci-mx5.c:58:
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin
Polarity */
WARNING: line over 80 characters
#873: FILE: drivers/usb/host/ehci-mxc.c:85:
(quoted diff) +1 -0
+			MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
WARNING: line over 80 characters
#1078: FILE: drivers/usb/host/ehci-mxc.c:184:
(quoted diff) +1 -0
+			MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
WARNING: line over 80 characters
#1179: FILE: board/freescale/mx35pdk/mx35pdk.c:105:
(quoted diff) +1 -0
+	mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION |
MUX_CONFIG_FUNC);
WARNING: line over 80 characters
#1180: FILE: board/freescale/mx35pdk/mx35pdk.c:106:
(quoted diff) +1 -0
+	mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION |
MUX_CONFIG_FUNC);

Quoted 6 lines

Quoted 3 lines
total: 0 errors, 16 warnings, 810 lines checked
Can you fix them ? Thanks !
OK, I'll do that. For the #define-s, do you prefer that I move the comment to the previous line, or that I split the end of the comment to the next line?

I'll let Stefano give a definitive answer of course, but I personally prefer that comments be moved before the defines.

Quoted 2 lines

Best regards,
Beno?t

Amicalement,

Signature · 1 line

Albert.

Albert ARIBAUD

2012-11-10 12:47 UTC #37 lore raw

PATCH v2 1/13 mx31: Move EHCI definitions to ehci-fsl.h

Quoted 2 lines

I'll let Stefano give a definitive answer of course, but I personally prefer that comments be moved before the defines.

Note: I mean that each comment should precede its corresponding define, of course; I don't want all these comments lumped together in a single block.

Amicalement,

Signature · 1 line

Albert.

Benoît Thébaudeau

author

2012-11-10 13:51 UTC #38 lore raw

PATCH v2 1/13 mx31: Move EHCI definitions to ehci-fsl.h

Quoted 9 lines · Albert ARIBAUD

Quoted 3 lines
I'll let Stefano give a definitive answer of course, but I personally
prefer that comments be moved before the defines.
Note: I mean that each comment should precede its corresponding define,
of course; I don't want all these comments lumped together in a single
block.

Sure. And if some comments fit at the end of the line, but not all, do you prefer to also move these fitting comments to the previous line for more consistency?

Cordialement,
Beno?t

stefano babic

2012-11-10 16:45 UTC #39 lore raw

PATCH v2 1/13 mx31: Move EHCI definitions to ehci-fsl.h

In reply to Benoît Thébaudeau

Am 10/11/2012 13:37, schrieb Beno?t Th?baudeau:

Quoted 104 lines

Hi Stefano,
Quoted 101 lines · Stefano Babic
Quoted 8 lines · Beno?t Th?baudeau
The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to
ehci-fsl.h so that all MXC SoCs can use them.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>
---
Hi Beno?t,
Quoted 8 lines
Changes for v2: None.
 .../arch/arm/include/asm/arch-mx31/imx-regs.h      |   26
 --------------------
 .../include/usb/ehci-fsl.h                         |   22
 +++++++++++++++++
 2 files changed, 22 insertions(+), 26 deletions(-)
By applying this patchset I see several minor issues reported by checkpatch:
WARNING: line over 80 characters
#303: FILE: drivers/usb/host/ehci-mx5.c:43:
+#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable
*/
WARNING: line over 80 characters
#305: FILE: drivers/usb/host/ehci-mx5.c:45:
+#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt
enable */
WARNING: line over 80 characters
#306: FILE: drivers/usb/host/ehci-mx5.c:46:
+#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr
enable */
WARNING: line over 80 characters
#312: FILE: drivers/usb/host/ehci-mx5.c:50:
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable
Overcurrent
Event */
WARNING: line over 80 characters
#313: FILE: drivers/usb/host/ehci-mx5.c:51:
+#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event
*/
WARNING: line over 80 characters
#343: FILE: drivers/usb/host/ehci-mx5.c:174:
(quoted diff) +1 -0
+			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */
WARNING: line over 80 characters
#352: FILE: drivers/usb/host/ehci-mx5.c:190:
(quoted diff) +1 -0
+			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */
WARNING: line over 80 characters
#641: FILE: drivers/usb/host/ehci-mx5.c:47:
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin
polarity */
WARNING: line over 80 characters
#645: FILE: drivers/usb/host/ehci-mx5.c:51:
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin
polarity */
WARNING: line over 80 characters
#648: FILE: drivers/usb/host/ehci-mx5.c:54:
+#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of
Overcurrent */
WARNING: line over 80 characters
#650: FILE: drivers/usb/host/ehci-mx5.c:56:
+#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent
*/
WARNING: line over 80 characters
#652: FILE: drivers/usb/host/ehci-mx5.c:58:
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin
Polarity */
WARNING: line over 80 characters
#873: FILE: drivers/usb/host/ehci-mxc.c:85:
(quoted diff) +1 -0
+			MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
WARNING: line over 80 characters
#1078: FILE: drivers/usb/host/ehci-mxc.c:184:
(quoted diff) +1 -0
+			MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
WARNING: line over 80 characters
#1179: FILE: board/freescale/mx35pdk/mx35pdk.c:105:
(quoted diff) +1 -0
+	mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_SION |
MUX_CONFIG_FUNC);
WARNING: line over 80 characters
#1180: FILE: board/freescale/mx35pdk/mx35pdk.c:106:
(quoted diff) +1 -0
+	mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_SION |
MUX_CONFIG_FUNC);

Quoted 6 lines

Quoted 3 lines
total: 0 errors, 16 warnings, 810 lines checked
Can you fix them ? Thanks !
OK, I'll do that. For the #define-s, do you prefer that I move the comment to the previous line, or that I split the end of the comment to the next line?

I have no preference, I usually move the comment to the previous line, but it is a question of taste ;-)

Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Benoît Thébaudeau

author

2012-11-13 19:55 UTC #40 lore raw

PATCH v3 1/13 mx31: Move EHCI definitions to ehci-fsl.h

In reply to Benoît Thébaudeau

The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.
Changes for v3: None.

 .../arch/arm/include/asm/arch-mx31/imx-regs.h      |   26 --------------------
 .../include/usb/ehci-fsl.h                         |   22 +++++++++++++++++
 2 files changed, 22 insertions(+), 26 deletions(-)

arch/arm/include/asm/arch-mx31/imx-regs.h +0 ~~-26~~

index 8fd3d08..01a849d 100644
@@ -896,32 +896,6 @@ struct esdc_regs {
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
 #define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
 
-/* USB portsc */
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
-#define MXC_EHCI_FORCE_FS		(1 << 24)
-#define MXC_EHCI_UTMI_8BIT		(0 << 28)
-#define MXC_EHCI_UTMI_16BIT		(1 << 28)
-#define MXC_EHCI_SERIAL			(1 << 29)
-#define MXC_EHCI_MODE_UTMI		(0 << 30)
-#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
-#define MXC_EHCI_MODE_ULPI		(2 << 30)
-#define MXC_EHCI_MODE_SERIAL		(3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
-#define MXC_EHCI_INTERFACE_MASK		(0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
-#define MXC_EHCI_TTL_ENABLED		(1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY		(1 << 7)
-#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
-#define MXC_EHCI_IPPUE_UP		(1 << 9)
-
 /*
  * CSPI register definitions
  */

include/usb/ehci-fsl.h +22 -0

index 2869302..4dee5b0 100644
@@ -246,9 +246,31 @@ struct usb_ehci {
 /*
  * For MXC SOCs
  */
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
+#define MXC_EHCI_FORCE_FS		(1 << 24)
+#define MXC_EHCI_UTMI_8BIT		(0 << 28)
+#define MXC_EHCI_UTMI_16BIT		(1 << 28)
+#define MXC_EHCI_SERIAL			(1 << 29)
+#define MXC_EHCI_MODE_UTMI		(0 << 30)
+#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
+#define MXC_EHCI_MODE_ULPI		(2 << 30)
+#define MXC_EHCI_MODE_SERIAL		(3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
+#define MXC_EHCI_INTERFACE_MASK		(0xf)
+
 #define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
 #define MXC_EHCI_TTL_ENABLED		(1 << 6)
+
 #define MXC_EHCI_INTERNAL_PHY		(1 << 7)
+#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
+#define MXC_EHCI_IPPUE_UP		(1 << 9)
 
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);

Benoît Thébaudeau

author

2012-11-13 19:55 UTC #41 lore raw

PATCH v3 2/13 ehci-mxc: Clean up

Clean up ehci-mxc:
- Remove useless #if's.
- Fix identation.
- Issue a #error if used with an unsupported platform.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.
Changes for v3: None.

 .../drivers/usb/host/ehci-mxc.c                    |   86 +++++++++-----------
 1 file changed, 40 insertions(+), 46 deletions(-)

drivers/usb/host/ehci-mxc.c +40 ~~-46~~

index a38bc9c..e21f2c5 100644
@@ -28,14 +28,11 @@
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
-#ifdef CONFIG_MX25
 #define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
 #define MX25_USB_CTRL_HSTD_BIT		(1<<5)
 #define MX25_USB_CTRL_USBTE_BIT		(1<<4)
 #define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
-#endif
 
-#ifdef CONFIG_MX31
 #define MX31_OTG_SIC_SHIFT	29
 #define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
 #define MX31_OTG_PM_BIT		(1 << 24)

@@ -49,59 +46,56 @@
 #define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
 #define MX31_H1_PM_BIT		(1 << 8)
 #define MX31_H1_DT_BIT		(1 << 4)
-#endif
 
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
 
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25)
 	v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
 		MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#endif
+#elif defined(CONFIG_MX31)
+	v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
 
-#ifdef CONFIG_MX31
-		v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-
-		switch (port) {
-		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
-
-			break;
-		case 1: /* H1 port */
-			v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
-				MX31_H1_DT_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-						<< MX31_H1_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_H1_PM_BIT;
-
-			if (!(flags & MXC_EHCI_TTL_ENABLED))
-				v |= MX31_H1_DT_BIT;
-
-			break;
-		case 2:	/* H2 port */
-			v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
-				MX31_H2_DT_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-						<< MX31_H2_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_H2_PM_BIT;
-
-			if (!(flags & MXC_EHCI_TTL_ENABLED))
-				v |= MX31_H2_DT_BIT;
-
-			break;
-		default:
-			return -EINVAL;
-		}
-#endif
+	switch (port) {
+	case 0:	/* OTG port */
+		v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_OTG_PM_BIT;
+
+		break;
+	case 1: /* H1 port */
+		v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
 
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_H1_PM_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX31_H1_DT_BIT;
+
+		break;
+	case 2:	/* H2 port */
+		v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_H2_PM_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX31_H2_DT_BIT;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+#else
+#error MXC EHCI USB driver not supported on this platform
+#endif
 	writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+
 	return 0;
 }

Stefano Babic

2012-11-16 08:29 UTC #42 lore raw

PATCH v3 2/13 ehci-mxc: Clean up

Quoted 9 lines · Beno?t Th?baudeau

Clean up ehci-mxc:
- Remove useless #if's.
- Fix identation.
- Issue a #error if used with an unsupported platform.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>
---

Applied (whole sries) to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Benoît Thébaudeau

author

2012-11-13 19:56 UTC #43 lore raw

PATCH v3 3/13 ehci-mx5: Clean up

In reply to Benoît Thébaudeau

Clean up ehci-mx5:
- Fix column alignments.
- Fix comments.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.
Changes for v3:
- Fix lines over 80 characters.

 .../drivers/usb/host/ehci-mx5.c                    |   45 +++++++++++---------
 1 file changed, 26 insertions(+), 19 deletions(-)

drivers/usb/host/ehci-mx5.c +26 ~~-19~~

index 9a2c295..46973b0 100644
@@ -29,9 +29,9 @@
 #define MX5_USBOTHER_REGS_OFFSET 0x800
 
 
-#define MXC_OTG_OFFSET		0
-#define MXC_H1_OFFSET		0x200
-#define MXC_H2_OFFSET		0x400
+#define MXC_OTG_OFFSET			0
+#define MXC_H1_OFFSET			0x200
+#define MXC_H2_OFFSET			0x400
 
 #define MXC_USBCTRL_OFFSET		0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET	0x8

@@ -40,23 +40,30 @@
 #define MXC_USBH2CTRL_OFFSET		0x14
 
 /* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT	(1 << 27) /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT	(1 << 24) /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT	(1 << 12) /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT	(1 << 11) /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT	(1 << 8) /* HOST1 power mask */
+/* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)
+/* OTG power mask */
+#define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)
+/* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)
+/* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)
+/* HOST1 power mask */
+#define MXC_H1_UCTRL_H1PM_BIT		(1 << 8)
 
 /* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT	(1 << 5) /* UH1 Disable Overcurrent Event */
+/* OTG Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)
+/* UH1 Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT		(1 << 5)
 
 /* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT	(1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT	(1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT	(1 << 4)
+#define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
 
 /* USB_CTRL_1 */
-#define MXC_USB_CTRL_UH1_EXT_CLK_EN		(1 << 25)
+#define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)
 
 /* USB pin configuration */
 #define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \

@@ -160,7 +167,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;
-	case 1:	/* Host 1 Host ULPI */
+	case 1:	/* Host 1 ULPI */
 #ifdef CONFIG_MX51
 		/* The clock for the USBH1 ULPI port will come externally
 		   from the PHY. */

@@ -171,9 +178,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
 		else
-			v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+			v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
 		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
 		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

@@ -187,9 +194,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 	case 2: /* Host 2 ULPI */
 		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
 		else
-			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+			v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
 
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
 		break;

Benoît Thébaudeau

author

2012-11-13 19:56 UTC #44 lore raw

PATCH v3 4/13 ehci-mx5: Fix OC_DIS usage

In reply to Benoît Thébaudeau

MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like MXC_H1_OC_DIS_BIT, not the opposite.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.
Changes for v3: None.

 .../drivers/usb/host/ehci-mx5.c                                  |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/usb/host/ehci-mx5.c +3 -3

index 46973b0..72cde1a 100644
@@ -151,11 +151,11 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			v = __raw_readl(usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-				/* OC/USBPWR is not used */
-				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-			else
 				/* OC/USBPWR is used */
 				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+			else
+				/* OC/USBPWR is not used */
+				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
 			__raw_writel(v, usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);

Benoît Thébaudeau

author

2012-11-13 19:56 UTC #45 lore raw

PATCH v3 5/13 ehci-mx5: Fix OPM usage

In reply to Benoît Thébaudeau

MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like MXC_H1_UCTRL_H1PM_BIT and MXC_H2_UCTRL_H2PM_BIT, not the opposite.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.
Changes for v3: None.

 .../drivers/usb/host/ehci-mx5.c                                    |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/usb/host/ehci-mx5.c +2 -2

index 72cde1a..8c1b70a 100644
@@ -161,9 +161,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 
 			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-				v |= MXC_OTG_UCTRL_OPM_BIT;
-			else
 				v &= ~MXC_OTG_UCTRL_OPM_BIT;
+			else
+				v |= MXC_OTG_UCTRL_OPM_BIT;
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;

Benoît Thébaudeau

author

2012-11-13 19:56 UTC #46 lore raw

PATCH v3 6/13 ehci-mx5: Fix *PM usage for i.MX53

In reply to Benoît Thébaudeau

The MXC_*_UCTRL_*PM_BIT bits are available only on i.MX51.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.
Changes for v3: None.

 .../drivers/usb/host/ehci-mx5.c                                 |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

drivers/usb/host/ehci-mx5.c +6 -1

index 8c1b70a..4f4b98a 100644
@@ -160,10 +160,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
 
 			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 				v &= ~MXC_OTG_UCTRL_OPM_BIT;
 			else
 				v |= MXC_OTG_UCTRL_OPM_BIT;
+#endif
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;

@@ -177,10 +179,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 #endif
 
 		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
 		else
 			v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
+#endif
 		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
 		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

@@ -193,11 +197,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		break;
 	case 2: /* Host 2 ULPI */
 		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+#ifdef CONFIG_MX51
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
 		else
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
-
+#endif
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
 		break;
 	}

Benoît Thébaudeau

author

2012-11-13 19:57 UTC #47 lore raw

PATCH v3 7/13 ehci-mx5: Add missing OC_DIS for i.MX53

In reply to Benoît Thébaudeau

The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.
Changes for v3: None.

 .../drivers/usb/host/ehci-mx5.c                    |   24 ++++++++++++++++++++
 1 file changed, 24 insertions(+)

drivers/usb/host/ehci-mx5.c +24 -0

index 4f4b98a..6f7fe80 100644
@@ -32,12 +32,14 @@
 #define MXC_OTG_OFFSET			0
 #define MXC_H1_OFFSET			0x200
 #define MXC_H2_OFFSET			0x400
+#define MXC_H3_OFFSET			0x600
 
 #define MXC_USBCTRL_OFFSET		0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET	0x8
 #define MXC_USB_PHY_CTR_FUNC2_OFFSET	0xc
 #define MXC_USB_CTRL_1_OFFSET		0x10
 #define MXC_USBH2CTRL_OFFSET		0x14
+#define MXC_USBH3CTRL_OFFSET		0x18
 
 /* USB_CTRL */
 /* OTG wakeup intr enable */

@@ -58,10 +60,16 @@
 #define MXC_H1_OC_DIS_BIT		(1 << 5)
 
 /* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_DIS_BIT	(1 << 30)
 #define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
 #define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
 #define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
 
+/* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_DIS_BIT	(1 << 30)
+#define MXC_H3_UCTRL_H3UIE_BIT		(1 << 8)
+#define MXC_H3_UCTRL_H3WIE_BIT		(1 << 7)
+
 /* USB_CTRL_1 */
 #define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

@@ -203,8 +211,24 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		else
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
 #endif
+#ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+			v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
+		else
+			v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+#endif
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
 		break;
+#ifdef CONFIG_MX53
+	case 3: /* Host 3 ULPI */
+		v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+			v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
+		else
+			v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+		__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
+		break;
+#endif
 	}
 
 	return ret;

Benoît Thébaudeau

author

2012-11-13 19:57 UTC #48 lore raw

PATCH v3 8/13 ehci-mxc: Make EHCI power/oc polarities configurable

In reply to Benoît Thébaudeau

Make EHCI power and overcurrent polarities configurable. If not set, these new configurartions keep the default register values so that existing board files do not have to be changed.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.
Changes for v3:
- Fix lines over 80 characters.

 .../drivers/usb/host/ehci-mx5.c                    |   56 ++++++++++++++++++++
 .../include/usb/ehci-fsl.h                         |   10 ++--
 2 files changed, 62 insertions(+), 4 deletions(-)

drivers/usb/host/ehci-mx5.c +56 -0

index 6f7fe80..7e60c3c 100644
@@ -46,29 +46,43 @@
 #define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)
 /* OTG power mask */
 #define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)
+/* OTG power pin polarity */
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT	(1 << 24)
 /* Host1 ULPI interrupt enable */
 #define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)
 /* HOST1 wakeup intr enable */
 #define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)
 /* HOST1 power mask */
 #define MXC_H1_UCTRL_H1PM_BIT		(1 << 8)
+/* HOST1 power pin polarity */
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT	(1 << 8)
 
 /* USB_PHY_CTRL_FUNC */
+/* OTG Polarity of Overcurrent */
+#define MXC_OTG_PHYCTRL_OC_POL_BIT	(1 << 9)
 /* OTG Disable Overcurrent Event */
 #define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)
+/* UH1 Polarity of Overcurrent */
+#define MXC_H1_OC_POL_BIT		(1 << 6)
 /* UH1 Disable Overcurrent Event */
 #define MXC_H1_OC_DIS_BIT		(1 << 5)
+/* OTG Power Pin Polarity */
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT	(1 << 3)
 
 /* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_POL_BIT	(1 << 31)
 #define MXC_H2_UCTRL_H2_OC_DIS_BIT	(1 << 30)
 #define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
 #define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
 #define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
+#define MXC_H2_UCTRL_H2_PWR_POL_BIT	(1 << 4)
 
 /* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_POL_BIT	(1 << 31)
 #define MXC_H3_UCTRL_H3_OC_DIS_BIT	(1 << 30)
 #define MXC_H3_UCTRL_H3UIE_BIT		(1 << 8)
 #define MXC_H3_UCTRL_H3WIE_BIT		(1 << 7)
+#define MXC_H3_UCTRL_H3_PWR_POL_BIT	(1 << 4)
 
 /* USB_CTRL_1 */
 #define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

@@ -158,12 +172,22 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		if (flags & MXC_EHCI_INTERNAL_PHY) {
 			v = __raw_readl(usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
+			if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+				v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
+			else
+				v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 				/* OC/USBPWR is used */
 				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
 			else
 				/* OC/USBPWR is not used */
 				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+#ifdef CONFIG_MX51
+			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+				v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
+			else
+				v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
+#endif
 			__raw_writel(v, usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);

@@ -174,6 +198,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			else
 				v |= MXC_OTG_UCTRL_OPM_BIT;
 #endif
+#ifdef CONFIG_MX53
+			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+				v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
+			else
+				v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
+#endif
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;

@@ -193,9 +223,19 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		else
 			v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
 #endif
+#ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
+		else
+			v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
+#endif
 		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
 		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H1_OC_POL_BIT;
+		else
+			v &= ~MXC_H1_OC_POL_BIT;
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
 		else

@@ -212,20 +252,36 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 			v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
 #endif
 #ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
+		else
+			v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
 		else
 			v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
+		else
+			v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
 #endif
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
 		break;
 #ifdef CONFIG_MX53
 	case 3: /* Host 3 ULPI */
 		v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
+		else
+			v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
 		else
 			v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
+		else
+			v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
 		__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
 		break;
 #endif

include/usb/ehci-fsl.h +6 -4

index 4dee5b0..a1438d6 100644
@@ -266,11 +266,13 @@ struct usb_ehci {
 #define MXC_EHCI_INTERFACE_MASK		(0xf)
 
 #define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
-#define MXC_EHCI_TTL_ENABLED		(1 << 6)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH	(1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW	(1 << 7)
+#define MXC_EHCI_TTL_ENABLED		(1 << 8)
 
-#define MXC_EHCI_INTERNAL_PHY		(1 << 7)
-#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
-#define MXC_EHCI_IPPUE_UP		(1 << 9)
+#define MXC_EHCI_INTERNAL_PHY		(1 << 9)
+#define MXC_EHCI_IPPUE_DOWN		(1 << 10)
+#define MXC_EHCI_IPPUE_UP		(1 << 11)
 
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);

Benoît Thébaudeau

author

2012-11-13 19:57 UTC #49 lore raw

PATCH v3 9/13 ehci-mxc: Make i.MX25 EHCI configurable

In reply to Benoît Thébaudeau

Use EHCI MXC configuration options for i.MX25.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Matthias Weisser <[email protected]>

---
Changes for v2: None.
Changes for v3:
- Fix lines over 80 characters.

 .../drivers/usb/host/ehci-mxc.c                    |   72 +++++++++++++++++---
 .../include/configs/zmx25.h                        |    6 +-
 2 files changed, 67 insertions(+), 11 deletions(-)

drivers/usb/host/ehci-mxc.c +64 -8

index e21f2c5..846aa3b 100644
@@ -28,10 +28,21 @@
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
-#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
-#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
+#define MX25_OTG_SIC_SHIFT	29
+#define MX25_OTG_SIC_MASK	(0x3 << MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BIT		(1 << 24)
+#define MX25_OTG_PP_BIT		(1 << 11)
+#define MX25_OTG_OCPOL_BIT	(1 << 3)
+
+#define MX25_H1_SIC_SHIFT	21
+#define MX25_H1_SIC_MASK	(0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT		(1 << 18)
+#define MX25_H1_PM_BIT		(1 << 8)
+#define MX25_H1_IPPUE_UP_BIT	(1 << 7)
+#define MX25_H1_IPPUE_DOWN_BIT	(1 << 6)
+#define MX25_H1_TLL_BIT		(1 << 5)
+#define MX25_H1_USBTE_BIT	(1 << 4)
+#define MX25_H1_OCPOL_BIT	(1 << 2)
 
 #define MX31_OTG_SIC_SHIFT	29
 #define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)

@@ -51,12 +62,57 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
 
-#if defined(CONFIG_MX25)
-	v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
-		MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#elif defined(CONFIG_MX31)
 	v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+#if defined(CONFIG_MX25)
+	switch (port) {
+	case 0:	/* OTG port */
+		v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
+				MX25_OTG_OCPOL_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX25_OTG_PM_BIT;
+
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MX25_OTG_PP_BIT;
+
+		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+			v |= MX25_OTG_OCPOL_BIT;
+
+		break;
+	case 1: /* H1 port */
+		v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
+				MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
+				MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
+				MX25_H1_IPPUE_UP_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX25_H1_PM_BIT;
+
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MX25_H1_PP_BIT;
+
+		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+			v |= MX25_H1_OCPOL_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX25_H1_TLL_BIT;
+
+		if (flags & MXC_EHCI_INTERNAL_PHY)
+			v |= MX25_H1_USBTE_BIT;
+
+		if (flags & MXC_EHCI_IPPUE_DOWN)
+			v |= MX25_H1_IPPUE_DOWN_BIT;
 
+		if (flags & MXC_EHCI_IPPUE_UP)
+			v |= MX25_H1_IPPUE_UP_BIT;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+#elif defined(CONFIG_MX31)
 	switch (port) {
 	case 0:	/* OTG port */
 		v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);

include/configs/zmx25.h +3 -3

index 447683a..e9216d9 100644
@@ -109,9 +109,9 @@
 #define CONFIG_USB_EHCI			/* Enable EHCI USB support */
 #define CONFIG_USB_EHCI_MXC
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT	2
-#define CONFIG_MXC_USB_PORTSC	0xC0000000
-#define CONFIG_MXC_USB_FLAGS	0
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	MXC_EHCI_MODE_SERIAL
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_STORAGE
 #define CONFIG_DOS_PARTITION

Benoît Thébaudeau

author

2012-11-13 19:57 UTC #50 lore raw

PATCH v3 10/13 ehci-mxc: Define host offsets

In reply to Benoît Thébaudeau

Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at SoC level.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.
Changes for v3: None.

 .../arch/arm/include/asm/arch-mx25/imx-regs.h                        |    1 +
 .../arch/arm/include/asm/arch-mx31/imx-regs.h                        |    1 +
 .../drivers/usb/host/ehci-mxc.c                                      |    2 +-
 3 files changed, 3 insertions(+), 1 deletion(-)

arch/arm/include/asm/arch-mx25/imx-regs.h +1 -0

index e780296..c1bc4bc 100644
@@ -246,6 +246,7 @@ struct aips_regs {
 #define IMX_RTIC_BASE		(0x53FEC000)
 #define IMX_IIM_BASE		(0x53FF0000)
 #define IMX_USB_BASE		(0x53FF4000)
+#define IMX_USB_PORT_OFFSET	0x200
 #define IMX_CSI_BASE		(0x53FF8000)
 #define IMX_DRYICE_BASE		(0x53FFC000)

arch/arm/include/asm/arch-mx31/imx-regs.h +1 -0

index 01a849d..ae3658b 100644
@@ -895,6 +895,7 @@ struct esdc_regs {
 
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
 #define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_PORT_OFFSET	0x200
 
 /*
  * CSPI register definitions

drivers/usb/host/ehci-mxc.c +1 -1

index 846aa3b..6260a8c 100644
@@ -169,7 +169,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 	udelay(80);
 
 	ehci = (struct usb_ehci *)(IMX_USB_BASE +
-		(0x200 * CONFIG_MXC_USB_PORT));
+			IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
 	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
 			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

Benoît Thébaudeau

author

2012-11-13 19:58 UTC #51 lore raw

PATCH v3 11/13 ehci-mxc: Add support for i.MX35

In reply to Benoît Thébaudeau

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2: None.
Changes for v3:
- Fix lines over 80 characters.

 .../arch/arm/include/asm/arch-mx35/imx-regs.h      |    2 +
 .../drivers/usb/host/ehci-mxc.c                    |   69 ++++++++++++++++++++
 2 files changed, 71 insertions(+)

arch/arm/include/asm/arch-mx35/imx-regs.h +2 -0

index 7b09809..cd7716f 100644
@@ -82,6 +82,8 @@
 #define PWM_BASE_ADDR		0x53FE0000
 #define RTIC_BASE_ADDR		0x53FEC000
 #define IIM_BASE_ADDR		0x53FF0000
+#define IMX_USB_BASE		0x53FF4000
+#define IMX_USB_PORT_OFFSET	0x400
 
 #define IMX_CCM_BASE		CCM_BASE_ADDR

drivers/usb/host/ehci-mxc.c +69 -0

87 lines not on this page · raw message

Benoît Thébaudeau

author

2012-11-13 19:58 UTC #52 lore raw

PATCH v3 12/13 mx35pdk: Add support for OTG

In reply to Benoît Thébaudeau

Add support for the OTG port on the mx35pdk Personality board.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Tested-by Stefano Babic <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Marek Vasut <[email protected]>

---
Changes for v2:
- Tested by Stefano.
Changes for v3:
- Fix lines over 80 characters.

 .../board/freescale/mx35pdk/lowlevel_init.S        |    4 ++++
 .../board/freescale/mx35pdk/mx35pdk.c              |   21 ++++++++++++++++++++
 .../include/configs/mx35pdk.h                      |   14 +++++++++++++
 3 files changed, 39 insertions(+)

board/freescale/mx35pdk/lowlevel_init.S +4 -0

index 698c4cf..6f4d4e0 100644
@@ -178,6 +178,10 @@
 	orr r1, r1, #0x00000C00
 	orr r1, r1, #0x00000003
 	str r1, [r0, #CLKCTL_CGR1]
+
+	ldr r1, [r0, #CLKCTL_CGR2]
+	orr r1, r1, #0x00C00000
+	str r1, [r0, #CLKCTL_CGR2]
 .endm
 
 .macro setup_sdram

board/freescale/mx35pdk/mx35pdk.c +21 -0

index 7cb6b30..4fa2c27 100644
@@ -97,6 +97,26 @@ static void setup_iomux_spi(void)
 	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
 }
 
+static void setup_iomux_usbotg(void)
+{
+	int in_pad, out_pad;
+
+	/* Set up pins for USBOTG. */
+	mxc_request_iomux(MX35_PIN_USBOTG_PWR,
+			  MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_USBOTG_OC,
+			  MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+	in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+		PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+	out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+		PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+	mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+	mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
 static void setup_iomux_fec(void)
 {
 	int pad;

@@ -188,6 +208,7 @@ int board_early_init_f(void)
 	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 
 	setup_iomux_i2c();
+	setup_iomux_usbotg();
 	setup_iomux_fec();
 	setup_iomux_spi();

include/configs/mx35pdk.h +14 -0

index 826c912..69b7d23 100644
@@ -110,6 +110,8 @@
 #define CONFIG_NET_RETRY_COUNT	100
 #define CONFIG_CMD_DATE
 
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
 #define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION

@@ -242,6 +244,18 @@
 #define CONFIG_MXC_NAND_HWECC
 #define CONFIG_SYS_NAND_LARGEPAGE
 
+/* EHCI driver */
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT	0
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERFACE_DIFF_UNI | \
+				 MXC_EHCI_POWER_PINS_ENABLED | \
+				 MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
 /* mmc driver */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC

Benoît Thébaudeau

author

2012-11-13 19:58 UTC #53 lore raw

PATCH v3 13/13 ehci-mx5/6: Make board_ehci_hcd_init() optional

In reply to Benoît Thébaudeau

A custom board_ehci_hcd_init() may be unneeded, so add a weak default implementation doing nothing.

By the way, use simple __weak from linux/compiler.h for board_ehci_hcd_postinit() instead of weak alias with full attribute.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Use simple __weak from linux/compiler.h instead of __attribute__.
- Also use __weak instead of __attribute__ for board_ehci_hcd_postinit().
- Extend to ehci-mx6.c.
Changes for v3: None.

 .../drivers/usb/host/ehci-mx5.c                                |    8 +++++---
 .../drivers/usb/host/ehci-mx6.c                                |    5 +++++
 2 files changed, 10 insertions(+), 3 deletions(-)

drivers/usb/host/ehci-mx5.c +5 -3

index 7e60c3c..adbed5c 100644
@@ -290,12 +290,14 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 	return ret;
 }
 
-void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+int __weak board_ehci_hcd_init(int port)
 {
+	return 0;
 }
 
-void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
-	__attribute((weak, alias("__board_ehci_hcd_postinit")));
+void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+{
+}
 
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {

drivers/usb/host/ehci-mx6.c +5 -0

index 9ce25da..1b20e41 100644
@@ -159,6 +159,11 @@ static void usbh1_oc_config(void)
 	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
 }
 
+int __weak board_ehci_hcd_init(int port)
+{
+	return 0;
+}
+
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	struct usb_ehci *ehci;