Patches for 2.6.24
Subsystems (6)
These patches are my latest round of patches for 2.6.24. Posted here for review/comment. All these patches exist in:
master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git for-2.6.24
- k
PATCH 1/5 85xx: Add basic Uniprocessor MPC8572 DS port
Added basic board port for MPC8572 DS reference platform that is similiar to the MPC8544/33 DS reference platform in uniprocessor mode.
Signed-off-by Kumar Gala <[email protected]>
--- arch/powerpc/boot/dts/mpc8572ds.dts | 404 ++++++++ arch/powerpc/configs/mpc8572_ds_defconfig | 1496 +++++++++++++++++++++++++++++ arch/powerpc/platforms/85xx/mpc85xx_ds.c | 31 + arch/powerpc/sysdev/fsl_pci.c | 2 + include/linux/pci_ids.h | 2 + 5 files changed, 1935 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/mpc8572ds.dts create mode 100644 arch/powerpc/configs/mpc8572_ds_defconfig
arch/powerpc/boot/dts/mpc8572ds.dts new file +404 -0
@@ -0,0 +1,404 @@ +/* + * MPC8572 DS Device Tree Source + * + * Copyright 2007 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/ { + model = "fsl,MPC8572DS"; + compatible = "fsl,MPC8572DS"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8572@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <20>; // 32 bytes + i-cache-line-size = <20>; // 32 bytes + d-cache-size = <8000>; // L1, 32K + i-cache-size = <8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <00000000 00000000>; // Filled by U-Boot + }; + + soc8572@ffe00000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <00000000 ffe00000 00100000>; + reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed + bus-frequency = <0>; // Filled out by uboot. + + memory-controller@2000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <2000 1000>; + interrupt-parent = <&mpic>; + interrupts = <12 2>; + }; + + memory-controller@6000 { + compatible = "fsl,mpc8572-memory-controller"; + reg = <6000 1000>; + interrupt-parent = <&mpic>; + interrupts = <12 2>; + }; + + l2-cache-controller@20000 { + compatible = "fsl,mpc8572-l2-cache-controller"; + reg = <20000 1000>; + cache-line-size = <20>; // 32 bytes + cache-size = <80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <10 2>; + }; + + i2c@3000 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3000 100>; + interrupts = <2b 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3100 100>; + interrupts = <2b 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "mdio"; + compatible = "gianfar"; + reg = <24520 20>; + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <a 1>; + reg = <0>; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <a 1>; + reg = <1>; + }; + phy2: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <a 1>; + reg = <2>; + }; + phy3: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = <a 1>; + reg = <3>; + }; + }; + + ethernet@24000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <24000 1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <1d 2 1e 2 22 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + }; + + ethernet@25000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <25000 1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <23 2 24 2 28 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; + + ethernet@26000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <26000 1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <1f 2 20 2 21 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy2>; + phy-connection-type = "rgmii-id"; + }; + + ethernet@27000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <27000 1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <25 2 26 2 27 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy3>; + phy-connection-type = "rgmii-id"; + }; + + serial@4500 { + device_type = "serial"; + compatible = "ns16550"; + reg = <4500 100>; + clock-frequency = <0>; + interrupts = <2a 2>; + interrupt-parent = <&mpic>; + }; + + serial@4600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <4600 100>; + clock-frequency = <0>; + interrupts = <2a 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8572-guts"; + reg = <e0000 1000>; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <40000 40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; + }; + }; + + pcie@ffe08000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <ffe08000 1000>; + bus-range = <0 ff>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 ffc00000 0 00010000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + interrupt-map-mask = <fb00 0 0 0>; + interrupt-map = < + /* IDSEL 0x11 - PCI slot 1 */ + 8800 0 0 1 &mpic 2 1 + 8800 0 0 2 &mpic 3 1 + 8800 0 0 3 &mpic 4 1 + 8800 0 0 4 &mpic 1 1 + + /* IDSEL 0x12 - PCI slot 2 */ + 9000 0 0 1 &mpic 3 1 + 9000 0 0 2 &mpic 4 1 + 9000 0 0 3 &mpic 1 1 + 9000 0 0 4 &mpic 2 1 + + // IDSEL 0x1c USB + e000 0 0 0 &i8259 c 2 + e100 0 0 0 &i8259 9 2 + e200 0 0 0 &i8259 a 2 + e300 0 0 0 &i8259 b 2 + + // IDSEL 0x1d Audio + e800 0 0 0 &i8259 6 2 + + // IDSEL 0x1e Legacy + f000 0 0 0 &i8259 7 2 + f100 0 0 0 &i8259 7 2 + + // IDSEL 0x1f IDE/SATA + f800 0 0 0 &i8259 e 2 + f900 0 0 0 &i8259 5 2 + + >; + + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + uli1575@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + isa@1e { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = <f000 0 0 0 0>; + ranges = <1 0 01000000 0 0 + 00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + reg = <1 20 2 + 1 a0 2 + 1 4d0 2>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "chrp,iic"; + interrupts = <9 2>; + interrupt-parent = <&mpic>; + }; + + i8042@60 { + #size-cells = <0>; + #address-cells = <1>; + reg = <1 60 1 1 64 1>; + interrupts = <1 3 c 3>; + interrupt-parent = + <&i8259>; + + keyboard@0 { + reg = <0>; + compatible = "pnpPNP,303"; + }; + + mouse@1 { + reg = <1>; + compatible = "pnpPNP,f03"; + }; + }; + + rtc@70 { + compatible = "pnpPNP,b00"; + reg = <1 70 2>; + }; + + gpio@400 { + reg = <1 400 80>; + }; + }; + }; + }; + + }; + + pcie@ffe09000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <ffe09000 1000>; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 ffc10000 0 00010000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <02000000 0 a0000000 + 02000000 0 a0000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + }; + }; + + pcie@ffe0a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <ffe0a000 1000>; + bus-range = <0 ff>; + ranges = <02000000 0 c0000000 c0000000 0 20000000 + 01000000 0 00000000 ffc20000 0 00010000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <1b 2>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <02000000 0 c0000000 + 02000000 0 c0000000 + 0 20000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + }; + }; +};
arch/powerpc/configs/mpc8572_ds_defconfig new file +1496 -0
1,496 lines not on this page · raw message
arch/powerpc/platforms/85xx/mpc85xx_ds.c +31 -0
@@ -181,6 +181,23 @@ static int __init mpc8544_ds_probe(void) } } +/* +* Called very early, device-tree isn't unflattened +*/ +static int __init mpc8572_ds_probe (void ) +{ +unsigned long root =of_get_flat_dt_root (); + +if (of_flat_dt_is_compatible (root,"fsl,MPC8572DS" )) { +#ifdef CONFIG_PCI + primary_phb_addr =0x8000 ; +#endif +return 1 ; + }else { +return 0 ; + } +} +define_machine (mpc8544_ds) { .name = "MPC8544 DS", .probe = mpc8544_ds_probe,
@@ -194,3 +211,17 @@ define_machine(mpc8544_ds) { .calibrate_decr = generic_calibrate_decr, .progress = udbg_progress, }; + +define_machine (mpc8572_ds) { + .name = "MPC8572 DS", + .probe = mpc8572_ds_probe, + .setup_arch = mpc85xx_ds_setup_arch, + .init_IRQ = mpc85xx_ds_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = mpc85xx_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +};
arch/powerpc/sysdev/fsl_pci.c +2 -0
@@ -255,5 +255,7 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_transpareDECLARE_PCI_FIXUP_EARLY (0x1957 ,PCI_DEVICE_ID_MPC8533 , quirk_fsl_pcie_transparent);DECLARE_PCI_FIXUP_EARLY (0x1957 ,PCI_DEVICE_ID_MPC8544E , quirk_fsl_pcie_transparent);DECLARE_PCI_FIXUP_EARLY (0x1957 ,PCI_DEVICE_ID_MPC8544 , quirk_fsl_pcie_transparent); +DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_transparent) +DECLARE_PCI_FIXUP_EARLY (0x1957 ,PCI_DEVICE_ID_MPC8572 , quirk_fsl_pcie_transparent);DECLARE_PCI_FIXUP_EARLY (0x1957 ,PCI_DEVICE_ID_MPC8641 , quirk_fsl_pcie_transparent);DECLARE_PCI_FIXUP_EARLY (0x1957 ,PCI_DEVICE_ID_MPC8641D , quirk_fsl_pcie_transparent);
include/linux/pci_ids.h +2 -0
@@ -2100,6 +2100,8 @@#define PCI_DEVICE_ID_MPC8533 0x0031#define PCI_DEVICE_ID_MPC8544E 0x0032#define PCI_DEVICE_ID_MPC8544 0x0033 +#define PCI_DEVICE_ID_MPC8572E 0x0040 +#define PCI_DEVICE_ID_MPC8572 0x0041#define PCI_DEVICE_ID_MPC8641 0x7010#define PCI_DEVICE_ID_MPC8641D 0x7011
Signature · 1 line
1.5.2.4
PATCH 2/5 DTS cleanup
Removed the following cruft from .dts files:
* 32-bit in cpu node -- doesn't exist in any spec and not used by kernel
* removed built-in (chrp legacy)
* Removed #interrupt-cells in places they don't need to be set
* Fixed ranges on lite5200*
* Removed clock-frequency from i8259 pic node, not sure where this came from
Signed-off-by Kumar Gala <[email protected]>
--- arch/powerpc/boot/dts/holly.dts | 1 - arch/powerpc/boot/dts/kuroboxHD.dts | 2 -- arch/powerpc/boot/dts/kuroboxHG.dts | 2 -- arch/powerpc/boot/dts/lite5200.dts | 7 ++----- arch/powerpc/boot/dts/lite5200b.dts | 7 ++----- arch/powerpc/boot/dts/mpc7448hpc2.dts | 4 ---- arch/powerpc/boot/dts/mpc8272ads.dts | 5 ----- arch/powerpc/boot/dts/mpc8313erdb.dts | 3 --- arch/powerpc/boot/dts/mpc832x_mds.dts | 4 ---- arch/powerpc/boot/dts/mpc832x_rdb.dts | 4 ---- arch/powerpc/boot/dts/mpc8349emitx.dts | 3 --- arch/powerpc/boot/dts/mpc8349emitxgp.dts | 3 --- arch/powerpc/boot/dts/mpc834x_mds.dts | 3 --- arch/powerpc/boot/dts/mpc836x_mds.dts | 4 ---- arch/powerpc/boot/dts/mpc8540ads.dts | 3 --- arch/powerpc/boot/dts/mpc8541cds.dts | 6 ------ arch/powerpc/boot/dts/mpc8544ds.dts | 5 ----- arch/powerpc/boot/dts/mpc8548cds.dts | 5 ----- arch/powerpc/boot/dts/mpc8555cds.dts | 6 ------ arch/powerpc/boot/dts/mpc8560ads.dts | 5 ----- arch/powerpc/boot/dts/mpc8568mds.dts | 4 ---- arch/powerpc/boot/dts/mpc8641_hpcn.dts | 6 ------ arch/powerpc/boot/dts/mpc866ads.dts | 5 ----- arch/powerpc/boot/dts/mpc885ads.dts | 5 ----- arch/powerpc/boot/dts/prpmc2800.dts | 1 - 25 files changed, 4 insertions(+), 99 deletions(-)
arch/powerpc/boot/dts/holly.dts +0 -1
@@ -31,7 +31,6 @@ timebase-frequency = <2faf080>; clock-frequency = <23c34600>; bus-frequency = <bebc200>; - 32-bit; }; };
arch/powerpc/boot/dts/kuroboxHD.dts +0 -2
@@ -47,7 +47,6 @@ XXXX add flash parts, rtc, ?? soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; compatible = "mpc10x"; store-gathering = <0>; /* 0 == off, !0 == on */
@@ -101,7 +100,6 @@ XXXX add flash parts, rtc, ?? compatible = "chrp,open-pic"; interrupt-controller; reg = <80040000 40000>; - built-in; }; pci@fec00000 {
arch/powerpc/boot/dts/kuroboxHG.dts +0 -2
@@ -47,7 +47,6 @@ XXXX add flash parts, rtc, ?? soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; compatible = "mpc10x"; store-gathering = <0>; /* 0 == off, !0 == on */
@@ -101,7 +100,6 @@ XXXX add flash parts, rtc, ?? compatible = "chrp,open-pic"; interrupt-controller; reg = <80040000 40000>; - built-in; }; pci@fec00000 {
arch/powerpc/boot/dts/lite5200.dts +2 -5
@@ -37,7 +37,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; };
@@ -50,10 +49,9 @@ model = "fsl,mpc5200"; compatible = "mpc5200"; revision = ""; // from bootloader - #interrupt-cells = <3>; device_type = "soc"; - ranges = <0 f0000000 f0010000>; - reg = <f0000000 00010000>; + ranges = <0 f0000000 0000c000>; + reg = <f0000000 00000100>; bus-frequency = <0>; // from bootloader system-frequency = <0>; // from bootloader
@@ -69,7 +67,6 @@ device_type = "interrupt-controller"; compatible = "mpc5200-pic"; reg = <500 80>; - built-in; }; gpt@600 { // General Purpose Timer
arch/powerpc/boot/dts/lite5200b.dts +2 -5
@@ -37,7 +37,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; };
@@ -50,10 +49,9 @@ model = "fsl,mpc5200b"; compatible = "mpc5200"; revision = ""; // from bootloader - #interrupt-cells = <3>; device_type = "soc"; - ranges = <0 f0000000 f0010000>; - reg = <f0000000 00010000>; + ranges = <0 f0000000 0000c000>; + reg = <f0000000 00000100>; bus-frequency = <0>; // from bootloader system-frequency = <0>; // from bootloader
@@ -69,7 +67,6 @@ device_type = "interrupt-controller"; compatible = "mpc5200b-pic\0mpc5200-pic"; reg = <500 80>; - built-in; }; gpt@600 { // General Purpose Timer
arch/powerpc/boot/dts/mpc7448hpc2.dts +0 -4
@@ -31,7 +31,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot clock-frequency = <0>; // From U-Boot bus-frequency = <0>; // From U-Boot - 32-bit; }; };
@@ -44,7 +43,6 @@ tsi109@c0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "tsi-bridge"; compatible = "tsi109-bridge", "tsi108-bridge"; ranges = <00000000 c0000000 00010000>;
@@ -129,7 +127,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <7400 400>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian;
@@ -181,7 +178,6 @@ device_type = "pic-router"; #address-cells = <0>; #interrupt-cells = <2>; - built-in; big-endian; interrupts = <17 2>; interrupt-parent = <&mpic>;
arch/powerpc/boot/dts/mpc8272ads.dts +0 -5
@@ -29,7 +29,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; }; };
@@ -38,7 +37,6 @@ #interrupt-cells = <2>; interrupt-controller; reg = <f8200000 f8200004>; - built-in; device_type = "pci-pic"; };
@@ -56,7 +54,6 @@ soc8272@f0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <00000000 f0000000 00053000>; reg = <f0000000 10000>;
@@ -118,7 +115,6 @@ cpm@f0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "cpm"; model = "CPM2"; ranges = <00000000 00000000 20000>;
@@ -161,7 +157,6 @@ #interrupt-cells = <2>; interrupt-controller; reg = <10c00 80>; - built-in; device_type = "cpm-pic"; compatible = "CPM2"; };
arch/powerpc/boot/dts/mpc8313erdb.dts +0 -3
@@ -29,7 +29,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; };
@@ -41,7 +40,6 @@ soc8313@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00000200>;
@@ -207,7 +205,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; };
arch/powerpc/boot/dts/mpc832x_mds.dts +0 -4
@@ -29,7 +29,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; }; };
@@ -46,7 +45,6 @@ soc8323@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00000200>;
@@ -163,7 +161,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; };
@@ -333,7 +330,6 @@ #address-cells = <0>; #interrupt-cells = <1>; reg = <80 80>; - built-in; big-endian; interrupts = <20 8 21 8>; //high:32 low:33 interrupt-parent = < &ipic >;
arch/powerpc/boot/dts/mpc832x_rdb.dts +0 -4
@@ -29,7 +29,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; }; };
@@ -41,7 +40,6 @@ soc8323@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00000200>;
@@ -132,7 +130,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; };
@@ -292,7 +289,6 @@ #address-cells = <0>; #interrupt-cells = <1>; reg = <80 80>; - built-in; big-endian; interrupts = <20 8 21 8>; //high:32 low:33 interrupt-parent = <&pic>;
arch/powerpc/boot/dts/mpc8349emitx.dts +0 -3
@@ -28,7 +28,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; };
@@ -40,7 +39,6 @@ soc8349@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00000200>;
@@ -244,7 +242,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; };
arch/powerpc/boot/dts/mpc8349emitxgp.dts +0 -3
@@ -28,7 +28,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; };
@@ -40,7 +39,6 @@ soc8349@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00000200>;
@@ -176,7 +174,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; };
arch/powerpc/boot/dts/mpc834x_mds.dts +0 -3
@@ -29,7 +29,6 @@ timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader - 32-bit; }; };
@@ -46,7 +45,6 @@ soc8349@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00000200>;
@@ -332,7 +330,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; }; };
arch/powerpc/boot/dts/mpc836x_mds.dts +0 -4
@@ -34,7 +34,6 @@ timebase-frequency = <3EF1480>; bus-frequency = <FBC5200>; clock-frequency = <1F78A400>; - 32-bit; }; };
@@ -51,7 +50,6 @@ soc8360@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00000200>;
@@ -178,7 +176,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <700 100>; - built-in; device_type = "ipic"; };
@@ -364,7 +361,6 @@ #address-cells = <0>; #interrupt-cells = <1>; reg = <80 80>; - built-in; big-endian; interrupts = <20 8 21 8>; //high:32 low:33 interrupt-parent = < &ipic >;
arch/powerpc/boot/dts/mpc8540ads.dts +0 -3
@@ -30,7 +30,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot - 32-bit; }; };
@@ -42,7 +41,6 @@ soc8540@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00100000>; // CCSRBAR 1M
@@ -268,7 +266,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian;
arch/powerpc/boot/dts/mpc8541cds.dts +0 -6
@@ -30,7 +30,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot - 32-bit; }; };
@@ -42,7 +41,6 @@ soc8541@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00100000>; // CCSRBAR 1M
@@ -197,15 +195,12 @@ device_type = "pci"; i8259@19000 { - clock-frequency = <0>; interrupt-controller; device_type = "interrupt-controller"; reg = <19000 0 0 0 1>; #address-cells = <0>; #interrupt-cells = <2>; - built-in; compatible = "chrp,iic"; - big-endian; interrupts = <1>; interrupt-parent = <&pci1>; };
@@ -240,7 +235,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian;
arch/powerpc/boot/dts/mpc8544ds.dts +0 -5
@@ -30,7 +30,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; }; };
@@ -42,7 +41,6 @@ soc8544@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc";
@@ -295,12 +293,10 @@ reg = <1 20 2 1 a0 2 1 4d0 2>; - clock-frequency = <0>; interrupt-controller; device_type = "interrupt-controller"; #address-cells = <0>; #interrupt-cells = <2>; - built-in; compatible = "chrp,iic"; interrupts = <9 2>; interrupt-parent = <&mpic>;
@@ -350,7 +346,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian;
arch/powerpc/boot/dts/mpc8548cds.dts +0 -5
@@ -30,7 +30,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot - 32-bit; }; };
@@ -42,7 +41,6 @@ soc8548@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <00001000 e0001000 000ff000 80000000 80000000 10000000
@@ -318,7 +316,6 @@ interrupt-parent = <&i8259>; i8259: interrupt-controller@20 { - clock-frequency = <0>; interrupt-controller; device_type = "interrupt-controller"; reg = <1 20 2
@@ -326,7 +323,6 @@ 1 4d0 2>; #address-cells = <0>; #interrupt-cells = <2>; - built-in; compatible = "chrp,iic"; interrupts = <0 1>; interrupt-parent = <&mpic>;
@@ -394,7 +390,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian;
arch/powerpc/boot/dts/mpc8555cds.dts +0 -6
@@ -30,7 +30,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot - 32-bit; }; };
@@ -42,7 +41,6 @@ soc8555@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00100000>; // CCSRBAR 1M
@@ -197,15 +195,12 @@ device_type = "pci"; i8259@19000 { - clock-frequency = <0>; interrupt-controller; device_type = "interrupt-controller"; reg = <19000 0 0 0 1>; #address-cells = <0>; #interrupt-cells = <2>; - built-in; compatible = "chrp,iic"; - big-endian; interrupts = <1>; interrupt-parent = <&pci1>; };
@@ -240,7 +235,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian;
arch/powerpc/boot/dts/mpc8560ads.dts +0 -5
@@ -30,7 +30,6 @@ timebase-frequency = <04ead9a0>; bus-frequency = <13ab6680>; clock-frequency = <312c8040>; - 32-bit; }; };
@@ -42,7 +41,6 @@ soc8560@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00000200>;
@@ -227,14 +225,12 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; device_type = "open-pic"; }; cpm@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "cpm"; model = "CPM2"; ranges = <0 0 c0000>;
@@ -249,7 +245,6 @@ interrupts = <2e 2>; interrupt-parent = <&mpic>; reg = <90c00 80>; - built-in; device_type = "cpm-pic"; };
arch/powerpc/boot/dts/mpc8568mds.dts +0 -4
@@ -34,7 +34,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; }; };
@@ -51,7 +50,6 @@ soc8568@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; reg = <e0000000 00100000>;
@@ -258,7 +256,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian;
@@ -449,7 +446,6 @@ #address-cells = <0>; #interrupt-cells = <1>; reg = <80 80>; - built-in; big-endian; interrupts = <2e 2 2e 2>; //high:30 low:30 interrupt-parent = <&mpic>;
arch/powerpc/boot/dts/mpc8641_hpcn.dts +0 -6
@@ -30,7 +30,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot - 32-bit; }; PowerPC,8641@1 { device_type = "cpu";
@@ -42,7 +41,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot - 32-bit; }; };
@@ -54,7 +52,6 @@ soc8641@f8000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <00001000 f8001000 000ff000 80000000 80000000 20000000
@@ -291,12 +288,10 @@ reg = <1 20 2 1 a0 2 1 4d0 2>; - clock-frequency = <0>; interrupt-controller; device_type = "interrupt-controller"; #address-cells = <0>; #interrupt-cells = <2>; - built-in; compatible = "chrp,iic"; interrupts = <9 2>; interrupt-parent =
@@ -366,7 +361,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <40000 40000>; - built-in; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian;
arch/powerpc/boot/dts/mpc866ads.dts +0 -5
@@ -30,7 +30,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; interrupts = <f 2>; // decrementer interrupt interrupt-parent = <&Mpc8xx_pic>; };
@@ -44,7 +43,6 @@ soc866@ff000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 ff000000 00100000>; reg = <ff000000 00000200>;
@@ -78,7 +76,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <0 24>; - built-in; device_type = "mpc8xx-pic"; compatible = "CPM"; };
@@ -86,7 +83,6 @@ cpm@ff000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "cpm"; model = "CPM"; ranges = <0 0 4000>;
@@ -103,7 +99,6 @@ interrupts = <5 2 0 2>; interrupt-parent = <&Mpc8xx_pic>; reg = <930 20>; - built-in; device_type = "cpm-pic"; compatible = "CPM"; };
arch/powerpc/boot/dts/mpc885ads.dts +0 -5
@@ -30,7 +30,6 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - 32-bit; interrupts = <f 2>; // decrementer interrupt interrupt-parent = <&Mpc8xx_pic>; };
@@ -44,7 +43,6 @@ soc885@ff000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 ff000000 00100000>; reg = <ff000000 00000200>;
@@ -98,7 +96,6 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <0 24>; - built-in; device_type = "mpc8xx-pic"; compatible = "CPM"; };
@@ -117,7 +114,6 @@ cpm@ff000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "cpm"; model = "CPM"; ranges = <0 0 4000>;
@@ -134,7 +130,6 @@ interrupts = <5 2 0 2>; interrupt-parent = <&Mpc8xx_pic>; reg = <930 20>; - built-in; device_type = "cpm-pic"; compatible = "CPM"; };
arch/powerpc/boot/dts/prpmc2800.dts +0 -1
@@ -43,7 +43,6 @@ mv64x60@f1000000 { /* Marvell Discovery */ #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <1>; model = "mv64360"; /* Default */ compatible = "marvell,mv64x60"; clock-frequency = <7f28155>; /* 133.333333 MHz */
Signature · 1 line
1.5.2.4
PATCH 3/5 Move PCI nodes to be sibilings with SOC nodes
Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well.
Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB.
Signed-off-by Kumar Gala <[email protected]>
--- arch/powerpc/boot/dts/lite5200.dts | 42 ++-- arch/powerpc/boot/dts/lite5200b.dts | 52 ++-- arch/powerpc/boot/dts/mpc8313erdb.dts | 60 +++--- arch/powerpc/boot/dts/mpc832x_mds.dts | 118 +++++----- arch/powerpc/boot/dts/mpc832x_rdb.dts | 66 +++--- arch/powerpc/boot/dts/mpc8349emitx.dts | 95 ++++---- arch/powerpc/boot/dts/mpc8349emitxgp.dts | 44 ++-- arch/powerpc/boot/dts/mpc834x_mds.dts | 240 +++++++++--------- arch/powerpc/boot/dts/mpc836x_mds.dts | 119 +++++----- arch/powerpc/boot/dts/mpc8540ads.dts | 172 +++++++------- arch/powerpc/boot/dts/mpc8541cds.dts | 190 +++++++------- arch/powerpc/boot/dts/mpc8544ds.dts | 372 +++++++++++++++------------- arch/powerpc/boot/dts/mpc8548cds.dts | 399 +++++++++++++++--------------- arch/powerpc/boot/dts/mpc8555cds.dts | 192 +++++++------- arch/powerpc/boot/dts/mpc8560ads.dts | 180 +++++++------- arch/powerpc/boot/dts/mpc8641_hpcn.dts | 269 +++++++++++---------- 16 files changed, 1325 insertions(+), 1285 deletions(-)
arch/powerpc/boot/dts/lite5200.dts +21 -21
@@ -182,27 +182,6 @@ interrupt-parent = <&mpc5200_pic>; }; - pci@0d00 { - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - compatible = "mpc5200-pci"; - reg = <d00 100>; - interrupt-map-mask = <f800 0 0 7>; - interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 - c000 0 0 2 &mpc5200_pic 0 0 3 - c000 0 0 3 &mpc5200_pic 0 0 3 - c000 0 0 4 &mpc5200_pic 0 0 3>; - clock-frequency = <0>; // From boot loader - interrupts = <2 8 0 2 9 0 2 a 0>; - interrupt-parent = <&mpc5200_pic>; - bus-range = <0 0>; - ranges = <42000000 0 80000000 80000000 0 20000000 - 02000000 0 a0000000 a0000000 0 10000000 - 01000000 0 00000000 b0000000 0 01000000>; - }; - spi@f00 { device_type = "spi"; compatible = "mpc5200-spi";
@@ -337,4 +316,25 @@ reg = <8000 4000>; }; }; + + pci@f0000d00 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + compatible = "mpc5200-pci"; + reg = <f0000d00 100>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 + c000 0 0 2 &mpc5200_pic 0 0 3 + c000 0 0 3 &mpc5200_pic 0 0 3 + c000 0 0 4 &mpc5200_pic 0 0 3>; + clock-frequency = <0>; // From boot loader + interrupts = <2 8 0 2 9 0 2 a 0>; + interrupt-parent = <&mpc5200_pic>; + bus-range = <0 0>; + ranges = <42000000 0 80000000 80000000 0 20000000 + 02000000 0 a0000000 a0000000 0 10000000 + 01000000 0 00000000 b0000000 0 01000000>; + }; };
arch/powerpc/boot/dts/lite5200b.dts +26 -26
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arch/powerpc/boot/dts/mpc8313erdb.dts +30 -30
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arch/powerpc/boot/dts/mpc832x_mds.dts +59 -59
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arch/powerpc/boot/dts/mpc832x_rdb.dts +33 -33
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arch/powerpc/boot/dts/mpc8349emitx.dts +49 -46
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arch/powerpc/boot/dts/mpc8349emitxgp.dts +22 -22
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arch/powerpc/boot/dts/mpc834x_mds.dts +120 -120
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arch/powerpc/boot/dts/mpc836x_mds.dts +59 -60
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arch/powerpc/boot/dts/mpc8540ads.dts +86 -86
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arch/powerpc/boot/dts/mpc8541cds.dts +95 -95
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arch/powerpc/boot/dts/mpc8544ds.dts +196 -176
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arch/powerpc/boot/dts/mpc8548cds.dts +203 -196
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arch/powerpc/boot/dts/mpc8555cds.dts +97 -95
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arch/powerpc/boot/dts/mpc8560ads.dts +90 -90
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arch/powerpc/boot/dts/mpc8641_hpcn.dts +139 -130
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Signature · 1 line
1.5.2.4
PATCH 4/5 83xx: Removed PCI exclude of PHB
Now that the generic code doesn't assign resources for Freescale PHBs we dont have to explicitly exclude it.
Signed-off-by Kumar Gala <[email protected]>
--- arch/powerpc/platforms/83xx/mpc8313_rdb.c | 2 -- arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 - arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 -- arch/powerpc/platforms/83xx/mpc834x_itx.c | 2 -- arch/powerpc/platforms/83xx/mpc834x_mds.c | 2 -- arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 - arch/powerpc/platforms/83xx/mpc83xx.h | 2 -- arch/powerpc/platforms/83xx/pci.c | 7 ------- 8 files changed, 0 insertions(+), 19 deletions(-)
arch/powerpc/platforms/83xx/mpc8313_rdb.c +0 -2
@@ -45,8 +45,6 @@ static void __init mpc8313_rdb_setup_arch(void)#ifdef CONFIG_PCI for (np =NULL ; (np =of_find_node_by_type (np,"pci" )) !=NULL ;)mpc83xx_add_bridge (np); - - ppc_md.pci_exclude_device = mpc83xx_exclude_device;#endif mpc831x_usb_cfg (); }
arch/powerpc/platforms/83xx/mpc832x_mds.c +0 -1
@@ -75,7 +75,6 @@ static void __init mpc832x_sys_setup_arch(void)#ifdef CONFIG_PCI for (np =NULL ; (np =of_find_node_by_type (np,"pci" )) !=NULL ;)mpc83xx_add_bridge (np); - ppc_md.pci_exclude_device = mpc83xx_exclude_device;#endif #ifdef CONFIG_QUICC_ENGINE
arch/powerpc/platforms/83xx/mpc832x_rdb.c +0 -2
@@ -49,8 +49,6 @@ static void __init mpc832x_rdb_setup_arch(void)#ifdef CONFIG_PCI for (np =NULL ; (np =of_find_node_by_type (np,"pci" )) !=NULL ;)mpc83xx_add_bridge (np); - - ppc_md.pci_exclude_device = mpc83xx_exclude_device;#endif #ifdef CONFIG_QUICC_ENGINE
arch/powerpc/platforms/83xx/mpc834x_itx.c +0 -2
@@ -54,8 +54,6 @@ static void __init mpc834x_itx_setup_arch(void)#ifdef CONFIG_PCI for (np =NULL ; (np =of_find_node_by_type (np,"pci" )) !=NULL ;)mpc83xx_add_bridge (np); - - ppc_md.pci_exclude_device = mpc83xx_exclude_device;#endif mpc834x_usb_cfg ();
arch/powerpc/platforms/83xx/mpc834x_mds.c +0 -2
@@ -85,8 +85,6 @@ static void __init mpc834x_mds_setup_arch(void)#ifdef CONFIG_PCI for (np =NULL ; (np =of_find_node_by_type (np,"pci" )) !=NULL ;)mpc83xx_add_bridge (np); - - ppc_md.pci_exclude_device = mpc83xx_exclude_device;#endif mpc834xemds_usb_cfg ();
arch/powerpc/platforms/83xx/mpc836x_mds.c +0 -1
@@ -81,7 +81,6 @@ static void __init mpc836x_mds_setup_arch(void)#ifdef CONFIG_PCI for (np =NULL ; (np =of_find_node_by_type (np,"pci" )) !=NULL ;)mpc83xx_add_bridge (np); - ppc_md.pci_exclude_device = mpc83xx_exclude_device;#endif #ifdef CONFIG_QUICC_ENGINE
arch/powerpc/platforms/83xx/mpc83xx.h +0 -2
@@ -49,8 +49,6 @@*/ extern int mpc83xx_add_bridge (struct device_node *dev); -extern int mpc83xx_exclude_device (struct pci_controller *hose, -u_char bus,u_char devfn);extern void mpc83xx_restart (char *cmd);extern long mpc83xx_time_init (void );extern int mpc834x_usb_cfg (void );
arch/powerpc/platforms/83xx/pci.c +0 -7
@@ -33,13 +33,6 @@ #define DBG(x...)#endif -int mpc83xx_exclude_device (struct pci_controller *hose,u_char bus,u_char devfn) -{ -if ((bus == hose->first_busno) &&PCI_SLOT (devfn) ==0 ) -return PCIBIOS_DEVICE_NOT_FOUND ; -return PCIBIOS_SUCCESSFUL ; -} -int __init mpc83xx_add_bridge (struct device_node *dev) {int len;
Signature · 1 line
1.5.2.4
PATCH 5/5 Add cpu feature for SPE handling
Make it so that SPE support can be determined at runtime. This is similiar to how we handle AltiVec. This allows us to have SPE support built in and work on processors with and without SPE.
Signed-off-by Kumar Gala <[email protected]>
--- arch/powerpc/kernel/cputable.c | 23 +++++++---------------- arch/powerpc/kernel/entry_32.S | 4 ++++ arch/powerpc/kernel/process.c | 15 +++++++++++---- arch/powerpc/kernel/ptrace.c | 6 ++---- include/asm-powerpc/cputable.h | 26 ++++++++++++++++++++++---- 5 files changed, 46 insertions(+), 28 deletions(-)
arch/powerpc/kernel/cputable.c +7 -16
@@ -68,15 +68,6 @@ extern void __restore_cpu_ppc970(void);#define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ PPC_FEATURE_BOOKE) -/* We only set the spe features if the kernel was compiled with -* spe support -*/ -#ifdef CONFIG_SPE -#define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE -#else -#define PPC_FEATURE_SPE_COMP 0 -#endif - static struct cpu_spec cpu_specs[] = { #ifdef CONFIG_PPC64 { /* Power3 */
@@ -1261,8 +1252,8 @@ static struct cpu_spec cpu_specs[] = {/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ .cpu_features = CPU_FTRS_E200, .cpu_user_features =COMMON_USER_BOOKE | -PPC_FEATURE_SPE_COMP | -PPC_FEATURE_HAS_EFP_SINGLE | +PPC_FEATURE_HAS_SPE_COMP | +PPC_FEATURE_HAS_EFP_SINGLE_COMP | PPC_FEATURE_UNIFIED_CACHE, .dcache_bsize = 32, .platform = "ppc5554",
@@ -1274,8 +1265,8 @@ static struct cpu_spec cpu_specs[] = {/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ .cpu_features = CPU_FTRS_E500, .cpu_user_features =COMMON_USER_BOOKE | -PPC_FEATURE_SPE_COMP | - PPC_FEATURE_HAS_EFP_SINGLE, +PPC_FEATURE_HAS_SPE_COMP | + PPC_FEATURE_HAS_EFP_SINGLE_COMP, .icache_bsize = 32, .dcache_bsize = 32, .num_pmcs = 4,
@@ -1290,9 +1281,9 @@ static struct cpu_spec cpu_specs[] = {/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ .cpu_features = CPU_FTRS_E500_2, .cpu_user_features =COMMON_USER_BOOKE | -PPC_FEATURE_SPE_COMP | -PPC_FEATURE_HAS_EFP_SINGLE | - PPC_FEATURE_HAS_EFP_DOUBLE, +PPC_FEATURE_HAS_SPE_COMP | +PPC_FEATURE_HAS_EFP_SINGLE_COMP | + PPC_FEATURE_HAS_EFP_DOUBLE_COMP, .icache_bsize = 32, .dcache_bsize = 32, .num_pmcs = 4,
arch/powerpc/kernel/entry_32.S +4 -0
@@ -504,9 +504,11 @@ BEGIN_FTR_SECTION END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) #endif /* CONFIG_ALTIVEC */ #ifdef CONFIG_SPE +BEGIN_FTR_SECTION oris r0,r0,MSR_SPE@h /* Disable SPE */ mfspr r12,SPRN_SPEFSCR /* save spefscr register value */ stw r12,THREAD+THREAD_SPEFSCR(r2) +END_FTR_SECTION_IFSET(CPU_FTR_SPE) #endif /* CONFIG_SPE */ and. r0,r0,r11 /* FP or altivec or SPE enabled? */ beq+ 1f
@@ -542,8 +544,10 @@ BEGIN_FTR_SECTION END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) #endif /* CONFIG_ALTIVEC */ #ifdef CONFIG_SPE +BEGIN_FTR_SECTION lwz r0,THREAD+THREAD_SPEFSCR(r2) mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */ +END_FTR_SECTION_IFSET(CPU_FTR_SPE) #endif /* CONFIG_SPE */ lwz r0,_CCR(r1)
arch/powerpc/kernel/process.c +11 -4
@@ -669,9 +669,13 @@ int set_fpexc_mode(struct task_struct *tsk, unsigned int val)* mode (asyn, precise, disabled) for 'Classic' FP. */ if (val &PR_FP_EXC_SW_ENABLE ) {#ifdef CONFIG_SPE - tsk->thread.fpexc_mode = val & - (PR_FP_EXC_SW_ENABLE |PR_FP_ALL_EXCEPT ); -return 0 ; +if (cpu_has_feature (CPU_FTR_SPE )) { + tsk->thread.fpexc_mode = val & + (PR_FP_EXC_SW_ENABLE |PR_FP_ALL_EXCEPT ); +return 0 ; + }else { +return -EINVAL ; + }#else return -EINVAL ;#endif
@@ -697,7 +701,10 @@ int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)#ifdef CONFIG_SPE - val = tsk->thread.fpexc_mode; +if (cpu_has_feature (CPU_FTR_SPE )) + val = tsk->thread.fpexc_mode; +else +return -EINVAL ;#else return -EINVAL ;#endif
arch/powerpc/kernel/ptrace.c +2 -4
@@ -576,8 +576,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)#ifdef CONFIG_SPE case PTRACE_GETEVRREGS :/* Get the child spe register state. */ -if (child->thread.regs->msr &MSR_SPE ) -giveup_spe (child); +flush_spe_to_thread (child); ret =get_evrregs ((unsigned long __user *)data, child);break ;
@@ -585,8 +584,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)/* Set the child spe register state. */ /* this is to clear the MSR_SPE bit to force a reload * of register state from memory */ -if (child->thread.regs->msr &MSR_SPE ) -giveup_spe (child); +flush_spe_to_thread (child); ret =set_evrregs (child, (unsigned long __user *)data);break ;#endif
include/asm-powerpc/cputable.h +22 -4
@@ -136,6 +136,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) +#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)/* * Add the 64-bit processor unique features in the top half of the word;
@@ -180,6 +181,21 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,#define PPC_FEATURE_HAS_ALTIVEC_COMP 0#endif +/* We only set the spe features if the kernel was compiled with spe +* support +*/ +#ifdef CONFIG_SPE +#define CPU_FTR_SPE_COMP CPU_FTR_SPE +#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE +#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE +#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE +#else +#define CPU_FTR_SPE_COMP 0 +#define PPC_FEATURE_HAS_SPE_COMP 0 +#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 +#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 +#endif +/* We need to mark all pages as being coherent if we're SMP or we * have a 74[45]x and an MPC107 host bridge. Also 83xx requires * it for PCI "streaming/prefetch" to work properly.
@@ -310,10 +326,12 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,#define CPU_FTRS_8XX (CPU_FTR_USE_TB)#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) -#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ - CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) -#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) -#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | \ +#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ + CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ + CPU_FTR_UNIFIED_ID_CACHE) +#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ + CPU_FTR_NODSISRALIGN) +#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Signature · 1 line
1.5.2.4
Re: [PATCH 2/5] [POWERPC] DTS cleanup
In reply to Kumar GalaQuoted 8 lines
Removed the following cruft from .dts files:
* 32-bit in cpu node -- doesn't exist in any spec and not used by kernel
* removed built-in (chrp legacy)
* Removed #interrupt-cells in places they don't need to be set
* Fixed ranges on lite5200*
* Removed clock-frequency from i8259 pic node, not sure where this came fromSigned-off-by Kumar Gala <[email protected]>
You also removed "big-endian" from an 8259 node, please put that in the commit message too.
Segher