powerpc: Add IPIC MSI support

PATCH In review Li Li 6 participants 9 messages Dec 4, 2007 – Dec 14, 2007

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Device tree bindings PowerPC Linux for PowerPC embedded PPC8XX and PPC83XX

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Li Li

author

2007-12-04 10:49 UTC #0 lore raw

PATCH 2/2 powerpc: Add IPIC MSI support

Modified based on discussion on list.

1. Adopt virq_to_hw routine
2. Correct a legacy bug

Implements the IPIC MSI as two level interrupt controller.

Signed-off-by Tony Li <[email protected]>

---
 arch/powerpc/boot/dts/mpc8377_mds.dts     |   14 ++
 arch/powerpc/boot/dts/mpc8378_mds.dts     |   14 ++
 arch/powerpc/boot/dts/mpc8379_mds.dts     |   14 ++
 arch/powerpc/platforms/83xx/Kconfig       |    6 +
 arch/powerpc/platforms/83xx/mpc837x_mds.c |    7 +
 arch/powerpc/sysdev/Makefile              |    1 +
 arch/powerpc/sysdev/ipic_msi.c            |  359 +++++++++++++++++++++++++++++
 include/asm-powerpc/ipic_msi.h            |   66 ++++++
 8 files changed, 481 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/sysdev/ipic_msi.c
 create mode 100644 include/asm-powerpc/ipic_msi.h

arch/powerpc/boot/dts/mpc8377_mds.dts +14 -0

index 8f54349..c11e529 100644
@@ -210,6 +210,20 @@
 			#interrupt-cells = <2>;
 			reg = <700 100>;
 		};
+
+		ipic-msi@7c0 {
+			compatible = "fsl,ipic-msi";
+			reg = <7c0 40>;
+			interrupts = < 43 8
+				       4  8
+				       51 8
+				       52 8
+				       56 8
+				       57 8
+				       58 8
+				       59 8 >;
+			interrupt-parent = < &ipic >;
+		};
 	};
 
 	pci@e0008500 {

arch/powerpc/boot/dts/mpc8378_mds.dts +14 -0

index e09b0c5..7b0bf1b 100644
@@ -192,6 +192,20 @@
 			#interrupt-cells = <2>;
 			reg = <700 100>;
 		};
+
+		ipic-msi@7c0 {
+			compatible = "fsl,ipic-msi";
+			reg = <7c0 40>;
+			interrupts = < 43 8
+				       4  8
+				       51 8
+				       52 8
+				       56 8
+				       57 8
+				       58 8
+				       59 8 >;
+			interrupt-parent = < &ipic >;
+		};
 	};
 
 	pci@e0008500 {

arch/powerpc/boot/dts/mpc8379_mds.dts +14 -0

index cdb4426..9fe4bd2 100644
@@ -236,6 +236,20 @@
 			#interrupt-cells = <2>;
 			reg = <700 100>;
 		};
+
+		ipic-msi@7c0 {
+			compatible = "fsl,ipic-msi";
+			reg = <7c0 40>;
+			interrupts = < 43 8
+				       4  8
+				       51 8
+				       52 8
+				       56 8
+				       57 8
+				       58 8
+				       59 8 >;
+			interrupt-parent = < &ipic >;
+		};
 	};
 
 	pci@e0008500 {

arch/powerpc/platforms/83xx/Kconfig +6 -0

index 00154c5..4c51f78 100644
@@ -88,6 +88,12 @@ config PPC_MPC837x
 	select FSL_SERDES
 	default y if MPC837x_MDS
 
+config IPIC_MSI
+	bool
+	depends on PCI_MSI
+	default y if PPC_MPC837x
+	default n
+
 config PPC_MPC83XX_PCIE
 	bool "MPC837X PCI Express support"
 	depends on PCIEPORTBUS && PPC_MPC837x

arch/powerpc/platforms/83xx/mpc837x_mds.c +7 -0

index b1d3570..f68a7e9 100644
@@ -17,6 +17,7 @@
 
 #include <asm/time.h>
 #include <asm/ipic.h>
+#include <asm/ipic_msi.h>
 #include <asm/udbg.h>
 #include <asm/prom.h>

@@ -94,6 +95,12 @@ static void __init mpc837x_mds_init_IRQ(void)
 	 * in case the boot rom changed something on us.
 	 */
 	ipic_set_default_priority();
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ipic-msi");
+	if (!np)
+		return;
+
+	ipic_msi_init(np, ipic_msi_cascade);
 }
 
 /*

arch/powerpc/sysdev/Makefile +1 -0

index 99a77d7..5946b6a 100644
@@ -25,6 +25,7 @@ ifeq ($(CONFIG_PPC_MERGE),y)
 obj-$(CONFIG_PPC_INDIRECT_PCI)	+= indirect_pci.o
 obj-$(CONFIG_PPC_I8259)		+= i8259.o
 obj-$(CONFIG_PPC_83xx)		+= ipic.o
+obj-$(CONFIG_IPIC_MSI)		+= ipic_msi.o
 obj-$(CONFIG_4xx)		+= uic.o
 obj-$(CONFIG_XILINX_VIRTEX)	+= xilinx_intc.o
 endif

arch/powerpc/sysdev/ipic_msi.c new file +359 -0

359 lines not on this page · raw message

include/asm-powerpc/ipic_msi.h new file +66 -0

66 lines not on this page · raw message

Signature · 1 line

1.5.2

Li Yang

2007-12-04 10:57 UTC #1 lore raw

Quoted 4 lines

-----Original Message-----
From: [email protected]=20 [mailto:[email protected]]=20 On Behalf Of Li Tony

Quoted 8 lines

Sent: Tuesday, December 04, 2007 6:39 PM
To: Gala Kumar; Phillips Kim; [email protected]; linuxppc-dev
Subject: [PATCH 2/2] powerpc: Add IPIC MSI support
=20
Modified based on discussion on list.
=20
1. Adopt virq_to_hw routine
2. Correct a legacy bug

The above lines should probably be placed after the "---" below.

Quoted 5 lines

=20
Implements the IPIC MSI as two level interrupt controller. =20
Signed-off-by Tony Li <[email protected]>
---

- Leo

Michael Ellerman

Acked-by

2007-12-04 11:59 UTC #2 lore raw

Quoted 8 lines · Li Yang

Quoted 8 lines
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Li Tony
Sent: Tuesday, December 04, 2007 6:39 PM
To: Gala Kumar; Phillips Kim; [email protected]; linuxppc-dev
Subject: [PATCH 2/2] powerpc: Add IPIC MSI support

Quoted 11 lines

Quoted 4 lines
Modified based on discussion on list.
1. Adopt virq_to_hw routine
2. Correct a legacy bug
The above lines should probably be placed after the "---" below.
Quoted 4 lines
Implements the IPIC MSI as two level interrupt controller.
Signed-off-by Tony Li <[email protected]>

The change log is a bit short in general for my liking.

Still, MSI bits ..

Acked-by Michael Ellerman <[email protected]>

cheers

Signature · 8 lines

Michael Ellerman
OzLabs, IBM Australia Development Lab

wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)

We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person

Kumar Gala

2007-12-14 05:45 UTC #3 lore raw

In reply to Li Li

Quoted 8 lines · Li Li

Modified based on discussion on list.
1. Adopt virq_to_hw routine
2. Correct a legacy bug
Implements the IPIC MSI as two level interrupt controller.
Signed-off-by Tony Li <[email protected]>

Tony, have you looked at the 85xx/86xx PCIe MSI mechanism? The 2nd level PIC handling seems like its pretty similar between IPIC and MPIC. Would like to see if we could somehow make the code common for to handle MSIs from both?

- k

Li Tony

2007-12-14 08:47 UTC #4 lore raw

=20
Hi,

I think it is possible to make common code to support both IPIC and = MPIC.
Currently, the MPIC has already implemented MSI which is different from = IPIC and embedded into the mpic code body.
If want to unifiy MSI code, we need to remove the current MPIC MSI = implementation.

Micheal, what is your opinion ??

Jin is working on 86xx msi now.=20

Tony

Quoted 26 lines

-----Original Message-----
From: Kumar Gala [mailto:[email protected]]=20
Sent: 2007=C4=EA12=D4=C214=C8=D5 13:45
To: Li Tony
Cc: Phillips Kim; [email protected]; linuxppc-dev
Subject: Re: [PATCH 2/2] powerpc: Add IPIC MSI support =20
=20
On Dec 4, 2007, at 4:39 AM, Li Li wrote:
=20
Quoted 8 lines
Modified based on discussion on list.
1. Adopt virq_to_hw routine
2. Correct a legacy bug
Implements the IPIC MSI as two level interrupt controller.
Signed-off-by Tony Li <[email protected]>
=20
Tony, have you looked at the 85xx/86xx PCIe MSI mechanism? =20 The 2nd level PIC handling seems like its pretty similar=20 between IPIC and MPIC. Would like to see if we could somehow=20 make the code common for to handle MSIs from both?
=20
- k
=20

Kumar Gala

2007-12-14 08:52 UTC #5 lore raw

Quoted 10 lines · Li Tony

Hi,
I think it is possible to make common code to support both IPIC and =20=
MPIC.
Currently, the MPIC has already implemented MSI which is different =20 from IPIC and embedded into the mpic code body.
If want to unifiy MSI code, we need to remove the current MPIC MSI =20 implementation.

The MPIC is going to have to support several MSI styles (IBM/U3, =20 PaSemi, and FSL) since we all seem to handle it differently.

Quoted 3 lines

Micheal, what is your opinion ??
Jin is working on 86xx msi now.

What PCIe cards are you using to test MSIs?

- k

Quoted 26 lines

Quoted 26 lines
-----Original Message-----
From: Kumar Gala [mailto:[email protected]]
Sent: 2007=C4=EA12=D4=C214=C8=D5 13:45
To: Li Tony
Cc: Phillips Kim; [email protected]; linuxppc-dev
Subject: Re: [PATCH 2/2] powerpc: Add IPIC MSI support
Quoted 8 lines · Li Li
Modified based on discussion on list.
1. Adopt virq_to_hw routine
2. Correct a legacy bug
Implements the IPIC MSI as two level interrupt controller.
Signed-off-by Tony Li <[email protected]>
Tony, have you looked at the 85xx/86xx PCIe MSI mechanism? The 2nd level PIC handling seems like its pretty similar between IPIC and MPIC. Would like to see if we could somehow make the code common for to handle MSIs from both?
- k

Li Li

author

2007-12-14 09:26 UTC #6 lore raw

Quoted 13 lines · Kumar Gala

=20
On Dec 14, 2007, at 2:47 AM, Li Tony wrote:
=20
Quoted 4 lines
=20
Hi,=20
=20
I think it is possible to make common code to support both IPIC
and =20
Quoted 5 lines
MPIC.=20
Currently, the MPIC has already implemented MSI which is different =20 from IPIC and embedded into the mpic code body.=20
If want to unifiy MSI code, we need to remove the current MPIC MSI =20 implementation.

Quoted 4 lines

=20
The MPIC is going to have to support several MSI styles (IBM/U3, =20 PaSemi, and FSL) since we all seem to handle it differently. =20

Yes, you are right. I misunderstands here.

Quoted 6 lines

Quoted 3 lines
Micheal, what is your opinion ??=20
=20
Jin is working on 86xx msi now.
=20
What PCIe cards are you using to test MSIs?
=20

Intel PRO1000 PCIE network card and SysKonnect card.

Quoted 29 lines

- k
=20
Quoted 18 lines
Quoted 18 lines
-----Original Message-----=20
From: Kumar Gala [mailto:[email protected]]=20
Sent: 2007=E5=B9=B412=E6=9C=8814=E6=97=A5 13:45=20
To: Li Tony=20
Cc: Phillips Kim; [email protected]; linuxppc-dev=20
Subject: Re: [PATCH 2/2] powerpc: Add IPIC MSI support=20 =20
=20
On Dec 4, 2007, at 4:39 AM, Li Li wrote:=20
=20
Quoted 8 lines
Modified based on discussion on list.=20
=20
1. Adopt virq_to_hw routine=20
2. Correct a legacy bug=20
=20
Implements the IPIC MSI as two level interrupt controller.=20 =20
Signed-off-by Tony Li <[email protected]>=20
Quoted 8 lines
Quoted 8 lines
=20
Tony, have you looked at the 85xx/86xx PCIe MSI mechanism?=20 The 2nd level PIC handling seems like its pretty similar=20 between IPIC and MPIC. Would like to see if we could somehow=20 make the code common for to handle MSIs from both?=20 =20
- k=20
=20

Jin Zhengxiong

2007-12-14 09:39 UTC #7 lore raw

In reply to Kumar Gala

=20

Quoted 20 lines

-----Original Message-----
From: Kumar Gala [mailto:[email protected]]=20
Sent: Friday, December 14, 2007 4:52 PM
To: Li Tony
Cc: Phillips Kim; [email protected]; linuxppc-dev list;=20 Jin Zhengxiong; Olof Johansson
Subject: Re: [PATCH 2/2] powerpc: Add IPIC MSI support =20
=20
On Dec 14, 2007, at 2:47 AM, Li Tony wrote:
=20
Quoted 9 lines
Hi,
I think it is possible to make common code to support both IPIC and=20 MPIC.
Currently, the MPIC has already implemented MSI which is different=20 from IPIC and embedded into the mpic code body.
If want to unifiy MSI code, we need to remove the current MPIC MSI=20 implementation.

Quoted 3 lines

=20
The MPIC is going to have to support several MSI styles=20 (IBM/U3, PaSemi, and FSL) since we all seem to handle it differently.

I enabled the MSI interrrupts on 85xx/86xx board similar to the IBM/U3 = board.
Did not enable another host as on 83xx board. Put the 256 MSI interrupts = after the=20
256 system interrupts and use the same mpic host. This can work and can = reuse most
of the mpic_msi codes. but since the host_map of MSI is something = different with MPIC.
I also think it's good idea to make a 2 level PIC handling mechanism for = MSI on 85xx/86xx board and=20
common the code to support for both IPIC and MPIC for fsl board.

=20

Quoted 5 lines

Quoted 3 lines
Micheal, what is your opinion ??
Jin is working on 86xx msi now.
=20
What PCIe cards are you using to test MSIs?

I used a SysKonnect 1000M PCIe ether card and the SATA driver to test = the MSI on 85xx/86xx board.

Best Regards,
Jason

Quoted 32 lines

- k
=20
Quoted 15 lines
Quoted 15 lines
-----Original Message-----
From: Kumar Gala [mailto:[email protected]]
Sent: 2007=C4=EA12=D4=C214=C8=D5 13:45
To: Li Tony
Cc: Phillips Kim; [email protected]; linuxppc-dev
Subject: Re: [PATCH 2/2] powerpc: Add IPIC MSI support
Quoted 5 lines · Li Li
Modified based on discussion on list.
1. Adopt virq_to_hw routine
2. Correct a legacy bug
Quoted 6 lines
Quoted 6 lines
Quoted 3 lines
Implements the IPIC MSI as two level interrupt controller.
Signed-off-by Tony Li <[email protected]>
Tony, have you looked at the 85xx/86xx PCIe MSI mechanism? The 2nd level PIC handling seems like its pretty similar=20
between IPIC=20
Quoted 1 line
Quoted 1 line
and MPIC. Would like to see if we could somehow make the=20
code common=20
Quoted 4 lines
Quoted 4 lines
for to handle MSIs from both?
- k
=20
=20

Michael Ellerman

2007-12-14 09:40 UTC #8 lore raw

In reply to Kumar Gala

Quoted 12 lines · Kumar Gala

Quoted 9 lines · Li Tony
Hi,
I think it is possible to make common code to support both IPIC and MPIC.
Currently, the MPIC has already implemented MSI which is different from IPIC and embedded into the mpic code body.
If want to unifiy MSI code, we need to remove the current MPIC MSI implementation.

Quoted 2 lines

The MPIC is going to have to support several MSI styles (IBM/U3, PaSemi, and FSL) since we all seem to handle it differently.

I haven't really looked at the similarities or differences, but I think Kumar is right, MPIC is going to have to (and already does) support different styles.

If there's some commonality that can be shared I'm all ears, patches welcome ;)

cheers

Signature · 8 lines

Michael Ellerman
OzLabs, IBM Australia Development Lab

wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)

We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person