ucc_uart: add support for Freescale QUICCEngine UART
Subsystems (3)
PATCH v3 1/1 ucc_uart: add support for Freescale QUICCEngine UART
Add support for UART serial ports using a Freescale QUICC Engine (found on some MPC83xx and MPC85xx SOCs).
Updated booting-without-of.txt to define new properties for a QE UART node, and a new node definition that describes uploaded QE firmware.
Because of a silicon bug in some QE-enabled SOCs (e.g. 8323 and 8360), a new microcode is required. This microcode implements UART via a work-around, hence it's called "Soft-UART". This driver can use the QE firmware upload feature to upload the correct microcode to the QE.
Signed-off-by Timur Tabi <[email protected]>
---
Updated w.r.t. comments from Anton V.
This patch is for Kumar's for-2.6.25 branch, and it applies on top of my previous patches, "qe: add ability to upload QE firmware" and "qe: add function qe_clock_source()".
Documentation/powerpc/booting-without-of.txt | 9 +- arch/powerpc/boot/dts/mpc832x_mds.dts | 50 + arch/powerpc/sysdev/qe_lib/Kconfig | 2 +- arch/powerpc/sysdev/qe_lib/ucc_slow.c | 10 +- drivers/serial/Kconfig | 10 + drivers/serial/Makefile | 1 + drivers/serial/ucc_uart.c | 1507 ++++++++++++++++++++++++++ 7 files changed, 1586 insertions(+), 3 deletions(-) create mode 100644 drivers/serial/ucc_uart.c
Documentation/powerpc/booting-without-of.txt +8 -1
@@ -1616,7 +1616,7 @@ platforms are moved over to use the flattened-device-tree model. Required properties: - device_type : should be "network", "hldc", "uart", "transparent" - "bisync" or "atm". + "bisync", "atm", or "serial". - compatible : could be "ucc_geth" or "fsl_atm" and so on. - model : should be "UCC". - device-id : the ucc number(1-8), corresponding to UCCx in UM.
@@ -1629,6 +1629,13 @@ platforms are moved over to use the flattened-device-tree model. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. - pio-handle : The phandle for the Parallel I/O port configuration. + - port-number : for UART drivers, the port number to use, between 0 and 3. + This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0. + The port number is added to the minor number of the device. Unlike the + CPM UART driver, the port-number is required for the QE UART driver. + - soft-uart : for UART drivers, if specified this means the QE UART device + driver should use "Soft-UART" mode, which is needed on some SOCs that have + broken UART hardware. Soft-UART is provided via a microcode upload. - rx-clock-name: the UCC receive clock source "none": clock source is disabled "brg1" through "brg16": clock source is BRG1-BRG16, respectively
arch/powerpc/boot/dts/mpc832x_mds.dts +50 -0
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arch/powerpc/sysdev/qe_lib/Kconfig +1 -1
@@ -4,7 +4,7 @@ config UCC_SLOW bool - default n + default y if SERIAL_QE help This option provides qe_lib support to UCC slow protocols: UART, BISYNC, QMC
arch/powerpc/sysdev/qe_lib/ucc_slow.c +9 -1
@@ -19,6 +19,7 @@#include <linux/stddef.h> #include <linux/interrupt.h> #include <linux/err.h> +#include <linux/module.h> #include <asm/io.h> #include <asm/immap_qe.h>
@@ -41,6 +42,7 @@ u32 ucc_slow_get_qe_cr_subblock(int uccs_num)default :return QE_CR_SUBBLOCK_INVALID ; } } +EXPORT_SYMBOL (ucc_slow_get_qe_cr_subblock);void ucc_slow_poll_transmitter_now (struct ucc_slow_private * uccs) {
@@ -56,6 +58,7 @@ void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)qe_issue_cmd (QE_GRACEFUL_STOP_TX , id,QE_CR_PROTOCOL_UNSPECIFIED ,0 ); } +EXPORT_SYMBOL (ucc_slow_graceful_stop_tx);void ucc_slow_stop_tx (struct ucc_slow_private * uccs) {
@@ -65,6 +68,7 @@ void ucc_slow_stop_tx(struct ucc_slow_private * uccs) id =ucc_slow_get_qe_cr_subblock (us_info->ucc_num);qe_issue_cmd (QE_STOP_TX , id,QE_CR_PROTOCOL_UNSPECIFIED ,0 ); } +EXPORT_SYMBOL (ucc_slow_stop_tx);void ucc_slow_restart_tx (struct ucc_slow_private * uccs) {
@@ -74,6 +78,7 @@ void ucc_slow_restart_tx(struct ucc_slow_private * uccs) id =ucc_slow_get_qe_cr_subblock (us_info->ucc_num);qe_issue_cmd (QE_RESTART_TX , id,QE_CR_PROTOCOL_UNSPECIFIED ,0 ); } +EXPORT_SYMBOL (ucc_slow_restart_tx);void ucc_slow_enable (struct ucc_slow_private * uccs,enum comm_dir mode) {
@@ -94,6 +99,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode) }out_be32 (&us_regs->gumr_l, gumr_l); } +EXPORT_SYMBOL (ucc_slow_enable);void ucc_slow_disable (struct ucc_slow_private * uccs,enum comm_dir mode) {
@@ -114,6 +120,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode) }out_be32 (&us_regs->gumr_l, gumr_l); } +EXPORT_SYMBOL (ucc_slow_disable);/* Initialize the UCC for Slow operations *
@@ -347,6 +354,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc *uccs_ret = uccs;return 0 ; } +EXPORT_SYMBOL (ucc_slow_init);void ucc_slow_free (struct ucc_slow_private * uccs) {
@@ -366,5 +374,5 @@ void ucc_slow_free(struct ucc_slow_private * uccs)kfree (uccs); } - +EXPORT_SYMBOL (ucc_slow_free);
drivers/serial/Kconfig +10 -0
@@ -1284,4 +1284,14 @@ config SERIAL_OF_PLATFORM Currently, only 8250 compatible ports are supported, but others can easily be added. +config SERIAL_QE + tristate "Freescale QUICC Engine serial port support" + depends on QUICC_ENGINE + select SERIAL_CORE + select FW_LOADER + default n + help + This driver supports the QE serial ports on Freescale embedded + PowerPC that contain a QUICC Engine. + endmenu
drivers/serial/Makefile +1 -0
@@ -64,3 +64,4 @@ obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o obj-$(CONFIG_SERIAL_NETX) += netx-serial.o obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o +obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
drivers/serial/ucc_uart.c new file +1507 -0
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Signature · 1 line
1.5.2.4