ColdFire: MCF547x_8x - Add M5475EVB and M5485EVB support
PATCH 8/8 ColdFire: MCF547x_8x - Add M5475EVB and M5485EVB support
ColdFire: MCF547x_8x - Add M5475EVB and M5485EVB support
--- CREDITS | 2 +- MAINTAINERS | 2 + MAKEALL | 2 + Makefile | 71 ++++++++++ README | 1 + doc/README.m5475evb | 279 +++++++++++++++++++++++++++++++++++++ ++ include/configs/M5475EVB.h | 311 +++++++++++++++++++++++++++++++++++++ +++++++ include/configs/M5485EVB.h | 296 +++++++++++++++++++++++++++++++++++++ ++++ 8 files changed, 963 insertions(+), 1 deletions(-) create mode 100644 doc/README.m5475evb create mode 100644 include/configs/M5475EVB.h create mode 100644 include/configs/M5485EVB.h
CREDITS +1 -1
@@ -290,7 +290,7 @@ W: http://www.leox.org N: TsiChung Liew E: Tsi-Chung.Liew at freescale.com -D: Support for ColdFire MCF523x, MCF532x, MCF5445x +D: Support for ColdFire MCF523x, MCF532x, MCF5445x, MCF547x_8x W: www.freescale.com N: Leif Lindholm
MAINTAINERS +2 -0
@@ -632,6 +632,8 @@ TsiChung Liew <[email protected]> M5329EVB mcf532x M5373EVB mcf532x M54455EVB mcf5445x + M5475EVB mcf547x_8x + M5485EVB mcf547x_8x Hayden Fraser <[email protected]>
MAKEALL +2 -0
@@ -645,6 +645,8 @@ LIST_coldfire=" \ M5329AFEE \ M5373EVB \ M54455EVB \ + M5475AFE \ + M5485AFE \ r5200 \ TASREG \ "
Makefile +71 -0
81 lines not on this page · raw message
#########################################################################
## MPC83xx Systems
#########################################################################
README +1 -0
@@ -139,6 +139,7 @@ Directory Hierarchy: - mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs - mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs + - mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs - mips Files specific to MIPS CPUs - mpc5xx Files specific to Freescale MPC5xx CPUs - mpc5xxx Files specific to Freescale MPC5xxx CPUs
doc/README.m5475evb new file +12 -0
@@ -0,0 +1,279 @@ +Freescale MCF5475EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew at freescale.com) +Created Jan 08, 2008 +=========================================== + + +Changed files: +============== + +- board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI
init
+- board/freescale/m547xevb/mii.c MII init +- board/freescale/m547xevb/Makefile Makefile +- board/freescale/m547xevb/config.mk config make +- board/freescale/m547xevb/u-boot.lds Linker description + +- cpu/mcf547x_8x/cpu.c cpu specific code +- cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs +- cpu/mcf547x_8x/interrupts.c cpu specific interrupt support +- cpu/mcf547x_8x/slicetimer.c Timer support +- cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock +- cpu/mcf547x_8x/Makefile Makefile +- cpu/mcf547x_8x/config.mk config make +- cpu/mcf547x_8x/start.S start up assembly code + +- doc/README.m5475evb This readme file + +- drivers/dma/MCD_dmaApi.c DMA API functions +- drivers/dma/MCD_tasks.c DMA Tasks +- drivers/dma/MCD_tasksInit.c DMA Tasks Init +- drivers/net/fsl_mcdmafec.c ColdFire common DMA FEC driver +- drivers/serial/mcfuart.c ColdFire common UART driver + +- include/MCD_dma.h DMA header file +- include/MCD_progCheck.h DMA header file +- include/MCD_tasksInit.h DMA header file +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/errno.h Error Number definition +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/fsl_mcddmafec.h DMA FEC structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_547x_8x.h mcf547x_8x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m547x_8x.h mcf547x_8x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M5475EVB.h Board specific configuration file + +- lib_m68k/board.c board init function +- lib_m68k/cache.c +- lib_m68k/interrupts Coldfire common interrupt functions +- lib_m68k/m68k_linux.c +- lib_m68k/traps.c Exception init code
+
+1 MCF547x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family +
+1.2 Configuration settings for M5475EVB Development Board
+CONFIG_MCF547x_8x -- define for all MCF547x_8x CPUs
+CONFIG_M547x -- define for all Freescale MCF547x CPUs
+CONFIG_M5475 -- define for M5475EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CFG_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_FSLDMAFEC -- define to use common dma FEC driver
+CONFIG_NET_MULTI -- define to use multi FEC in u-boot
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CFG_DISCOVER_PHY -- enable PHY discovery
+CFG_RX_ETH_BUFFER -- Set FEC Receive buffer
+CFG_FAULT_ECHO_LINK_DOWN--
+CFG_FEC0_PINMUX -- Set FEC0 Pin configuration
+CFG_FEC1_PINMUX -- Set FEC1 Pin configuration
+CFG_FEC0_MIIBASE -- Set FEC0 MII base register
+CFG_FEC1_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
+
+CONFIG_CMD_USB -- enable USB commands
+CONFIG_USB_OHCI_NEW -- enable USB OHCI driver
+CONFIG_USB_STORAGE -- enable USB Storage device
+CONFIG_DOS_PARTITION -- enable DOS read/write
+
+CONFIG_SLTTMR -- define to use SLT timer
+
+CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SOFT_I2C -- define for I2C bit-banged
+CFG_I2C_SPEED -- define for I2C speed
+CFG_I2C_SLAVE -- define for I2C slave address
+CFG_I2C_OFFSET -- define for I2C base address offset
+CFG_IMMR -- define for MBAR offset
+
+CONFIG_PCI -- define for PCI support
+CONFIG_PCI_PNP -- define for Plug n play support
+CONFIG_SKIPPCI_HOSTBRIDGE -- SKIP PCI Host bridge
+CFG_PCI_MEM_BUS -- PCI memory logical offset
+CFG_PCI_MEM_PHYS -- PCI memory physical offset
+CFG_PCI_MEM_SIZE -- PCI memory size
+CFG_PCI_IO_BUS -- PCI IO logical offset
+CFG_PCI_IO_PHYS -- PCI IO physical offset
+CFG_PCI_IO_SIZE -- PCI IO size
+CFG_PCI_CFG_BUS -- PCI Configuration logical offset
+CFG_PCI_CFG_PHYS -- PCI Configuration physical offset
+CFG_PCI_CFG_SIZE -- PCI Configuration size
+
+CFG_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CFG_INIT_RAM_ADDR -- defines the base address of the MCF547x internal
SRAM
+
+CFG_CSn_BASE -- defines the Chip Select Base register
+CFG_CSn_MASK -- defines the Chip Select Mask register
+CFG_CSn_CTRL -- defines the Chip Select Control register
+
+CFG_SDRAM_BASE -- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0xFF800000-0xFFFFFFFF (8MB)
+ DDR: 0x00000000-0x3FFFFFFF (1024MB)
+ SRAM: 0xF2000000-0xF2000FFF (4KB)
+ PCI: 0x70000000-0x8FFFFFFF (512MB)
+ IP: 0xF0000000-0xFFFFFFFF (256MB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux
+ version) from codesourcery.com was used. Download it from:
+ http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M5475AFE_config, or - boot 2MB, RAM 64MB + make M5475BFE_config, or - boot 2MB, code 16MB, RAM 64MB + make M5475CFE_config, or - boot 2MB, code 16MB, Video, USB, RAM 64MB + make M5475DFE_config, or - boot 2MB, USB, RAM 64MB + make M5475EFE_config, or - boot 2MB, Video, USB, RAM 64MB + make M5475FFE_config, or - boot 2MB, code 32MB, Video, USB, RAM
128MB
+ make M5475GFE_config, or - boot 2MB, RAM 64MB
+ make
+
+5. SCREEN DUMP
+==============
+5.1
+
+U-Boot 1.3.1 (Jan 8 2008 - 12:47:44)
+
+CPU: Freescale MCF5475
+ CPU CLK 266 Mhz BUS CLK 133 Mhz
+Board: Freescale FireEngine 5475 EVB
+I2C: ready
+DRAM: 64 MB
+FLASH: 18 MB
+In: serial +Out: serial +Err: serial +Net: FEC0, FEC1
+-> pri
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+eth1addr=00:e0:0c:bc:e5:61
+ipaddr=192.162.1.2
+serverip=192.162.1.1
+gatewayip=192.162.1.1
+netmask=255.255.255.0
+hostname=M547xEVB
+netdev=eth0
+loadaddr=10000
+u-boot=u-boot.bin
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save
+stdin=serial
+stdout=serial
+stderr=serial
+ethact=FEC0
+mem=65024k
+
+Environment size: 433/8188 bytes
+-> bdin +memstart = 0x00000000 +memsize = 0x04000000 +flashstart = 0xFF800000 +flashsize = 0x01200000 +flashoffset = 0x00000000 +sramstart = 0xF2000000 +sramsize = 0x00001000 +mbar = 0xF0000000 +busfreq = 133.333 MHz +pcifreq = 0 MHz +ethaddr = 00:E0:0C:BC:E5:60 +eth1addr = 00:E0:0C:BC:E5:61 +ip_addr = 192.162.1.2 +baudrate = 115200 bps +-> ? +? - alias for 'help' +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy +crc32 - checksum calculation +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +icache - enable or disable instruction cache +icrc32 - checksum calculation +iloop - infinite loop on address range +imd - i2c memory display +iminfo - print header information for application image +imls - list all images found in flash +imm - i2c memory modify (auto-incrementing) +imw - memory write (fill) +inm - memory modify (constant address) +iprobe - probe to discover valid I2C chip addresses +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +md - memory display +mii - MII utility commands +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill)
+nfs - boot image via network using NFS protocol
+nm - memory modify (constant address)
+pci - list and access PCI Configuration Space
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage +setenv - set environment variables
+sleep - delay execution for some time
+tftpboot- boot image via network using TFTP protocol
+usb - USB sub-system
+usbboot - boot from USB device
+version - print monitor version
+-> usb start
+(Re)start USB...
+USB: OHCI pci controller (1131, 1561) found @(0:17:0)
+OHCI regs address 0x80000000
+scanning bus for devices... 2 USB Device(s) found
+ scanning bus for storage devices... 1 Storage Device(s) found
+->
include/configs/M5475EVB.h new file +49 -0
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timeout is 6.71sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_USB
+
+#define CONFIG_SLTTMR
+
+#define CONFIG_FSLDMAFEC
+#ifdef CONFIG_FSLDMAFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CONFIG_HAS_ETH1
+
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 32
+# define CFG_TX_ETH_BUFFER 48
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define CFG_FEC1_PINMUX 0
+# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
+
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#endif
+
+#ifdef CONFIG_CMD_USB
+# define CONFIG_USB_OHCI_NEW
+# define CONFIG_USB_STORAGE
+
+# ifndef CONFIG_CMD_PCI
+# define CONFIG_CMD_PCI
+# endif
+# define CONFIG_PCI_OHCI
+# define CONFIG_DOS_PARTITION
+
+# undef CFG_USB_OHCI_BOARD_INIT
+# undef CFG_USB_OHCI_CPU_INIT
+# define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+# define CFG_USB_OHCI_SLOT_NAME "isp1561"
+# define CFG_OHCI_SWAP_REG_ACCESS
+#endif
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00008F00
+#define CFG_IMMR CFG_MBAR
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+#define CONFIG_SKIPPCI_HOSTBRIDGE
+
+#define CFG_PCI_CACHE_LINE_SIZE 8
+
+#define CFG_PCI_MEM_BUS 0x80000000
+#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
+#define CFG_PCI_MEM_SIZE 0x10000000
+
+#define CFG_PCI_IO_BUS 0x71000000
+#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
+#define CFG_PCI_IO_SIZE 0x01000000
+
+#define CFG_PCI_CFG_BUS 0x70000000
+#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
+#define CFG_PCI_CFG_SIZE 0x01000000
+#endif
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M547xEVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off bank 1;" \
+ "era ff800000 ff82ffff;" \
+ "cp.b ${loadaddr} ff800000 ${filesize};"\
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer
Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x00010000
+
+#define CFG_HZ 1000
+#define CFG_CLK CFG_BUSCLK
+#define CFG_CPU_CLK CFG_CLK * 2
+
+#define CFG_MBAR 0xF0000000
+#define CFG_INTSRAM (CFG_MBAR + 0x10000)
+#define CFG_INTSRAMSZ 0x8000
+
+/*#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */ +/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0xF2000000
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x21
+#define CFG_INIT_RAM1_ADDR (CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
+#define CFG_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM
*/
+#define CFG_INIT_RAM1_CTRL 0x21
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial
data */
+#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -0x10)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+ +/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_CFG1 0x73711630
+#define CFG_SDRAM_CFG2 0x46370000
+#define CFG_SDRAM_CTRL 0xE10B0000
+#define CFG_SDRAM_EMOD 0x40010000
+#define CFG_SDRAM_MODE 0x018D0000
+#define CFG_SDRAM_DRVSTRENGTH 0x000002AA
+#ifdef CFG_DRAMSZ1
+# define CFG_SDRAM_SIZE (CFG_DRAMSZ + CFG_DRAMSZ1)
+#else
+# define CFG_SDRAM_SIZE CFG_DRAMSZ
+#endif
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+ +/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+# define CFG_FLASH_BASE (CFG_CS0_BASE)
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection
*/
+# define CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CFG_NOR1SZ
+# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+# define CFG_FLASH_SIZE ((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
+# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
+#else
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_FLASH_SIZE (CFG_BOOTSZ << 20)
+#endif
+#endif
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET 0x2000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_EMBEDDED 1
+ +/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+ +/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - NOR Flash
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE 0xFF800000
+#define CFG_CS0_MASK (((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
+#define CFG_CS0_CTRL 0x00101980
+
+#ifdef CFG_NOR1SZ
+#define CFG_CS1_BASE 0xF8000000
+#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
+#define CFG_CS1_CTRL 0x00000D80
+#endif
+
+#endif /* _M5475EVB_H */
include/configs/M5485EVB.h new file +49 -0
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timeout is 6.71sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_USB
+
+#define CONFIG_SLTTMR
+
+#define CONFIG_FSLDMAFEC
+#ifdef CONFIG_FSLDMAFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CONFIG_HAS_ETH1
+
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 32
+# define CFG_TX_ETH_BUFFER 48
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define CFG_FEC1_PINMUX 0
+# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
+
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#endif
+
+#ifdef CONFIG_CMD_USB
+# define CONFIG_USB_STORAGE
+# define CONFIG_DOS_PARTITION
+# define CONFIG_USB_OHCI_NEW
+# ifndef CONFIG_CMD_PCI
+# define CONFIG_CMD_PCI
+# endif
+/*# define CONFIG_PCI_OHCI*/
+# define CFG_USB_OHCI_REGS_BASE 0x80041000
+# define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+# define CFG_USB_OHCI_SLOT_NAME "isp1561"
+# define CFG_OHCI_SWAP_REG_ACCESS
+#endif
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00008F00
+#define CFG_IMMR CFG_MBAR
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+
+#define CFG_PCI_MEM_BUS 0x80000000
+#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
+#define CFG_PCI_MEM_SIZE 0x10000000
+
+#define CFG_PCI_IO_BUS 0x71000000
+#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
+#define CFG_PCI_IO_SIZE 0x01000000
+
+#define CFG_PCI_CFG_BUS 0x70000000
+#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
+#define CFG_PCI_CFG_SIZE 0x01000000
+#endif
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#define CONFIG_HOSTNAME M548xEVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off bank 1;" \
+ "era ff800000 ff82ffff;" \
+ "cp.b ${loadaddr} ff800000 ${filesize};"\
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer
Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x00010000
+
+#define CFG_HZ 1000
+#define CFG_CLK CFG_BUSCLK
+#define CFG_CPU_CLK CFG_CLK * 2
+
+#define CFG_MBAR 0xF0000000
+#define CFG_INTSRAM (CFG_MBAR + 0x10000)
+#define CFG_INTSRAMSZ 0x8000
+
+/*#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */ +/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0xF2000000
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x21
+#define CFG_INIT_RAM1_ADDR (CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
+#define CFG_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM
*/
+#define CFG_INIT_RAM1_CTRL 0x21
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial
data */
+#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -0x10)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+ +/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_CFG1 0x73711630
+#define CFG_SDRAM_CFG2 0x46370000
+#define CFG_SDRAM_CTRL 0xE10B0000
+#define CFG_SDRAM_EMOD 0x40010000
+#define CFG_SDRAM_MODE 0x018D0000
+#define CFG_SDRAM_DRVSTRENGTH 0x000002AA
+#ifdef CFG_DRAMSZ1
+# define CFG_SDRAM_SIZE (CFG_DRAMSZ + CFG_DRAMSZ1)
+#else
+# define CFG_SDRAM_SIZE CFG_DRAMSZ
+#endif
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+ +/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+# define CFG_FLASH_BASE (CFG_CS0_BASE)
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection
*/
+# define CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CFG_NOR1SZ
+# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+# define CFG_FLASH_SIZE ((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
+# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
+#else
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_FLASH_SIZE (CFG_BOOTSZ << 20)
+#endif
+#endif
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET 0x2000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_EMBEDDED 1
+ +/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+ +/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - NOR Flash
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE 0xFF800000
+#define CFG_CS0_MASK (((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
+#define CFG_CS0_CTRL 0x00101980
+
+#ifdef CFG_NOR1SZ
+#define CFG_CS1_BASE 0xF8000000
+#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
+#define CFG_CS1_CTRL 0x00000D80
+#endif
+
+#endif /* _M5485EVB_H */
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1.5.2