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Problem with configuring the LCD in VGA mode

DISCUSSION Arun C 2 participants 6 messages Mar 8, 2008 – Mar 10, 2008

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Arun C

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#0 lore raw

Hi all,

I have a custom board with VGA support for LCD and i am using the latest git frame buffer driver.

LCD works fine without any problem in QVGA mode with the following timings,

DSS1fclk=55Mhz

mode "240x320-60"

        # D: 5.000 MHz, H: 19.455 kHz, V: 59.862 Hz
        geometry 240 320 240 320 16
        timings 200000 0 14 3 1 3 1
        accel false
        rgba 5/11,6/5,5/0,0/0

endmode

I changed the following parameters for VGA mode keeping DSS1fclk at 55MHz

        .x_res          = 480,
        .y_res          = 640,
        .hsw            = 2,            
        .hfp            = 0,            
        .hbp            = 28,           
        .vsw            = 1,            
        .vfp            = 2,            
        .vbp            = 0,            
        .pixel_clock    = 20000,

As with these settings my pixel clock is set to 18.3Mhz and LCD comes up with the linux logo.

But if I try to display continuously to frame buffer lcd flickers and gfxfifo underflow irq occurs frequently.

I tried increasing DSS1fclk to 82.5 (660Mhz/8) still gfxfifo underflows.

If i keep DSS1fclk=55Mhz and pixel_clock=5000 it works without any problem but the vfreq( vertical refresh rate) is very too low for decent viewing in VGA mode.

Any body faced this issue?? Please help me to solve this problem.

Regards,
Arun c

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#1 lore raw

Hi Arun,

Quoted 13 lines

I changed the following parameters for VGA mode keeping DSS1fclk at 55MHz

        .x_res          = 480,
        .y_res          = 640,
        .hsw            = 2,
        .hfp            = 0,
        .hbp            = 28,
        .vsw            = 1,
        .vfp            = 2,
        .vbp            = 0,
        .pixel_clock    = 20000,

For VGA LCD on 3430SDP we have configured DSS for

         left_margin     = 79,           /* pixclocks */
         right_margin    = 89,           /* pixclocks */
         upper_margin    = 1,            /* line clocks */
         lower_margin    = 0,            /* line clocks */
         hsync_len       = 3,            /* pixclocks */
         vsync_len       = 2,            /* line clocks */
         sync            = 1,            /* hsync & vsync polarity */
         acb             = 0x28,         /* AC-bias pin frequency */
         ipc             = 1,            /* Invert pixel clock */
         onoff           = 1;            /* HSYNC/VSYNC Pixel clk Control*/
Quoted 3 lines

As with these settings my pixel clock is set to 18.3Mhz and LCD comes up with the linux logo.

What is the pixel clock required by LCD? Make your FCLK 4 times the pixel clock.

Quoted 3 lines

But if I try to display continuously to frame buffer lcd flickers and gfxfifo underflow irq occurs frequently.

The FIFO settings needs to be adjusted as well, the difference between upper and lower threshold can be made equal to burst size. And keep the high threshold to 0xff.

Quoted 7 lines

I tried increasing DSS1fclk to 82.5 (660Mhz/8) still gfxfifo underflows.

If i keep DSS1fclk=55Mhz and pixel_clock=5000 it works without any problem but the vfreq( vertical refresh rate) is very too low for decent viewing in VGA mode.

5000?

Quoted 1 line

Any body faced this issue?? Please help me to solve this problem.

Regards,
Khasim

author
#2 lore raw

Hi,

Thanks Syed Khasim for the reply,

Quoted 12 lines

For VGA LCD on 3430SDP we have configured DSS for

         left_margin     = 79,           /* pixclocks */
         right_margin    = 89,           /* pixclocks */
         upper_margin    = 1,            /* line clocks */
         lower_margin    = 0,            /* line clocks */
         hsync_len       = 3,            /* pixclocks */
         vsync_len       = 2,            /* line clocks */
         sync            = 1,            /* hsync & vsync polarity */
         acb             = 0x28,         /* AC-bias pin frequency */
         ipc             = 1,            /* Invert pixel clock */
         onoff           = 1;            /* HSYNC/VSYNC Pixel clk Control*/

I tried with the above values and i am still getting irq errors(gfx underflow).

The timings corresponding to above values are given below

mode "480x640-49"

        # D: 20.600 MHz, H: 31.644 kHz, V: 49.213 Hz
        geometry 480 640 480 640 16
        timings 48543 89 79 0 1 3 2
        accel false
        rgba 5/11,6/5,5/0,0/0

endmode

DSS1fclk is at 82.5 Mhz and my prcm settings is PRCM 3 ( Clocking rate (Crystal/DPLL/MPU): 13.0/660/330 MHz).

That means my dss1Iclk is 110Mhz (L3 is also 110Mhz) is this making any problem??

Quoted 4 lines
Quoted 3 lines

As with these settings my pixel clock is set to 18.3Mhz and LCD comes up with the linux logo.

What is the pixel clock required by LCD? Make your FCLK 4 times the pixel clock.

My lcd datasheet says minimum 23 MHz and maximum 26 MHz. But now my pixel clock is 20Mhz and FCLK is 82.5 (82.5 > 20*4). Is this enough??

Quoted 2 lines

The FIFO settings needs to be adjusted as well, the difference between upper and lower threshold can be made equal to burst size. And keep the high threshold to 0xff.

This is matching in my case( burst = 16 X 32 , high= 0xFF ,low =0xC0)

Quoted 5 lines
Quoted 4 lines

If i keep DSS1fclk=55Mhz and pixel_clock=5000 it works without any problem but the vfreq( vertical refresh rate) is very too low for decent viewing in VGA mode.

5000?

Yes in the git kernel this 5000 is multiplied by 1000 for setting pixel clock.

Regards,
Arun c

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#3 lore raw
Quoted 7 lines
Quoted 2 lines

The FIFO settings needs to be adjusted as well, the difference between

upper and lower threshold can be made equal to burst size. And keep the high threshold to 0xff.

Quoted 1 line

This is matching in my case( burst = 16 X 32 , high= 0xFF ,low =0xC0)

Which processor are you using? For 2430 case it can be 0xFF and 0xC0, for 3430 the FIFO size extends to 0x3FF and 0x3C0 (default values).

What is the make of LCD? Have we used this before on any OMAP boards?

What is the DDR frequency?

Regards,
Khasim

author
#4 lore raw
Quoted 7 lines · Khasim
Quoted 6 lines
Quoted 1 line

The FIFO settings needs to be adjusted as well, the difference between

upper and lower threshold can be made equal to burst size. And keep the high threshold to 0xff.

Quoted 1 line

This is matching in my case( burst = 16 X 32 , high= 0xFF ,low =0xC0)

Quoted 9 lines

Which processor are you using? For 2430 case it can be 0xFF and 0xC0, for 3430 the FIFO size extends to 0x3FF and 0x3C0 (default values).

What is the make of LCD? Have we used this before on any OMAP boards?

What is the DDR frequency?

Regards,
Khasim

I am using 2430 custom board.

Yes my lcd works fine in QVGA resolution

DDR is at 110Mhz(L3 clock)

The interesting thing is that IRQ error messages increases with the pixel clock ie, only lower pixel clocks( 5Mhz ,6 Mhz etc) are seems to be stable on my board.

Regards,
Arun c

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The information transmitted herewith is confidential and proprietary information intended only for use by the individual or entity to which it is addressed. If the reader of this message is not the intended recipient, you are hereby notified that any review, retransmission, dissemination, distribution, copying or other use of, or taking of any action in reliance upon this information is strictly prohibited. If you have received this communication in error, please contact the sender and delete the material from your computer.
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Please do not print this email unless it is absolutely necessary. Spread environmental awareness.

#5 lore raw
Quoted 15 lines
Quoted 3 lines

Which processor are you using? For 2430 case it can be 0xFF and 0xC0,

for 3430 the FIFO size extends to 0x3FF and 0x3C0 (default values).

Quoted 8 lines

What is the make of LCD? Have we used this before on any OMAP boards?

What is the DDR frequency?

Regards,
Khasim

I am using 2430 custom board.

Quoted 10 lines

Yes my lcd works fine in QVGA resolution

DDR is at 110Mhz(L3 clock)

The interesting thing is that IRQ error messages increases with the pixel clock ie, only lower pixel clocks( 5Mhz ,6 Mhz etc) are seems to be stable on my board.

I have seen issues in using 640x480 resolution for TVOUT on 2430 processor, Generally it is adviced to use VRFB in rotation 0 mode to get good DDR bandwidth. This helps in overcoming the flicker due to bandwidth issues.

You can refer to TI's code for DDR usage. But the issue is it uses consistent memory of size (2048 * bpp * height).

Regards,
Khasim