mpc83xx: initialize serdes for MPC837xEMDS boards
PATCH 1/2 mpc83xx: initialize serdes for MPC837xEMDS boards
This patch is stolen from Anton Vorontsov's patch
for mpc837xerdb boards.
The reference clk and xcorevdd voltage of serdes1/2 is same between mpc837xemds and mpc837xerdb.
8377E: LYNX1- 2 SATA LYNX2- 2 PCIE
8378E: LYNX1- 2 SGMII LYNX2- 2 PCIE
8379E: LYNX1- 2 SATA LYNX2- 2 SATA
Signed-off-by Dave Liu <[email protected]>
--- board/freescale/mpc837xemds/mpc837xemds.c | 33 +++++++++++++++++++++++++++++ include/configs/MPC837XEMDS.h | 5 ++++ 2 files changed, 38 insertions(+), 0 deletions(-)
board/freescale/mpc837xemds/mpc837xemds.c +33 -0
@@ -12,6 +12,8 @@#include <common.h> #include <i2c.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> #include <spd_sdram.h> #if defined(CONFIG_OF_LIBFDT )#include <libfdt.h>
@@ -29,6 +31,37 @@ int board_early_init_f(void)/* Clear all of the interrupt of BCSR */ bcsr[0xe ] =0xff ; +#ifdef CONFIG_FSL_SERDES +immap_t *immr = (immap_t *)CFG_IMMR ; +u32 spridr =in_be32 (&immr->sysconf.spridr); + +/* we check only part num, and don't look for CPU revisions */ +switch (spridr >>16 ) { +case SPR_8379E_REV10 >>16 : +case SPR_8379_REV10 >>16 : +fsl_setup_serdes (CONFIG_FSL_SERDES1 ,FSL_SERDES_PROTO_SATA , +FSL_SERDES_CLK_100 ,FSL_SERDES_VDD_1V ); +fsl_setup_serdes (CONFIG_FSL_SERDES2 ,FSL_SERDES_PROTO_SATA , +FSL_SERDES_CLK_100 ,FSL_SERDES_VDD_1V ); +break ; +case SPR_8378E_REV10 >>16 : +case SPR_8378_REV10 >>16 : +fsl_setup_serdes (CONFIG_FSL_SERDES1 ,FSL_SERDES_PROTO_PEX , +FSL_SERDES_CLK_100 ,FSL_SERDES_VDD_1V ); +break ; +case SPR_8377E_REV10 >>16 : +case SPR_8377_REV10 >>16 : +fsl_setup_serdes (CONFIG_FSL_SERDES1 ,FSL_SERDES_PROTO_SATA , +FSL_SERDES_CLK_100 ,FSL_SERDES_VDD_1V ); +fsl_setup_serdes (CONFIG_FSL_SERDES2 ,FSL_SERDES_PROTO_PEX , +FSL_SERDES_CLK_100 ,FSL_SERDES_VDD_1V ); +break ; +default : +printf ("serdes not configured: unknown CPU part number: " +"%04x\n" , spridr >>16 ); +break ; + } +#endif /* CONFIG_FSL_SERDES */ return 0 ; }
include/configs/MPC837XEMDS.h +5 -0
@@ -389,6 +389,11 @@/* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "eTSEC1" +/* SERDES */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 +#define CONFIG_FSL_SERDES2 0xe3100 +/* * Environment */
Signature · 1 line
1.5.4.rc4