AT91SAM9260 support

index 4110e15..c6df5bd 100644
@@ -41,7 +41,7 @@ ulong resettime;
 AT91PS_PITC p_pitc;
 
 /* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init(void)
+int timer_init(void)
 {
 	/*
 	 * Enable PITC Clock

index 0971fea..1819f6b 100644
@@ -38,7 +38,7 @@
 #include <common.h>
 #include <arm926ejs.h>
 
-#if defined(CONFIG_INTEGRATOR) || defined(CONFIG_AT91CAP9ADK)
+#ifdef CONFIG_INTEGRATOR
 
 	/* Timer functionality supplied by Integrator board (AP or CP) */
 

similarity index 94%
rename from cpu/arm926ejs/at91cap9/ether.c
rename to cpu/arm926ejs/at91sam9/ether.c
index b7958d5..8de1bb7 100644
@@ -23,12 +23,12 @@
  */
 
 #include <common.h>
-#include <asm/arch/AT91CAP9.h>
+#include <asm/arch/hardware.h>
 
 extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
 
 #if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
-void at91cap9_eth_initialize(bd_t *bi)
+void at91sam9_eth_initialize(bd_t *bi)
 {
 	macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00);
 }

similarity index 100%
rename from cpu/arm926ejs/at91cap9/spi.c
rename to cpu/arm926ejs/at91sam9/spi.c

similarity index 97%
rename from cpu/arm926ejs/at91cap9/timer.c
rename to cpu/arm926ejs/at91sam9/timer.c
index c6df5bd..79c135f 100644
@@ -26,7 +26,7 @@
 #include <asm/arch/hardware.h>
 
 /*
- * We're using the AT91CAP9 PITC in 32 bit mode, by
+ * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
  * setting the 20 bit counter period to its maximum (0xfffff).
  */
 #define TIMER_LOAD_VAL	0xfffff

@@ -134,8 +134,7 @@ ulong get_tbclk(void)
 }
 
 /*
- * Reset the cpu by setting up the watchdog timer and let him time out
- * on the AT91CAP9ADK board
+ * Reset the cpu by setting up the watchdog timer and let him time out.
  */
 void reset_cpu(ulong ignored)
 {

similarity index 96%
rename from cpu/arm926ejs/at91cap9/usb.c
rename to cpu/arm926ejs/at91sam9/usb.c
index 69da5f3..09292a6 100644
@@ -24,7 +24,6 @@
 #include <common.h>
 
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
-#ifdef CONFIG_AT91CAP9
 
 #include <asm/arch/hardware.h>
 

@@ -50,5 +49,4 @@ int usb_cpu_init_fail(void)
 	return usb_cpu_stop();
 }
 
-#endif /* CONFIG_AT91CAP9 */
 #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */

similarity index 100%
rename from include/asm-arm/arch-at91cap9/AT91CAP9.h
rename to include/asm-arm/arch-at91sam9/AT91CAP9.h

similarity index 100%
rename from include/asm-arm/arch-at91cap9/clk.h
rename to include/asm-arm/arch-at91sam9/clk.h

similarity index 100%
rename from include/asm-arm/arch-at91cap9/hardware.h
rename to include/asm-arm/arch-at91sam9/hardware.h

similarity index 100%
rename from include/asm-arm/arch-at91cap9/memory-map.h
rename to include/asm-arm/arch-at91sam9/memory-map.h

index 16a6dcb..1a98a91 100644
@@ -63,7 +63,7 @@ extern int atstk1000_eth_initialize(bd_t *);
 extern int atngw100_eth_initialize(bd_t *);
 extern int mcffec_initialize(bd_t*);
 extern int mcdmafec_initialize(bd_t*);
-extern int at91cap9_eth_initialize(bd_t *);
+extern int at91sam9_eth_initialize(bd_t *);
 
 #ifdef CONFIG_API
 extern void (*push_packet)(volatile void *, int);

@@ -285,7 +285,7 @@ int eth_initialize(bd_t *bis)
 	mcdmafec_initialize(bis);
 #endif
 #if defined(CONFIG_AT91CAP9)
-	at91cap9_eth_initialize(bis);
+	at91sam9_eth_initialize(bis);
 #endif
 
 	if (!eth_devices) {

deleted file mode 100644
index 02ef9a8..0000000
@@ -1,518 +0,0 @@
-/*
- * (C) Copyright 2008
- * AT91CAP9 definitions
- * Author : ATMEL AT91 application group
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91CAP9_H
-#define AT91CAP9_H
-
-typedef volatile unsigned int AT91_REG;
-
-/* Static Memory Controller */
-typedef struct _AT91S_SMC {
-	AT91_REG	SMC_SETUP0;	/* Setup Register for CS 0 */
-	AT91_REG	SMC_PULSE0;	/* Pulse Register for CS 0 */
-	AT91_REG	SMC_CYCLE0;	/* Cycle Register for CS 0 */
-	AT91_REG	SMC_CTRL0;	/* Control Register for CS 0 */
-	AT91_REG	SMC_SETUP1;	/* Setup Register for CS 1 */
-	AT91_REG	SMC_PULSE1;	/* Pulse Register for CS 1 */
-	AT91_REG	SMC_CYCLE1;	/* Cycle Register for CS 1 */
-	AT91_REG	SMC_CTRL1;	/* Control Register for CS 1 */
-	AT91_REG	SMC_SETUP2;	/* Setup Register for CS 2 */
-	AT91_REG	SMC_PULSE2;	/* Pulse Register for CS 2 */
-	AT91_REG	SMC_CYCLE2;	/* Cycle Register for CS 2 */
-	AT91_REG	SMC_CTRL2;	/* Control Register for CS 2 */
-	AT91_REG	SMC_SETUP3;	/* Setup Register for CS 3 */
-	AT91_REG	SMC_PULSE3;	/* Pulse Register for CS 3 */
-	AT91_REG	SMC_CYCLE3;	/* Cycle Register for CS 3 */
-	AT91_REG	SMC_CTRL3;	/* Control Register for CS 3 */
-	AT91_REG	SMC_SETUP4;	/* Setup Register for CS 4 */
-	AT91_REG	SMC_PULSE4;	/* Pulse Register for CS 4 */
-	AT91_REG	SMC_CYCLE4;	/* Cycle Register for CS 4 */
-	AT91_REG	SMC_CTRL4;	/* Control Register for CS 4 */
-	AT91_REG	SMC_SETUP5;	/* Setup Register for CS 5 */
-	AT91_REG	SMC_PULSE5;	/* Pulse Register for CS 5 */
-	AT91_REG	SMC_CYCLE5;	/* Cycle Register for CS 5 */
-	AT91_REG	SMC_CTRL5;	/* Control Register for CS 5 */
-	AT91_REG	SMC_SETUP6;	/* Setup Register for CS 6 */
-	AT91_REG	SMC_PULSE6;	/* Pulse Register for CS 6 */
-	AT91_REG	SMC_CYCLE6;	/* Cycle Register for CS 6 */
-	AT91_REG	SMC_CTRL6;	/* Control Register for CS 6 */
-	AT91_REG	SMC_SETUP7;	/* Setup Register for CS 7 */
-	AT91_REG	SMC_PULSE7;	/* Pulse Register for CS 7 */
-	AT91_REG	SMC_CYCLE7;	/* Cycle Register for CS 7 */
-	AT91_REG	SMC_CTRL7;	/* Control Register for CS 7 */
-} AT91S_SMC, *AT91PS_SMC;
-
-/* SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x */
-#define AT91C_SMC_NWESETUP	(0x3F <<  0)	/* NWE Setup Length */
-#define AT91C_SMC_NCSSETUPWR	(0x3F <<  8)	/* NCS Setup Length for WRite */
-#define AT91C_SMC_NRDSETUP	(0x3F << 16)	/* NRD Setup Length */
-#define AT91C_SMC_NCSSETUPRD	(0x3F << 24)	/* NCS Setup Length for ReaD */
-/* SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x */
-#define AT91C_SMC_NWEPULSE	(0x7F <<  0)	/* NWE Pulse Length */
-#define AT91C_SMC_NCSPULSEWR	(0x7F <<  8)	/* NCS Pulse Length for WRite */
-#define AT91C_SMC_NRDPULSE	(0x7F << 16)	/* NRD Pulse Length */
-#define AT91C_SMC_NCSPULSERD	(0x7F << 24)	/* NCS Pulse Length for ReaD */
-/* SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x */
-#define AT91C_SMC_NWECYCLE	(0x1FF <<  0)	/* Total Write Cycle Length */
-#define AT91C_SMC_NRDCYCLE	(0x1FF << 16)	/* Total Read Cycle Length */
-/* SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x */
-#define AT91C_SMC_READMODE	(0x1 <<  0)	/* Read Mode */
-#define AT91C_SMC_WRITEMODE	(0x1 <<  1)	/* Write Mode */
-#define AT91C_SMC_NWAITM	(0x3 <<  5)	/* NWAIT Mode */
-		/* External NWAIT disabled */
-#define		AT91C_SMC_NWAITM_NWAIT_DISABLE		(0x0 <<  5)
-		/* External NWAIT enabled in frozen mode */
-#define		AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN	(0x2 <<  5)
-		/* External NWAIT enabled in ready mode */
-#define		AT91C_SMC_NWAITM_NWAIT_ENABLE_READY	(0x3 <<  5)
-#define AT91C_SMC_BAT		(0x1 <<  8)	/* Byte Access Type */
-		/*
-		 * Write controled by ncs, nbs0, nbs1, nbs2, nbs3.
-		 * Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
-		 */
-#define		AT91C_SMC_BAT_BYTE_SELECT		(0x0 <<  8)
-		/*
-		 * Write controled by ncs, nwe0, nwe1, nwe2, nwe3.
-		 * Read controled by ncs and nrd.
-		 */
-#define		AT91C_SMC_BAT_BYTE_WRITE		(0x1 <<  8)
-#define AT91C_SMC_DBW		(0x3 << 12)	/* Data Bus Width */
-#define		AT91C_SMC_DBW_WIDTH_EIGTH_BITS		(0x0 << 12)
-#define		AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS	(0x1 << 12)
-#define		AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS	(0x2 << 12)
-#define AT91C_SMC_TDF		(0xF << 16)	/* Data Float Time */
-#define AT91C_SMC_TDFEN		(0x1 << 20)	/* TDF Enabled */
-#define AT91C_SMC_PMEN		(0x1 << 24)	/* Page Mode Enabled */
-#define AT91C_SMC_PS		(0x3 << 28)	/* Page Size */
-#define		AT91C_SMC_PS_SIZE_FOUR_BYTES		(0x0 << 28)
-#define		AT91C_SMC_PS_SIZE_EIGHT_BYTES		(0x1 << 28)
-#define		AT91C_SMC_PS_SIZE_SIXTEEN_BYTES		(0x2 << 28)
-#define		AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES	(0x3 << 28)
-/* SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x */
-/* SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x */
-/* SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x */
-/* SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x */
-/* SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x */
-/* SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x */
-/* SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x */
-/* SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x */
-/* SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x */
-/* SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x */
-/* SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x */
-/* SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x */
-/* SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x */
-/* SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x */
-/* SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x */
-/* SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x */
-/* SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x */
-/* SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x */
-/* SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x */
-/* SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x */
-/* SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x */
-/* SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x */
-/* SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x */
-/* SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x */
-/* SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x */
-/* SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x */
-/* SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x */
-/* SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x */
-
-/* AHB CCFG */
-typedef struct _AT91S_CCFG {
-	AT91_REG	Reserved0[1];
-	AT91_REG	CCFG_MPBS0;	/* MPB Slave 0 */
-	AT91_REG	CCFG_UDPHS;	/* AHB Periphs */
-	AT91_REG	CCFG_MPBS1;	/* MPB Slave 1 */
-	AT91_REG	CCFG_EBICSA;	/* EBI Chip Select Assignement */
-	AT91_REG	Reserved1[2];
-	AT91_REG	CCFG_MPBS2;	/* MPB Slave 2 */
-	AT91_REG	CCFG_MPBS3;	/* MPB Slave 3 */
-	AT91_REG	CCFG_BRIDGE;	/* APB Bridge */
-	AT91_REG	Reserved2[49];
-	AT91_REG	CCFG_MATRIXVERSION;/* Version */
-} AT91S_CCFG, *AT91PS_CCFG;
-
-/* CCFG_UDPHS : (CCFG Offset: 0x8) UDPHS Configuration */
-#define AT91C_CCFG_UDPHS_UDP_SELECT	(0x1 << 31)	/* UDPHS or UDP */
-#define		AT91C_CCFG_UDPHS_UDP_SELECT_UDPHS	(0x0 << 31)
-#define		AT91C_CCFG_UDPHS_UDP_SELECT_UDP		(0x1 << 31)
-/* CCFG_EBICSA : (CCFG Offset: 0x10) EBI Chip Select Assignement Register */
-#define AT91C_EBI_CS1A			(0x1 <<  1)	/* CS1 Assignment */
-#define		AT91C_EBI_CS1A_SMC			(0x0 <<  1)
-#define		AT91C_EBI_CS1A_BCRAMC			(0x1 <<  1)
-#define AT91C_EBI_CS3A			(0x1 <<  3)	/* CS 3 Assignment */
-#define		AT91C_EBI_CS3A_SMC			(0x0 <<  3)
-#define		AT91C_EBI_CS3A_SM			(0x1 <<  3)
-#define AT91C_EBI_CS4A			(0x1 <<  4)	/* CS4 Assignment */
-#define		AT91C_EBI_CS4A_SMC			(0x0 <<  4)
-#define		AT91C_EBI_CS4A_CF			(0x1 <<  4)
-#define AT91C_EBI_CS5A			(0x1 <<  5)	/* CS 5 Assignment */
-#define		AT91C_EBI_CS5A_SMC			(0x0 <<  5)
-#define		AT91C_EBI_CS5A_CF			(0x1 <<  5)
-#define AT91C_EBI_DBPUC			(0x1 <<  8)	/* Data Bus Pull-up */
-#define AT91C_EBI_DDRPUC		(0x1 <<  9)	/* DDDR DQS Pull-up */
-#define AT91C_EBI_SUP			(0x1 << 16)	/* EBI Supply */
-#define		AT91C_EBI_SUP_1V8			(0x0 << 16)
-#define		AT91C_EBI_SUP_3V3			(0x1 << 16)
-#define AT91C_EBI_LP			(0x1 << 17)	/* EBI Low Power */
-#define		AT91C_EBI_LP_LOW_DRIVE			(0x0 << 17)
-#define		AT91C_EBI_LP_STD_DRIVE			(0x1 << 17)
-#define AT91C_CCFG_DDR_SDR_SELECT	(0x1 << 31)	/* DDR or SDR */
-#define		AT91C_CCFG_DDR_SDR_SELECT_DDR		(0x0 << 31)
-#define		AT91C_CCFG_DDR_SDR_SELECT_SDR		(0x1 << 31)
-/* CCFG_BRIDGE : (CCFG Offset: 0x24) BRIDGE Configuration */
-#define AT91C_CCFG_AES_TDES_SELECT	(0x1 << 31)	/* AES or TDES */
-#define		AT91C_CCFG_AES_TDES_SELECT_AES		(0x0 << 31)
-#define		AT91C_CCFG_AES_TDES_SELECT_TDES		(0x1 << 31)
-
-/* PIO controller */
-typedef struct _AT91S_PIO {
-	AT91_REG	PIO_PER;	/* PIO Enable Register */
-	AT91_REG	PIO_PDR;	/* PIO Disable Register */
-	AT91_REG	PIO_PSR;	/* PIO Status Register */
-	AT91_REG	Reserved0[1];
-	AT91_REG	PIO_OER;	/* Output Enable Register */
-	AT91_REG	PIO_ODR;	/* Output Disable Register */
-	AT91_REG	PIO_OSR;	/* Output Status Register */
-	AT91_REG	Reserved1[1];
-	AT91_REG	PIO_IFER;	/* Input Filter Enable Register */
-	AT91_REG	PIO_IFDR;	/* Input Filter Disable Register */
-	AT91_REG	PIO_IFSR;	/* Input Filter Status Register */
-	AT91_REG	Reserved2[1];
-	AT91_REG	PIO_SODR;	/* Set Output Data Register */
-	AT91_REG	PIO_CODR;	/* Clear Output Data Register */
-	AT91_REG	PIO_ODSR;	/* Output Data Status Register */
-	AT91_REG	PIO_PDSR;	/* Pin Data Status Register */
-	AT91_REG	PIO_IER;	/* Interrupt Enable Register */
-	AT91_REG	PIO_IDR;	/* Interrupt Disable Register */
-	AT91_REG	PIO_IMR;	/* Interrupt Mask Register */
-	AT91_REG	PIO_ISR;	/* Interrupt Status Register */
-	AT91_REG	PIO_MDER;	/* Multi-driver Enable Register */
-	AT91_REG	PIO_MDDR;	/* Multi-driver Disable Register */
-	AT91_REG	PIO_MDSR;	/* Multi-driver Status Register */
-	AT91_REG	Reserved3[1];
-	AT91_REG	PIO_PPUDR;	/* Pull-up Disable Register */
-	AT91_REG	PIO_PPUER;	/* Pull-up Enable Register */
-	AT91_REG	PIO_PPUSR;	/* Pull-up Status Register */
-	AT91_REG	Reserved4[1];
-	AT91_REG	PIO_ASR;	/* Select A Register */
-	AT91_REG	PIO_BSR;	/* Select B Register */
-	AT91_REG	PIO_ABSR;	/* AB Select Status Register */
-	AT91_REG	Reserved5[9];
-	AT91_REG	PIO_OWER;	/* Output Write Enable Register */
-	AT91_REG	PIO_OWDR;	/* Output Write Disable Register */
-	AT91_REG	PIO_OWSR;	/* Output Write Status Register */
-} AT91S_PIO, *AT91PS_PIO;
-
-/* Power Management Controller */
-typedef struct _AT91S_PMC {
-	AT91_REG	PMC_SCER;	/* System Clock Enable Register */
-	AT91_REG	PMC_SCDR;	/* System Clock Disable Register */
-	AT91_REG	PMC_SCSR;	/* System Clock Status Register */
-	AT91_REG	Reserved0[1];
-	AT91_REG	PMC_PCER;	/* Peripheral Clock Enable Register */
-	AT91_REG	PMC_PCDR;	/* Peripheral Clock Disable Register */
-	AT91_REG	PMC_PCSR;	/* Peripheral Clock Status Register */
-	AT91_REG	PMC_UCKR;	/* UTMI Clock Configuration Register */
-	AT91_REG	PMC_MOR;	/* Main Oscillator Register */
-	AT91_REG	PMC_MCFR;	/* Main Clock  Frequency Register */
-	AT91_REG	PMC_PLLAR;	/* PLL A Register */
-	AT91_REG	PMC_PLLBR;	/* PLL B Register */
-	AT91_REG	PMC_MCKR;	/* Master Clock Register */
-	AT91_REG	Reserved1[3];
-	AT91_REG	PMC_PCKR[8];	/* Programmable Clock Register */
-	AT91_REG	PMC_IER;	/* Interrupt Enable Register */
-	AT91_REG	PMC_IDR;	/* Interrupt Disable Register */
-	AT91_REG	PMC_SR;		/* Status Register */
-	AT91_REG	PMC_IMR;	/* Interrupt Mask Register */
-} AT91S_PMC, *AT91PS_PMC;
-
-/* PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register */
-#define AT91C_PMC_PCK		(0x1 <<  0)	/* Processor Clock */
-#define AT91C_PMC_OTG		(0x1 <<  5)	/* USB OTG Clock */
-#define AT91C_PMC_UHP		(0x1 <<  6)	/* USB Host Port Clock */
-#define AT91C_PMC_UDP		(0x1 <<  7)	/* USB Device Port Clock */
-#define AT91C_PMC_PCK0		(0x1 <<  8)	/* Programmable Clock Output */
-#define AT91C_PMC_PCK1		(0x1 <<  9)	/* Programmable Clock Output */
-#define AT91C_PMC_PCK2		(0x1 << 10)	/* Programmable Clock Output */
-#define AT91C_PMC_PCK3		(0x1 << 11)	/* Programmable Clock Output */
-/* PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register */
-/* PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register */
-/* CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register */
-/* CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register */
-/* CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register */
-/* CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register */
-/* CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register */
-/* PMC_MCKR : (PMC Offset: 0x30) Master Clock Register */
-#define AT91C_PMC_CSS		(0x3 <<  0)	/* Clock Selection */
-#define		AT91C_PMC_CSS_SLOW_CLK		(0x0 <<  0)	/* Slow Clk */
-#define		AT91C_PMC_CSS_MAIN_CLK		(0x1 <<  0)	/* Main Clk */
-#define		AT91C_PMC_CSS_PLLA_CLK		(0x2 <<  0)	/* PLL A Clk */
-#define		AT91C_PMC_CSS_PLLB_CLK		(0x3 <<  0)	/* PLL B Clk */
-#define AT91C_PMC_PRES		(0x7 <<  2)	/* Clock Prescaler */
-#define		AT91C_PMC_PRES_CLK		(0x0 <<  2)
-#define		AT91C_PMC_PRES_CLK_2		(0x1 <<  2)
-#define		AT91C_PMC_PRES_CLK_4		(0x2 <<  2)
-#define		AT91C_PMC_PRES_CLK_8		(0x3 <<  2)
-#define		AT91C_PMC_PRES_CLK_16		(0x4 <<  2)
-#define		AT91C_PMC_PRES_CLK_32		(0x5 <<  2)
-#define		AT91C_PMC_PRES_CLK_64		(0x6 <<  2)
-#define AT91C_PMC_MDIV		(0x3 <<  8)	/* Master Clock Division */
-#define		AT91C_PMC_MDIV_1		(0x0 <<  8)
-#define		AT91C_PMC_MDIV_2		(0x1 <<  8)
-#define		AT91C_PMC_MDIV_4		(0x2 <<  8)
-/* PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register */
-/* PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register */
-#define AT91C_PMC_MOSCS		(0x1 <<  0)	/* MOSC mask */
-#define AT91C_PMC_LOCKA		(0x1 <<  1)	/* PLL A mask */
-#define AT91C_PMC_LOCKB		(0x1 <<  2)	/* PLL B mask */
-#define AT91C_PMC_MCKRDY	(0x1 <<  3)	/* Master mask */
-#define AT91C_PMC_LOCKU		(0x1 <<  6)	/* PLL UTMI mask */
-#define AT91C_PMC_PCK0RDY	(0x1 <<  8)	/* PCK0_RDY mask */
-#define AT91C_PMC_PCK1RDY	(0x1 <<  9)	/* PCK1_RDY mask */
-#define AT91C_PMC_PCK2RDY	(0x1 << 10)	/* PCK2_RDY mask */
-#define AT91C_PMC_PCK3RDY	(0x1 << 11)	/* PCK3_RDY mask */
-/* PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register */
-/* PMC_SR : (PMC Offset: 0x68) PMC Status Register */
-/* PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register */
-
-/* Reset controller */
-typedef struct _AT91S_RSTC {
-	AT91_REG	RSTC_RCR;	/* Reset Control Register */
-	AT91_REG	RSTC_RSR;	/* Reset Status Register */
-	AT91_REG	RSTC_RMR;	/* Reset Mode Register */
-} AT91S_RSTC, *AT91PS_RSTC;
-
-/* RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register */
-#define AT91C_RSTC_PROCRST	(0x1 <<  0)	/* Processor Reset */
-#define AT91C_RSTC_ICERST	(0x1 <<  1)	/* ICE Interface Reset */
-#define AT91C_RSTC_PERRST	(0x1 <<  2)	/* Peripheral Reset */
-#define AT91C_RSTC_EXTRST	(0x1 <<  3)	/* External Reset */
-#define AT91C_RSTC_KEY		(0xFF << 24)	/* Password */
-/* RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register */
-#define AT91C_RSTC_URSTS	(0x1 <<  0)	/* User Reset Status */
-#define AT91C_RSTC_RSTTYP	(0x7 <<  8)	/* Reset Type */
-#define		AT91C_RSTC_RSTTYP_GENERAL	(0x0 <<  8)
-#define		AT91C_RSTC_RSTTYP_WAKEUP	(0x1 <<  8)
-#define		AT91C_RSTC_RSTTYP_WATCHDOG	(0x2 <<  8)
-#define		AT91C_RSTC_RSTTYP_SOFTWARE	(0x3 <<  8)
-#define		AT91C_RSTC_RSTTYP_USER		(0x4 <<  8)
-#define AT91C_RSTC_NRSTL	(0x1 << 16)	/* NRST pin level */
-#define AT91C_RSTC_SRCMP	(0x1 << 17)	/* Software Rst in Progress. */
-/* RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register */
-#define AT91C_RSTC_URSTEN	(0x1 <<  0)	/* User Reset Enable */
-#define AT91C_RSTC_URSTIEN	(0x1 <<  4)	/* User Reset Int. Enable */
-#define AT91C_RSTC_ERSTL	(0xF <<  8)	/* User Reset Enable */
-
-/* Periodic Timer Controller */
-typedef struct _AT91S_PITC {
-	AT91_REG	PITC_PIMR;	/* Period Interval Mode Register */
-	AT91_REG	PITC_PISR;	/* Period Interval Status Register */
-	AT91_REG	PITC_PIVR;	/* Period Interval Value Register */
-	AT91_REG	PITC_PIIR;	/* Period Interval Image Register */
-} AT91S_PITC, *AT91PS_PITC;
-
-/* PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register */
-#define AT91C_PITC_PIV		(0xFFFFF <<  0)	/* Periodic Interval Value */
-#define AT91C_PITC_PITEN	(0x1 << 24)	/* PIT Enable */
-#define AT91C_PITC_PITIEN	(0x1 << 25)	/* PIT Interrupt Enable */
-/* PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register */
-#define AT91C_PITC_PITS		(0x1 <<  0)	/* PIT Status */
-/* PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register */
-#define AT91C_PITC_CPIV		(0xFFFFF <<  0)	/* Current Value */
-#define AT91C_PITC_PICNT	(0xFFF << 20)	/* Periodic Interval Counter */
-/* PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register */
-
-/* Serial Paraller Interface */
-typedef struct _AT91S_SPI {
-	AT91_REG	SPI_CR;		/* Control Register */
-	AT91_REG	SPI_MR;		/* Mode Register */
-	AT91_REG	SPI_RDR;	/* Receive Data Register */
-	AT91_REG	SPI_TDR;	/* Transmit Data Register */
-	AT91_REG	SPI_SR;		/* Status Register */
-	AT91_REG	SPI_IER;	/* Interrupt Enable Register */
-	AT91_REG	SPI_IDR;	/* Interrupt Disable Register */
-	AT91_REG	SPI_IMR;	/* Interrupt Mask Register */
-	AT91_REG	Reserved0[4];
-	AT91_REG	SPI_CSR[4];	/* Chip Select Register */
-	AT91_REG	Reserved1[48];
-	AT91_REG	SPI_RPR;	/* Receive Pointer Register */
-	AT91_REG	SPI_RCR;	/* Receive Counter Register */
-	AT91_REG	SPI_TPR;	/* Transmit Pointer Register */
-	AT91_REG	SPI_TCR;	/* Transmit Counter Register */
-	AT91_REG	SPI_RNPR;	/* Receive Next Pointer Register */
-	AT91_REG	SPI_RNCR;	/* Receive Next Counter Register */
-	AT91_REG	SPI_TNPR;	/* Transmit Next Pointer Register */
-	AT91_REG	SPI_TNCR;	/* Transmit Next Counter Register */
-	AT91_REG	SPI_PTCR;	/* PDC Transfer Control Register */
-	AT91_REG	SPI_PTSR;	/* PDC Transfer Status Register */
-} AT91S_SPI, *AT91PS_SPI;
-
-/* SPI_CR : (SPI Offset: 0x0) SPI Control Register */
-#define AT91C_SPI_SPIEN		(0x1 <<  0)	/* SPI Enable */
-#define AT91C_SPI_SPIDIS	(0x1 <<  1)	/* SPI Disable */
-#define AT91C_SPI_SWRST		(0x1 <<  7)	/* SPI Software reset */
-#define AT91C_SPI_LASTXFER	(0x1 << 24)	/* SPI Last Transfer */
-/* SPI_MR : (SPI Offset: 0x4) SPI Mode Register */
-#define AT91C_SPI_MSTR		(0x1 <<  0)	/* Master/Slave Mode */
-#define AT91C_SPI_PS		(0x1 <<  1)	/* Peripheral Select */
-#define		AT91C_SPI_PS_FIXED		(0x0 <<  1)
-#define		AT91C_SPI_PS_VARIABLE		(0x1 <<  1)
-#define AT91C_SPI_PCSDEC	(0x1 <<  2)	/* Chip Select Decode */
-#define AT91C_SPI_FDIV		(0x1 <<  3)	/* Clock Selection */
-#define AT91C_SPI_MODFDIS	(0x1 <<  4)	/* Mode Fault Detection */
-#define AT91C_SPI_LLB		(0x1 <<  7)	/* Clock Selection */
-#define AT91C_SPI_PCS		(0xF << 16)	/* Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS	(0xFF << 24)	/* Delay Between Chip Selects */
-/* SPI_RDR : (SPI Offset: 0x8) Receive Data Register */
-#define AT91C_SPI_RD		(0xFFFF <<  0)	/* Receive Data */
-#define AT91C_SPI_RPCS		(0xF << 16)	/* Peripheral CS Status */
-/* SPI_TDR : (SPI Offset: 0xc) Transmit Data Register */
-#define AT91C_SPI_TD		(0xFFFF <<  0)	/* Transmit Data */
-#define AT91C_SPI_TPCS		(0xF << 16)	/* Peripheral CS Status */
-/* SPI_SR : (SPI Offset: 0x10) Status Register */
-#define AT91C_SPI_RDRF		(0x1 <<  0)	/* Receive Data Register Full */
-#define AT91C_SPI_TDRE		(0x1 <<  1)	/* Trans. Data Register Empty */
-#define AT91C_SPI_MODF		(0x1 <<  2)	/* Mode Fault Error */
-#define AT91C_SPI_OVRES		(0x1 <<  3)	/* Overrun Error Status */
-#define AT91C_SPI_ENDRX		(0x1 <<  4)	/* End of Receiver Transfer */
-#define AT91C_SPI_ENDTX		(0x1 <<  5)	/* End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF	(0x1 <<  6)	/* RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE	(0x1 <<  7)	/* TXBUFE Interrupt */
-#define AT91C_SPI_NSSR		(0x1 <<  8)	/* NSSR Interrupt */
-#define AT91C_SPI_TXEMPTY	(0x1 <<  9)	/* TXEMPTY Interrupt */
-#define AT91C_SPI_SPIENS	(0x1 << 16)	/* Enable Status */
-/* SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register */
-/* SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register */
-/* SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register */
-/* SPI_CSR : (SPI Offset: 0x30) Chip Select Register */
-#define AT91C_SPI_CPOL		(0x1 <<  0)	/* Clock Polarity */
-#define AT91C_SPI_NCPHA		(0x1 <<  1)	/* Clock Phase */
-#define AT91C_SPI_CSAAT		(0x1 <<  3)	/* CS Active After Transfer */
-#define AT91C_SPI_BITS		(0xF <<  4)	/* Bits Per Transfer */
-#define		AT91C_SPI_BITS_8		(0x0 <<  4)	/* 8 Bits */
-#define		AT91C_SPI_BITS_9		(0x1 <<  4)	/* 9 Bits */
-#define		AT91C_SPI_BITS_10		(0x2 <<  4)	/* 10 Bits */
-#define		AT91C_SPI_BITS_11		(0x3 <<  4)	/* 11 Bits */
-#define		AT91C_SPI_BITS_12		(0x4 <<  4)	/* 12 Bits */
-#define		AT91C_SPI_BITS_13		(0x5 <<  4)	/* 13 Bits */
-#define		AT91C_SPI_BITS_14		(0x6 <<  4)	/* 14 Bits */
-#define		AT91C_SPI_BITS_15		(0x7 <<  4)	/* 15 Bits */
-#define		AT91C_SPI_BITS_16		(0x8 <<  4)	/* 16 Bits */
-#define AT91C_SPI_SCBR		(0xFF <<  8)	/* Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS		(0xFF << 16)	/* Delay Before SPCK */
-#define AT91C_SPI_DLYBCT	(0xFF << 24)	/* Delay Between Transfers */
-/* SPI_PTCR : PDC Transfer Control Register */
-#define AT91C_PDC_RXTEN		(0x1 <<  0)	/* Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS	(0x1 <<  1)	/* Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN		(0x1 <<  8)	/* Transm. Transfer Enable */
-#define AT91C_PDC_TXTDIS	(0x1 <<  9)	/* Transm. Transfer Disable */
-
-/* PIO definitions */
-#define AT91C_PIO_PA0		(1 <<  0)	/* Pin Controlled by PA0 */
-#define AT91C_PA0_SPI0_MISO	AT91C_PIO_PA0
-#define AT91C_PIO_PA1		(1 <<  1)	/* Pin Controlled by PA1 */
-#define AT91C_PA1_SPI0_MOSI	AT91C_PIO_PA1
-#define AT91C_PIO_PA2		(1 <<  2)	/* Pin Controlled by PA2 */
-#define AT91C_PA2_SPI0_SPCK	AT91C_PIO_PA2
-#define AT91C_PIO_PA3		(1 <<  3)	/* Pin Controlled by PA3 */
-#define AT91C_PA3_SPI0_NPCS1	AT91C_PIO_PA3
-#define AT91C_PIO_PA4		(1 <<  4)	/* Pin Controlled by PA4 */
-#define AT91C_PA4_SPI0_NPCS2A	AT91C_PIO_PA4
-#define AT91C_PIO_PA5		(1 <<  5)	/* Pin Controlled by PA5 */
-#define AT91C_PA5_SPI0_NPCS0	AT91C_PIO_PA5
-#define AT91C_PIO_PA10		(1 << 10)	/* Pin Controlled by PA10 */
-#define AT91C_PIO_PA11		(1 << 11)	/* Pin Controlled by PA11 */
-#define AT91C_PIO_PA22		(1 << 22)	/* Pin Controlled by PA22 */
-#define AT91C_PA22_TXD0		AT91C_PIO_PA22
-#define AT91C_PIO_PA23		(1 << 23)	/* Pin Controlled by PA23 */
-#define AT91C_PA23_RXD0		AT91C_PIO_PA23
-#define AT91C_PIO_PA28		(1 << 28)	/* Pin Controlled by PA28 */
-#define AT91C_PA28_SPI0_NPCS3A	AT91C_PIO_PA28
-#define AT91C_PIO_PB21		(1 << 21)	/* Pin Controlled by PB21 */
-#define AT91C_PB21_E_TXCK	AT91C_PIO_PB21
-#define AT91C_PIO_PB22		(1 << 22)	/* Pin Controlled by PB22 */
-#define AT91C_PB22_E_RXDV	AT91C_PIO_PB22
-#define AT91C_PIO_PB23		(1 << 23)	/* Pin Controlled by PB23 */
-#define AT91C_PB23_E_TX0	AT91C_PIO_PB23
-#define AT91C_PIO_PB24		(1 << 24)	/* Pin Controlled by PB24 */
-#define AT91C_PB24_E_TX1	AT91C_PIO_PB24
-#define AT91C_PIO_PB25		(1 << 25)	/* Pin Controlled by PB25 */
-#define AT91C_PB25_E_RX0	AT91C_PIO_PB25
-#define AT91C_PIO_PB26		(1 << 26)	/* Pin Controlled by PB26 */
-#define AT91C_PB26_E_RX1	AT91C_PIO_PB26
-#define AT91C_PIO_PB27		(1 << 27)	/* Pin Controlled by PB27 */
-#define AT91C_PB27_E_RXER	AT91C_PIO_PB27
-#define AT91C_PIO_PB28		(1 << 28)	/* Pin Controlled by PB28 */
-#define AT91C_PB28_E_TXEN	AT91C_PIO_PB28
-#define AT91C_PIO_PB29		(1 << 29)	/* Pin Controlled by PB29 */
-#define AT91C_PB29_E_MDC	AT91C_PIO_PB29
-#define AT91C_PIO_PB30		(1 << 30)	/* Pin Controlled by PB30 */
-#define AT91C_PB30_E_MDIO	AT91C_PIO_PB30
-#define AT91C_PIO_PB31		(1 << 31)	/* Pin Controlled by PB31 */
-#define AT91C_PIO_PC29		(1 << 29)	/* Pin Controlled by PC29 */
-#define AT91C_PIO_PC30		(1 << 30)	/* Pin Controlled by PC30 */
-#define AT91C_PC30_DRXD		AT91C_PIO_PC30
-#define AT91C_PIO_PC31		(1 << 31)	/* Pin Controlled by PC31 */
-#define AT91C_PC31_DTXD		AT91C_PIO_PC31
-#define AT91C_PIO_PD0		(1 <<  0)	/* Pin Controlled by PD0 */
-#define AT91C_PD0_TXD1		AT91C_PIO_PD0
-#define AT91C_PD0_SPI0_NPCS2D	AT91C_PIO_PD0
-#define AT91C_PIO_PD1		(1 <<  1)	/* Pin Controlled by PD1 */
-#define AT91C_PD1_RXD1		AT91C_PIO_PD1
-#define AT91C_PD1_SPI0_NPCS3D	AT91C_PIO_PD1
-#define AT91C_PIO_PD2		(1 <<  2)	/* Pin Controlled by PD2 */
-#define AT91C_PD2_TXD2		AT91C_PIO_PD2
-#define AT91C_PIO_PD3		(1 <<  3)	/* Pin Controlled by PD3 */
-#define AT91C_PD3_RXD2		AT91C_PIO_PD3
-#define AT91C_PIO_PD15		(1 << 15)	/* Pin Controlled by PD15 */
-
-/* Peripheral ID */
-#define AT91C_ID_SYS		 1	/* System Controller */
-#define AT91C_ID_PIOABCD	 2	/* Parallel IO Controller A, B, C, D */
-#define AT91C_ID_US0		 8	/* USART 0 */
-#define AT91C_ID_US1		 9	/* USART 1 */
-#define AT91C_ID_US2		10	/* USART 2 */
-#define AT91C_ID_SPI0		15	/* Serial Peripheral Interface 0 */
-#define AT91C_ID_EMAC		22	/* Ethernet Mac */
-#define AT91C_ID_UHP		29	/* USB Host Port */
-
-/* Base addresses */
-#define AT91C_BASE_SMC		((AT91PS_SMC)	0xFFFFE800)	/* SMC */
-#define AT91C_BASE_CCFG		((AT91PS_CCFG)	0xFFFFEB10)	/* CCFG */
-#define AT91C_BASE_DBGU		((unsigned long)0xFFFFEE00)	/* DBGU */
-#define AT91C_BASE_PIOA		((AT91PS_PIO)	0xFFFFF200)	/* PIOA */
-#define AT91C_BASE_PIOB		((AT91PS_PIO)	0xFFFFF400)	/* PIOB */
-#define AT91C_BASE_PIOC		((AT91PS_PIO)	0xFFFFF600)	/* PIOC */
-#define AT91C_BASE_PIOD		((AT91PS_PIO)	0xFFFFF800)	/* PIOD */
-#define AT91C_BASE_PMC		((AT91PS_PMC)	0xFFFFFC00)	/* PMC */
-#define AT91C_BASE_RSTC		((AT91PS_RSTC)	0xFFFFFD00)	/* RSTC */
-#define AT91C_BASE_PITC		((AT91PS_PITC)	0xFFFFFD30)	/* PITC */
-#define AT91C_BASE_US0		((unsigned long)0xFFF8C000)	/* US0 */
-#define AT91C_BASE_US1		((unsigned long)0xFFF90000)	/* US1 */
-#define AT91C_BASE_US2		((unsigned long)0xFFF94000)	/* US2 */
-#define AT91C_BASE_SPI0		((AT91PS_SPI)	0xFFFA4000)	/* SPI0 */
-#define AT91C_BASE_MACB		((unsigned long)0xFFFBC000)	/* MACB */
-
-#endif

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+/*
+ * include/asm-arm/arch-at91/at91_pio.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Parallel I/O Controller (PIO) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIO_H
+#define AT91_PIO_H
+
+#define PIO_PER		0x00	/* Enable Register */
+#define PIO_PDR		0x04	/* Disable Register */
+#define PIO_PSR		0x08	/* Status Register */
+#define PIO_OER		0x10	/* Output Enable Register */
+#define PIO_ODR		0x14	/* Output Disable Register */
+#define PIO_OSR		0x18	/* Output Status Register */
+#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
+#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
+#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
+#define PIO_SODR	0x30	/* Set Output Data Register */
+#define PIO_CODR	0x34	/* Clear Output Data Register */
+#define PIO_ODSR	0x38	/* Output Data Status Register */
+#define PIO_PDSR	0x3c	/* Pin Data Status Register */
+#define PIO_IER		0x40	/* Interrupt Enable Register */
+#define PIO_IDR		0x44	/* Interrupt Disable Register */
+#define PIO_IMR		0x48	/* Interrupt Mask Register */
+#define PIO_ISR		0x4c	/* Interrupt Status Register */
+#define PIO_MDER	0x50	/* Multi-driver Enable Register */
+#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
+#define PIO_MDSR	0x58	/* Multi-driver Status Register */
+#define PIO_PUDR	0x60	/* Pull-up Disable Register */
+#define PIO_PUER	0x64	/* Pull-up Enable Register */
+#define PIO_PUSR	0x68	/* Pull-up Status Register */
+#define PIO_ASR		0x70	/* Peripheral A Select Register */
+#define PIO_BSR		0x74	/* Peripheral B Select Register */
+#define PIO_ABSR	0x78	/* AB Status Register */
+#define PIO_OWER	0xa0	/* Output Write Enable Register */
+#define PIO_OWDR	0xa4	/* Output Write Disable Register */
+#define PIO_OWSR	0xa8	/* Output Write Status Register */
+
+#endif

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+/*
+ * include/asm-arm/arch-at91/at91_pit.h
+ *
+ * Periodic Interval Timer (PIT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIT_H
+#define AT91_PIT_H
+
+#define AT91_PIT_MR		(AT91_PIT + 0x00)	/* Mode Register */
+#define		AT91_PIT_PITIEN		(1 << 25)		/* Timer Interrupt Enable */
+#define		AT91_PIT_PITEN		(1 << 24)		/* Timer Enabled */
+#define		AT91_PIT_PIV		(0xfffff)		/* Periodic Interval Value */
+
+#define AT91_PIT_SR		(AT91_PIT + 0x04)	/* Status Register */
+#define		AT91_PIT_PITS		(1 << 0)		/* Timer Status */
+
+#define AT91_PIT_PIVR		(AT91_PIT + 0x08)	/* Periodic Interval Value Register */
+#define AT91_PIT_PIIR		(AT91_PIT + 0x0c)	/* Periodic Interval Image Register */
+#define		AT91_PIT_PICNT		(0xfff << 20)		/* Interval Counter */
+#define		AT91_PIT_CPIV		(0xfffff)		/* Inverval Value */
+
+#endif

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+/*
+ * include/asm-arm/arch-at91/at91_rstc.h
+ *
+ * Reset Controller (RSTC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RSTC_H
+#define AT91_RSTC_H
+
+#define AT91_RSTC_CR		(AT91_RSTC + 0x00)	/* Reset Controller Control Register */
+#define		AT91_RSTC_PROCRST	(1 << 0)		/* Processor Reset */
+#define		AT91_RSTC_PERRST	(1 << 2)		/* Peripheral Reset */
+#define		AT91_RSTC_EXTRST	(1 << 3)		/* External Reset */
+#define		AT91_RSTC_KEY		(0xa5 << 24)		/* KEY Password */
+
+#define AT91_RSTC_SR		(AT91_RSTC + 0x04)	/* Reset Controller Status Register */
+#define		AT91_RSTC_URSTS		(1 << 0)		/* User Reset Status */
+#define		AT91_RSTC_RSTTYP	(7 << 8)		/* Reset Type */
+#define			AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
+#define			AT91_RSTC_RSTTYP_WAKEUP		(1 << 8)
+#define			AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
+#define			AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
+#define			AT91_RSTC_RSTTYP_USER	(4 << 8)
+#define		AT91_RSTC_NRSTL		(1 << 16)		/* NRST Pin Level */
+#define		AT91_RSTC_SRCMP		(1 << 17)		/* Software Reset Command in Progress */
+
+#define AT91_RSTC_MR		(AT91_RSTC + 0x08)	/* Reset Controller Mode Register */
+#define		AT91_RSTC_URSTEN	(1 << 0)		/* User Reset Enable */
+#define		AT91_RSTC_URSTIEN	(1 << 4)		/* User Reset Interrupt Enable */
+#define		AT91_RSTC_ERSTL		(0xf << 8)		/* External Reset Length */
+
+#endif

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index f9b9a84..aaad926 100644
@@ -78,4 +78,28 @@
 #define		AT91_SPI_DLYBS		(0xff << 16)		/* Delay before SPCK */
 #define		AT91_SPI_DLYBCT		(0xff << 24)		/* Delay between Consecutive Transfers */
 
+#define AT91_SPI_RPR		0x0100			/* Receive Pointer Register */
+
+#define AT91_SPI_RCR		0x0104			/* Receive Counter Register */
+
+#define AT91_SPI_TPR		0x0108			/* Transmit Pointer Register */
+
+#define AT91_SPI_TCR		0x010c			/* Transmit Counter Register */
+
+#define AT91_SPI_RNPR		0x0110			/* Receive Next Pointer Register */
+
+#define AT91_SPI_RNCR		0x0114			/* Receive Next Counter Register */
+
+#define AT91_SPI_TNPR		0x0118			/* Transmit Next Pointer Register */
+
+#define AT91_SPI_TNCR		0x011c			/* Transmit Next Counter Register */
+
+#define AT91_SPI_PTCR		0x0120			/* PDC Transfer Control Register */
+#define		AT91_SPI_RXTEN		(0x1 << 0)		/* Receiver Transfer Enable */
+#define		AT91_SPI_RXTDIS		(0x1 << 1)		/* Receiver Transfer Disable */
+#define		AT91_SPI_TXTEN		(0x1 << 8)		/* Transmitter Transfer Enable */
+#define		AT91_SPI_TXTDIS		(0x1 << 9)		/* Transmitter Transfer Disable */
+
+#define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
+
 #endif

index ca65a2a..86da9a6 100644
@@ -28,12 +28,12 @@
 
 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
 {
-	return AT91C_MASTER_CLOCK;
+	return AT91_MASTER_CLOCK;
 }
 
 static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
 {
-	return AT91C_MASTER_CLOCK;
+	return AT91_MASTER_CLOCK;
 }
 
 #endif /* __ASM_ARM_ARCH_CLK_H__ */

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index ec0a671..0d889ff 100644
@@ -1,28 +1,42 @@
 /*
- * (C) Copyright 2007
- * Stelian Pop <stelian.pop <at> leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
+ * include/asm-arm/arch-at91/hardware.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *  Copyright (C) 2003 ATMEL
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
+
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
 #include <asm/sizes.h>
 
-#include <asm/arch/AT91CAP9.h>
+#if defined(CONFIG_AT91RM9200)
+#include <asm/arch/at91rm9200.h>
+#elif defined(CONFIG_AT91SAM9260)
+#include <asm/arch/at91sam9260.h>
+#elif defined(CONFIG_AT91SAM9261)
+#include <asm/arch/at91sam9261.h>
+#elif defined(CONFIG_AT91SAM9263)
+#include <asm/arch/at91sam9263.h>
+#elif defined(CONFIG_AT91SAM9RL)
+#include <asm/arch/at91sam9rl.h>
+#elif defined(CONFIG_AT91CAP9)
+#include <asm/arch/at91cap9.h>
+#define AT91_BASE_EMAC	AT91CAP9_BASE_EMAC
+#define AT91_BASE_SPI	AT91CAP9_BASE_SPI0
+#define AT91_ID_UHP	AT91CAP9_ID_UHP
+#define AT91_PMC_UHP	AT91CAP9_PMC_UHP
+#elif defined(CONFIG_AT91X40)
+#include <asm/arch/at91x40.h>
+#else
+#error "Unsupported AT91 processor"
+#endif
 
 /*
  * container_of - cast a member of a structure out to the containing structure

new file mode 100644
index 0000000..be9e9ab
@@ -0,0 +1,40 @@
+/*
+ * include/asm-arm/arch-at91/io.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include <asm/io.h>
+
+static inline unsigned int at91_sys_read(unsigned int reg_offset)
+{
+	void *addr = (void *)AT91_BASE_SYS;
+
+	return __raw_readl(addr + reg_offset);
+}
+
+static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
+{
+	void *addr = (void *)AT91_BASE_SYS;
+
+	__raw_writel(value, addr + reg_offset);
+}
+
+#endif

index eee7bd6..da98822 100644
@@ -24,11 +24,11 @@
 #ifndef __ASM_ARM_ARCH_MEMORYMAP_H__
 #define __ASM_ARM_ARCH_MEMORYMAP_H__
 
-#include <asm/arch/AT91CAP9.h>
+#include <asm/arch/hardware.h>
 
-#define USART0_BASE AT91C_BASE_US0
-#define USART1_BASE AT91C_BASE_US1
-#define USART2_BASE AT91C_BASE_US2
-#define USART3_BASE AT91C_BASE_DBGU
+#define USART0_BASE AT91_USART0
+#define USART1_BASE AT91_USART1
+#define USART2_BASE AT91_USART2
+#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU)
 
 #endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */

index 52e62de..7444c5a 100644
@@ -23,7 +23,13 @@
  */
 
 #include <common.h>
-#include <asm/arch/AT91CAP9.h>
+#include <asm/arch/at91cap9.h>
+#include <asm/arch/at91cap9_matrix.h>
+#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif

@@ -40,183 +46,168 @@ DECLARE_GLOBAL_DATA_PTR;
 static void at91cap9_serial_hw_init(void)
 {
 #ifdef CONFIG_USART0
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
+	at91_set_A_periph(AT91_PIN_PA22, 1);		/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PA23, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
 #endif
 
 #ifdef CONFIG_USART1
-	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
+	at91_set_A_periph(AT91_PIN_PD0, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PD1, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
 #endif
 
 #ifdef CONFIG_USART2
-	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
+	at91_set_A_periph(AT91_PIN_PD2, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PD3, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
 #endif
 
 #ifdef CONFIG_USART3	/* DBGU */
-	AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
+	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
+	at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
 #endif
-
-
 }
 
 static void at91cap9_nor_hw_init(void)
 {
-	/* Ensure EBI supply is 3.3V */
-	AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
+	unsigned long csa;
 
+	/* Ensure EBI supply is 3.3V */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 	/* Configure SMC CS0 for parallel flash */
-	AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
-				     AT91C_FLASH_NCS_WR_SETUP |
-				     AT91C_FLASH_NRD_SETUP |
-				     AT91C_FLASH_NCS_RD_SETUP;
-
-	AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
-				     AT91C_FLASH_NCS_WR_PULSE |
-				     AT91C_FLASH_NRD_PULSE |
-				     AT91C_FLASH_NCS_RD_PULSE;
-
-	AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
-				     AT91C_FLASH_NRD_CYCLE;
-
-	AT91C_BASE_SMC->SMC_CTRL0 =  AT91C_SMC_READMODE |
-				     AT91C_SMC_WRITEMODE |
-				     AT91C_SMC_NWAITM_NWAIT_DISABLE |
-				     AT91C_SMC_BAT_BYTE_WRITE |
-				     AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
-				     (AT91C_SMC_TDF & (1 << 16));
+	at91_sys_write(AT91_SMC_SETUP(0),
+		       AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
+		       AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
+	at91_sys_write(AT91_SMC_PULSE(0),
+		       AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
+		       AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
+	at91_sys_write(AT91_SMC_CYCLE(0),
+		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
+	at91_sys_write(AT91_SMC_MODE(0),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
+		       AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
 }
 
 #ifdef CONFIG_CMD_NAND
 static void at91cap9_nand_hw_init(void)
 {
+	unsigned long csa;
+
 	/* Enable CS3 */
-	AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
+		       AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
-				     AT91C_SM_NCS_WR_SETUP |
-				     AT91C_SM_NRD_SETUP |
-				     AT91C_SM_NCS_RD_SETUP;
-
-	AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
-				     AT91C_SM_NCS_WR_PULSE |
-				     AT91C_SM_NRD_PULSE |
-				     AT91C_SM_NCS_RD_PULSE;
-
-	AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
-				     AT91C_SM_NRD_CYCLE;
-
-	AT91C_BASE_SMC->SMC_CTRL3 =  AT91C_SMC_READMODE |
-				     AT91C_SMC_WRITEMODE |
-				     AT91C_SMC_NWAITM_NWAIT_DISABLE |
-				     AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
-				     AT91C_SM_TDF;
-
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
+		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
+		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
 
 	/* RDY/BSY is not connected */
 
 	/* Enable NandFlash */
-	AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
-	AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
+	at91_set_gpio_output(AT91_PIN_PD15, 1);
 }
 #endif
 
 #ifdef CONFIG_HAS_DATAFLASH
 static void at91cap9_spi_hw_init(void)
 {
-	AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
-				   AT91C_PD1_SPI0_NPCS3D;
-	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
-				   AT91C_PD1_SPI0_NPCS3D;
-
-	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
-	AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
-				   AT91C_PA1_SPI0_MOSI |
-				   AT91C_PA0_SPI0_MISO |
-				   AT91C_PA3_SPI0_NPCS1 |
-				   AT91C_PA5_SPI0_NPCS0 |
-				   AT91C_PA2_SPI0_SPCK;
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
-				   AT91C_PA4_SPI0_NPCS2A |
-				   AT91C_PA1_SPI0_MOSI |
-				   AT91C_PA0_SPI0_MISO |
-				   AT91C_PA3_SPI0_NPCS1 |
-				   AT91C_PA5_SPI0_NPCS0 |
-				   AT91C_PA2_SPI0_SPCK;
-
-	/* Enable Clock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
+	at91_set_B_periph(AT91_PIN_PA5, 0);	/* SPI0_NPCS0 */
+
+	at91_set_B_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
+	at91_set_B_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
+	at91_set_B_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void at91cap9_macb_hw_init(void)
 {
-	unsigned int gpio;
-
 	/* Enable clock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
 
 	/*
 	 * Disable pull-up on:
 	 *	RXDV (PB22) => PHY normal mode (not Test mode)
-	 *	ERX0 (PB25) => PHY ADDR0
+	 * 	ERX0 (PB25) => PHY ADDR0
 	 *	ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
 	 *
 	 * PHY has internal pull-down
 	 */
-	AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
-				     AT91C_PB25_E_RX0 |
-				     AT91C_PB26_E_RX1;
+	writel(pin_to_mask(AT91_PIN_PB22) |
+	       pin_to_mask(AT91_PIN_PB25) |
+	       pin_to_mask(AT91_PIN_PB26),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 
 	/* Need to reset PHY -> 500ms reset */
-	AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
-				    (AT91C_RSTC_ERSTL & (0x0D << 8)) |
-				    AT91C_RSTC_URSTEN;
-	AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
-				    AT91C_RSTC_EXTRST;
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0D << 8) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 
 	/* Wait for end hardware reset */
-	while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 
 	/* Re-enable pull-up */
-	AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
-				     AT91C_PB25_E_RX0 |
-				     AT91C_PB26_E_RX1;
-
-#ifdef CONFIG_RMII
-	gpio =	AT91C_PB30_E_MDIO |
-		AT91C_PB29_E_MDC  |
-		AT91C_PB21_E_TXCK |
-		AT91C_PB27_E_RXER |
-		AT91C_PB25_E_RX0  |
-		AT91C_PB22_E_RXDV |
-		AT91C_PB26_E_RX1  |
-		AT91C_PB28_E_TXEN |
-		AT91C_PB23_E_TX0  |
-		AT91C_PB24_E_TX1;
-	AT91C_BASE_PIOB->PIO_ASR = gpio;
-	AT91C_BASE_PIOB->PIO_BSR = 0;
-	AT91C_BASE_PIOB->PIO_PDR = gpio;
-#else
-#error AT91CAP9A-DK works only in RMII mode
+	writel(pin_to_mask(AT91_PIN_PB22) |
+	       pin_to_mask(AT91_PIN_PB25) |
+	       pin_to_mask(AT91_PIN_PB26),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_set_A_periph(AT91_PIN_PB21, 0);	/* ETXCK_EREFCK */
+	at91_set_A_periph(AT91_PIN_PB22, 0);	/* ERXDV */
+	at91_set_A_periph(AT91_PIN_PB25, 0);	/* ERX0 */
+	at91_set_A_periph(AT91_PIN_PB26, 0);	/* ERX1 */
+	at91_set_A_periph(AT91_PIN_PB27, 0);	/* ERXER */
+	at91_set_A_periph(AT91_PIN_PB28, 0);	/* ETXEN */
+	at91_set_A_periph(AT91_PIN_PB23, 0);	/* ETX0 */
+	at91_set_A_periph(AT91_PIN_PB24, 0);	/* ETX1 */
+	at91_set_A_periph(AT91_PIN_PB30, 0);	/* EMDIO */
+	at91_set_A_periph(AT91_PIN_PB29, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_B_periph(AT91_PIN_PC25, 0);	/* ECRS */
+	at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
+	at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
+	at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
+	at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
+	at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
 #endif
-
 	/* Unlock EMAC, 3 0 2 1 sequence */
 #define MP_MAC_KEY0	0x5969cb2a
 #define MP_MAC_KEY1	0xb4a1872e
 #define MP_MAC_KEY2	0x05683fbc
 #define MP_MAC_KEY3	0x3634fba4
 #define UNLOCK_MAC	0x00000008
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
+	writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
+	writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
+	writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
+	writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
+	writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
 }
 #endif
 

@@ -229,11 +220,11 @@ static void at91cap9_uhp_hw_init(void)
 #define MP_OHCI_KEY2	0x4823efbc
 #define MP_OHCI_KEY3	0x8651aae4
 #define UNLOCK_OHCI	0x00000010
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
+	writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
+	writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
+	writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
+	writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
+	writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
 }
 #endif
 

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index 2f02126..1277973 100644
@@ -25,7 +25,9 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/at91cap9.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
 
 #ifdef CONFIG_CMD_NAND
 

@@ -51,10 +53,10 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
 		IO_ADDR_W |= MASK_ALE;
 		break;
 	case NAND_CTL_CLRNCE:
-		AT91C_BASE_PIOD->PIO_SODR = AT91C_PIO_PD15;
+		at91_set_gpio_value(AT91_PIN_PD15, 1);
 		break;
 	case NAND_CTL_SETNCE:
-		AT91C_BASE_PIOD->PIO_CODR = AT91C_PIO_PD15;
+		at91_set_gpio_value(AT91_PIN_PD15, 0);
 		break;
 	}
 	this->IO_ADDR_W = (void *) IO_ADDR_W;

index 8de1bb7..e4f5601 100644
@@ -30,6 +30,6 @@ extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
 #if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
 void at91sam9_eth_initialize(bd_t *bi)
 {
-	macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00);
+	macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
 }
 #endif

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index 79c135f..9d04769 100644
@@ -24,22 +24,24 @@
 
 #include <common.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/io.h>
 
 /*
  * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
  * setting the 20 bit counter period to its maximum (0xfffff).
  */
 #define TIMER_LOAD_VAL	0xfffff
-#define READ_RESET_TIMER (AT91C_BASE_PITC->PITC_PIVR)
-#define READ_TIMER (AT91C_BASE_PITC->PITC_PIIR)
+#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
+#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
 #define TIMER_FREQ (AT91C_MASTER_CLOCK << 4)
 #define TICKS_TO_USEC(ticks) ((ticks) / 6)
 
 ulong get_timer_masked(void);
 ulong resettime;
 
-AT91PS_PITC p_pitc;
-
 /* nothing really to do with interrupts, just starts up a counter. */
 int timer_init(void)
 {

@@ -47,13 +49,10 @@ int timer_init(void)
 	 * Enable PITC Clock
 	 * The clock is already enabled for system controller in boot
 	 */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
 
 	/* Enable PITC */
-	AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN;
-
-	/* Load PITC_PIMR with the right timer value */
-	AT91C_BASE_PITC->PITC_PIMR |= TIMER_LOAD_VAL;
+	at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN);
 
 	reset_timer_masked();
 

@@ -139,9 +138,9 @@ ulong get_tbclk(void)
 void reset_cpu(ulong ignored)
 {
 	/* this is the way Linux does it */
-	AT91C_BASE_RSTC->RSTC_RCR = (0xA5 << 24) |
-				    AT91C_RSTC_PROCRST |
-				    AT91C_RSTC_PERRST;
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
+				     AT91_RSTC_PROCRST |
+				     AT91_RSTC_PERRST);
 
 	while (1);
 	/* Never reached */

index 09292a6..d678897 100644
@@ -26,12 +26,14 @@
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
 
 #include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
+#include <asm/arch/at91_pmc.h>
 
 int usb_cpu_init(void)
 {
 	/* Enable USB host clock. */
-	AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UHP;
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_UHP;
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP);
+	at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP);
 
 	return 0;
 }

@@ -39,8 +41,8 @@ int usb_cpu_init(void)
 int usb_cpu_stop(void)
 {
 	/* Disable USB host clock. */
-	AT91C_BASE_PMC->PMC_PCDR = 1 << AT91C_ID_UHP;
-	AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_UHP;
+	at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP);
+	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP);
 	return 0;
 }
 

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index 9c98338..703784e 100644
@@ -417,13 +417,13 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 
 	/* choose RMII or MII mode. This depends on the board */
 #ifdef CONFIG_RMII
-#ifdef CONFIG_AT91CAP9ADK
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
 	macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
 #else
 	macb_writel(macb, USRIO, 0);
 #endif
 #else
-#ifdef CONFIG_AT91CAP9ADK
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
 	macb_writel(macb, USRIO, MACB_BIT(CLKEN));
 #else
 	macb_writel(macb, USRIO, MACB_BIT(MII));

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index 0d889ff..80b334f 100644
@@ -20,6 +20,10 @@
 #include <asm/arch/at91rm9200.h>
 #elif defined(CONFIG_AT91SAM9260)
 #include <asm/arch/at91sam9260.h>
+#define AT91_BASE_EMAC	AT91SAM9260_BASE_EMAC
+#define AT91_BASE_SPI	AT91SAM9260_BASE_SPI0
+#define AT91_ID_UHP	AT91SAM9260_ID_UHP
+#define AT91_PMC_UHP	AT91SAM926x_PMC_UHP
 #elif defined(CONFIG_AT91SAM9261)
 #include <asm/arch/at91sam9261.h>
 #elif defined(CONFIG_AT91SAM9263)

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index 1a98a91..99897ca 100644
@@ -284,7 +284,7 @@ int eth_initialize(bd_t *bis)
 #if defined(CONFIG_FSLDMAFEC)
 	mcdmafec_initialize(bis);
 #endif
-#if defined(CONFIG_AT91CAP9)
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
 	at91sam9_eth_initialize(bis);
 #endif
 

index f56443e..db5dec9 100644
@@ -41,6 +41,7 @@ int find_dev_and_part(const char *id, struct mtd_device **dev,
 		u8 *part_num, struct part_info **part);
 #endif
 
+#ifndef CFG_NO_FLASH
 extern flash_info_t flash_info[];	/* info for FLASH chips */
 
 /*

@@ -275,15 +276,19 @@ flash_fill_sect_ranges (ulong addr_first, ulong addr_last,
 
 	return rcode;
 }
+#endif /* CFG_NO_FLASH */
 
 int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
+#ifndef CFG_NO_FLASH
 	ulong bank;
+#endif
 
 #ifdef CONFIG_HAS_DATAFLASH
 	dataflash_print_info();
 #endif
 
+#ifndef CFG_NO_FLASH
 	if (argc == 1) {	/* print info for all FLASH banks */
 		for (bank=0; bank <CFG_MAX_FLASH_BANKS; ++bank) {
 			printf ("\nBank # %ld: ", bank+1);

@@ -301,11 +306,13 @@ int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 	printf ("\nBank # %ld: ", bank);
 	flash_print_info (&flash_info[bank-1]);
+#endif /* CFG_NO_FLASH */
 	return 0;
 }
 
 int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
+#ifndef CFG_NO_FLASH
 	flash_info_t *info;
 	ulong bank, addr_first, addr_last;
 	int n, sect_first, sect_last;

@@ -397,8 +404,12 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	rcode = flash_sect_erase(addr_first, addr_last);
 	return rcode;
+#else
+	return 0;
+#endif /* CFG_NO_FLASH */
 }
 
+#ifndef CFG_NO_FLASH
 int flash_sect_erase (ulong addr_first, ulong addr_last)
 {
 	flash_info_t *info;

@@ -439,12 +450,17 @@ int flash_sect_erase (ulong addr_first, ulong addr_last)
 	}
 	return rcode;
 }
+#endif /* CFG_NO_FLASH */
 
 int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
+#ifndef CFG_NO_FLASH
 	flash_info_t *info;
-	ulong bank, addr_first, addr_last;
-	int i, p, n, sect_first, sect_last;
+	ulong bank;
+	int i, n, sect_first, sect_last;
+#endif /* CFG_NO_FLASH */
+	ulong addr_first, addr_last;
+	int p;
 #if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
 	struct mtd_device *dev;
 	struct part_info *part;

@@ -487,6 +503,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 #endif
 
+#ifndef CFG_NO_FLASH
 	if (strcmp(argv[2], "all") == 0) {
 		for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) {
 			info = &flash_info[bank-1];

@@ -611,10 +628,11 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 	rcode = flash_sect_protect (p, addr_first, addr_last);
+#endif /* CFG_NO_FLASH */
 	return rcode;
 }
 
-
+#ifndef CFG_NO_FLASH
 int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
 {
 	flash_info_t *info;

@@ -667,6 +685,7 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
 	}
 	return rcode;
 }
+#endif /* CFG_NO_FLASH */
 
 
 /**************************************************/

index 4262e26..d6d7a5b 100644
@@ -492,7 +492,11 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 
 	/* Check if we are copying from DataFlash to RAM */
-	if (addr_dataflash(addr) && !addr_dataflash(dest) && (addr2info(dest)==NULL) ){
+	if (addr_dataflash(addr) && !addr_dataflash(dest)
+#ifndef CFG_NO_FLASH
+				 && (addr2info(dest) == NULL)
+#endif
+	   ){
 		int rc;
 		rc = read_dataflash(addr, count * size, (char *) dest);
 		if (rc != 1) {

index 36c99a0..79dc402 100644
@@ -31,7 +31,7 @@ struct dataflash_addr {
 	int cs;
 };
 
-#ifdef CONFIG_AT91SAM9260EK
+#if defined(CONFIG_AT91SAM9260EK)
 struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
 	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
 	{CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}

@@ -48,51 +48,13 @@ struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
 #endif
 
 /*define the area offsets*/
-#if defined(CONFIG_AT91SAM9261EK) || defined(CONFIG_AT91SAM9260EK) || \
-	defined(CONFIG_AT91SAM9263EK) || defined(CONFIG_AT91CAP9ADK)
-#if	defined(CONFIG_NEW_PARTITION)
 dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
-	{0x00000000,	0x00003FFF, 	FLAG_PROTECT_SET,	0,    		"Bootstrap"},  	/* ROM code */
-	{0x00004200,	0x000083FF, 	FLAG_PROTECT_CLEAR,	0,    		"Environment"},	/* u-boot environment */
-	{0x00008400,	0x0003DDFF,	FLAG_PROTECT_SET,	0,    		"U-Boot"},     	/* u-boot code */
-	{0x0003DE00,	0x00041FFF,	FLAG_PROTECT_CLEAR,	FLAG_SETENV,	"MON"},	       	/* Room for alternative boot monitor */
-	{0x00042000,	0x0018BFFF,	FLAG_PROTECT_CLEAR,	FLAG_SETENV,	"OS"},	       	/* data area size to tune */
-	{0x0018C000,	0xFFFFFFFF,	FLAG_PROTECT_CLEAR,	FLAG_SETENV,	"FS"},	       	/* data area size to tune */
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x0003DDFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x0003DE00, 0x0023DE3F, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x0023DE40, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
 };
-#else
-dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
-	{0, 0x3fff, FLAG_PROTECT_SET},			/* ROM code */
-	{0x4000, 0x7fff, FLAG_PROTECT_CLEAR},		/* u-boot environment */
-	{0x8000, 0x37fff, FLAG_PROTECT_SET},		/* u-boot code */
-	{0x38000, 0x1fffff, FLAG_PROTECT_CLEAR},	/* data area size to tune */
-};
-#endif
-#elif defined(CONFIG_NEW_PARTITION)
-/*define the area offsets*/
-/* Invalid partitions should be defined with start > end */
-dataflash_protect_t area_list[NB_DATAFLASH_AREA*CFG_MAX_DATAFLASH_BANKS] = {
-	{0x00000000, 0x000083ff, FLAG_PROTECT_SET,	0,		"Bootstrap"},	/* ROM code */
-	{0x00008400, 0x00020fff, FLAG_PROTECT_SET,	0,		"U-Boot"},	/* u-boot code */
-	{0x00021000, 0x000293ff, FLAG_PROTECT_CLEAR,	0,		"Environment"},	/* u-boot environment 8Kb */
-	{0x00029400, 0x00041fff, FLAG_PROTECT_INVALID,	0,		"<Unused>"},	/* Rest of Sector 1 */
-	{0x00042000, 0x0018Bfff, FLAG_PROTECT_CLEAR,	FLAG_SETENV,	"OS"},	/* data area size to tune */
-	{0x0018C000, 0xffffffff, FLAG_PROTECT_CLEAR,	FLAG_SETENV,	"FS"},	/* data area size to tune */
-
-	{0x00000000, 0xffffffff, FLAG_PROTECT_CLEAR,	FLAG_SETENV,	"Data"},	/* data area */
-	{0xffffffff, 0x00000000, FLAG_PROTECT_INVALID,	0,		"<Invalid>"},	/* Invalid */
-	{0xffffffff, 0x00000000, FLAG_PROTECT_INVALID,	0,		"<Invalid>"},	/* Invalid */
-	{0xffffffff, 0x00000000, FLAG_PROTECT_INVALID,	0,		"<Invalid>"},	/* Invalid */
-	{0xffffffff, 0x00000000, FLAG_PROTECT_INVALID,	0,		"<Invalid>"},	/* Invalid */
-	{0xffffffff, 0x00000000, FLAG_PROTECT_INVALID,	0,		"<Invalid>"},	/* Invalid */
-};
-#else
-dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
-	{0, 0x7fff, FLAG_PROTECT_SET},			/* ROM code */
-	{0x8000, 0x1ffff, FLAG_PROTECT_SET},		/* u-boot code */
-	{0x20000, 0x27fff, FLAG_PROTECT_CLEAR},		/* u-boot environment */
-	{0x28000, 0x1fffff, FLAG_PROTECT_CLEAR},	/* data area size to tune */
-};
-#endif
 
 extern void AT91F_SpiInit (void);
 extern int AT91F_DataflashProbe (int i, AT91PS_DataflashDesc pDesc);

@@ -108,7 +70,7 @@ int AT91F_DataflashInit (void)
 {
 	int i, j;
 	int dfcode;
-	int part = 0;
+	int part;
 	int last_part;
 	int found[CFG_MAX_DATAFLASH_BANKS];
 	unsigned char protected;

@@ -181,7 +143,8 @@ int AT91F_DataflashInit (void)
 				(dataflash_info[i].Device.pages_number *
 				dataflash_info[i].Device.pages_size)-1;
 
-		last_part=0;
+		part = 0;
+		last_part = 0;
 		/* set the area addresses */
 		for(j = 0; j<NB_DATAFLASH_AREA; j++) {
 			if(found[i]!=0) {

index fbd5e17..68f0324 100644
@@ -38,11 +38,7 @@
 #include "config.h"
 
 /*number of protected area*/
-#ifdef	CONFIG_NEW_PARTITION
-# define NB_DATAFLASH_AREA	6
-#else
-# define NB_DATAFLASH_AREA	4
-#endif
+#define NB_DATAFLASH_AREA		5
 
 #ifdef CFG_NO_FLASH